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Differential D46389

[mips][microMIPS] Move conditional moves out of isCodeGenOnly
ClosedPublic

Authored by sdardis on May 3 2018, 7:17 AM.

Details

Reviewers
atanasyan
smaksimovic
abeserminji
Commits
rGeead208872cb: [mips] Move conditional moves out of isCodeGenOnly
rL331863: [mips] Move conditional moves out of isCodeGenOnly

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.May 3 2018, 7:17 AM
Herald added a subscriber: arichardson. · View Herald TranscriptMay 3 2018, 7:17 AM
atanasyan accepted this revision.May 4 2018, 12:42 AM

LGTM

This revision is now accepted and ready to land.May 4 2018, 12:42 AM
Closed by commit rL331863: [mips] Move conditional moves out of isCodeGenOnly (authored by sdardis). · Explain WhyMay 9 2018, 3:37 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
46 lines
4 lines
8 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
8 lines
8 lines
Mips/
16 lines

Diff 145893

llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

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} }
def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>; defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>; defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
let isCodeGenOnly = 1 in { let DecoderNamespace = "MicroMips" in {
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
}
let isCodeGenOnly = 1 in {
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS; ISA_MICROMIPS;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS; ISA_MICROMIPS;
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 825 Lines • ▼ Show 20 Linesclass ABS_FM_MM<bits<2> fmt, bits<7> funct> : MMArch {
let Inst{14-13} = fmt; let Inst{14-13} = fmt;
let Inst{12-6} = funct; let Inst{12-6} = funct;
let Inst{5-0} = 0x3b; let Inst{5-0} = 0x3b;
} }
class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch { class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch {
bits<5> fd; bits<5> fd;
bits<5> fs; bits<5> fs;
bits<3> fcc;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x15; let Inst{31-26} = 0x15;
let Inst{25-21} = fd; let Inst{25-21} = fd;
let Inst{20-16} = fs; let Inst{20-16} = fs;
let Inst{15-13} = 0x0; //cc let Inst{15-13} = fcc; //cc
let Inst{12-11} = 0x0; let Inst{12-11} = 0x0;
let Inst{10-9} = fmt; let Inst{10-9} = fmt;
let Inst{8-0} = func; let Inst{8-0} = func;
} }
class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch { class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch {
bits<5> fd; bits<5> fd;
bits<5> fs; bits<5> fs;
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llvm/trunk/lib/Target/Mips/MipsCondMov.td

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let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>, def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>, def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>, def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
} }
let AdditionalPredicates = [NotInMicroMips] in {
def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
II_MOVZ_D>, CMov_I_F_FM<18, 17>, II_MOVZ_D>, CMov_I_F_FM<18, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
II_MOVN_D>, CMov_I_F_FM<19, 17>, II_MOVN_D>, CMov_I_F_FM<19, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
}
let DecoderNamespace = "MipsFP64" in { let DecoderNamespace = "MipsFP64" in {
def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>, def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
Show All 10 Linesdef MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
let AdditionalPredicates = [NotInMicroMips] in {
def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;
def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM<17, 1>, MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM<17, 0>, MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
}
let DecoderNamespace = "MipsFP64" in { let DecoderNamespace = "MipsFP64" in {
def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
} }
// Instantiation of conditional move patterns. // Instantiation of conditional move patterns.
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llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

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0x85 0x60 0x10 0x00 # CHECK: lwl $4, 16($5) 0x85 0x60 0x10 0x00 # CHECK: lwl $4, 16($5)
0x85 0x60 0x10 0x10 # CHECK: lwr $4, 16($5) 0x85 0x60 0x10 0x10 # CHECK: lwr $4, 16($5)
0x85 0x60 0x10 0x80 # CHECK: swl $4, 16($5) 0x85 0x60 0x10 0x80 # CHECK: swl $4, 16($5)
0x85 0x60 0x10 0x90 # CHECK: swr $4, 16($5) 0x85 0x60 0x10 0x90 # CHECK: swr $4, 16($5)
0xe6 0x00 0x58 0x48 # CHECK: movz $9, $6, $7 0xe6 0x00 0x58 0x48 # CHECK: movz $9, $6, $7
0xe6 0x00 0x18 0x48 # CHECK: movn $9, $6, $7 0xe6 0x00 0x18 0x48 # CHECK: movn $9, $6, $7
0x26 0x55 0x7b 0x09 # CHECK: movt $9, $6, $fcc0 0x26 0x55 0x7b 0x09 # CHECK: movt $9, $6, $fcc0
0x26 0x55 0x7b 0x01 # CHECK: movf $9, $6, $fcc0 0x26 0x55 0x7b 0x01 # CHECK: movf $9, $6, $fcc0
0xe6 0x54 0x78 0x20 # CHECK: movz.s $f4, $f6, $7
0xe6 0x54 0x78 0x21 # CHECK: movz.d $f4, $f6, $7
0xe6 0x54 0x38 0x20 # CHECK: movn.s $f4, $f6, $7
0xe6 0x54 0x38 0x21 # CHECK: movn.d $f4, $f6, $7
0x86 0x54 0x60 0x00 # CHECK: movt.s $f4, $f6, $fcc0
0x86 0x54 0x60 0x02 # CHECK: movt.d $f4, $f6, $fcc0
0x86 0x54 0x20 0x00 # CHECK: movf.s $f4, $f6, $fcc0
0x86 0x54 0x20 0x02 # CHECK: movf.d $f4, $f6, $fcc0
0x06 0x00 0x7c 0x2d # CHECK: mthi $6 0x06 0x00 0x7c 0x2d # CHECK: mthi $6
0x06 0x00 0x7c 0x0d # CHECK: mfhi $6 0x06 0x00 0x7c 0x0d # CHECK: mfhi $6
0x06 0x00 0x7c 0x3d # CHECK: mtlo $6 0x06 0x00 0x7c 0x3d # CHECK: mtlo $6
0x06 0x00 0x7c 0x1d # CHECK: mflo $6 0x06 0x00 0x7c 0x1d # CHECK: mflo $6
0xa4 0x00 0x3c 0xcb # CHECK: madd $4, $5 0xa4 0x00 0x3c 0xcb # CHECK: madd $4, $5
0xa4 0x00 0x3c 0xdb # CHECK: maddu $4, $5 0xa4 0x00 0x3c 0xdb # CHECK: maddu $4, $5
0xa4 0x00 0x3c 0xeb # CHECK: msub $4, $5 0xa4 0x00 0x3c 0xeb # CHECK: msub $4, $5
0xa4 0x00 0x3c 0xfb # CHECK: msubu $4, $5 0xa4 0x00 0x3c 0xfb # CHECK: msubu $4, $5
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llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

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0x60 0x85 0x00 0x10 # CHECK: lwl $4, 16($5) 0x60 0x85 0x00 0x10 # CHECK: lwl $4, 16($5)
0x60 0x85 0x10 0x10 # CHECK: lwr $4, 16($5) 0x60 0x85 0x10 0x10 # CHECK: lwr $4, 16($5)
0x60 0x85 0x80 0x10 # CHECK: swl $4, 16($5) 0x60 0x85 0x80 0x10 # CHECK: swl $4, 16($5)
0x60 0x85 0x90 0x10 # CHECK: swr $4, 16($5) 0x60 0x85 0x90 0x10 # CHECK: swr $4, 16($5)
0x00 0xe6 0x48 0x58 # CHECK: movz $9, $6, $7 0x00 0xe6 0x48 0x58 # CHECK: movz $9, $6, $7
0x00 0xe6 0x48 0x18 # CHECK: movn $9, $6, $7 0x00 0xe6 0x48 0x18 # CHECK: movn $9, $6, $7
0x55 0x26 0x09 0x7b # CHECK: movt $9, $6, $fcc0 0x55 0x26 0x09 0x7b # CHECK: movt $9, $6, $fcc0
0x55 0x26 0x01 0x7b # CHECK: movf $9, $6, $fcc0 0x55 0x26 0x01 0x7b # CHECK: movf $9, $6, $fcc0
0x54 0xe6 0x20 0x78 # CHECK: movz.s $f4, $f6, $7
0x54 0xe6 0x21 0x78 # CHECK: movz.d $f4, $f6, $7
0x54 0xe6 0x20 0x38 # CHECK: movn.s $f4, $f6, $7
0x54 0xe6 0x21 0x38 # CHECK: movn.d $f4, $f6, $7
0x54 0x86 0x00 0x60 # CHECK: movt.s $f4, $f6, $fcc0
0x54 0x86 0x02 0x60 # CHECK: movt.d $f4, $f6, $fcc0
0x54 0x86 0x00 0x20 # CHECK: movf.s $f4, $f6, $fcc0
0x54 0x86 0x02 0x20 # CHECK: movf.d $f4, $f6, $fcc0
0x00 0x06 0x2d 0x7c # CHECK: mthi $6 0x00 0x06 0x2d 0x7c # CHECK: mthi $6
0x00 0x06 0x0d 0x7c # CHECK: mfhi $6 0x00 0x06 0x0d 0x7c # CHECK: mfhi $6
0x00 0x06 0x3d 0x7c # CHECK: mtlo $6 0x00 0x06 0x3d 0x7c # CHECK: mtlo $6
0x00 0x06 0x1d 0x7c # CHECK: mflo $6 0x00 0x06 0x1d 0x7c # CHECK: mflo $6
0x00 0xa4 0xcb 0x3c # CHECK: madd $4, $5 0x00 0xa4 0xcb 0x3c # CHECK: madd $4, $5
0x00 0xa4 0xdb 0x3c # CHECK: maddu $4, $5 0x00 0xa4 0xdb 0x3c # CHECK: maddu $4, $5
0x00 0xa4 0xeb 0x3c # CHECK: msub $4, $5 0x00 0xa4 0xeb 0x3c # CHECK: msub $4, $5
0x00 0xa4 0xfb 0x3c # CHECK: msubu $4, $5 0x00 0xa4 0xfb 0x3c # CHECK: msubu $4, $5
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llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s

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# CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b] # CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10] # CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18] # CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20] # CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
# CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28] # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30] # CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38] # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20] # CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21] # CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM
# CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20] # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM
# CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21] # CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM
# CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00] # CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM
# CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02] # CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVT_D32_MM
# CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00] # CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM
# CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02] # CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
# CHECK-EL: madd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x01,0x11] # CHECK-EL: madd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x01,0x11]
# CHECK-EL: madd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x09,0x11] # CHECK-EL: madd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x09,0x11]
# CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11] # CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11]
# CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11] # CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11]
# CHECK-EL: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x02,0x11] # CHECK-EL: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x02,0x11]
# CHECK-EL: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x0a,0x11] # CHECK-EL: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x0a,0x11]
# CHECK-EL: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x22,0x11] # CHECK-EL: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x22,0x11]
# CHECK-EL: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x2a,0x11] # CHECK-EL: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x2a,0x11]
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# CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b] # CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b]
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b] # CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b] # CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b] # CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
# CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b] # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b] # CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b] # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78] # CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78] # CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM
# CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38] # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM
# CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38] # CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM
# CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60] # CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM
# CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60] # CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_D32_MM
# CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20] # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20] # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
# CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01] # CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
# CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09] # CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
# CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21] # CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
# CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29] # CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
# CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02] # CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02]
# CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a] # CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a]
# CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22] # CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22]
# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a] # CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
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