[Power9]Legalize and emit code for DW vector extract and convert to Quad-Precision

[lei]

Summary

Implemente patterns to extract DW vector elements and convert to QP

[nemanjai]

If the definition of the new instruction can be avoided, feel free to do so on the commit. If it can't, add a comment as to why it is necessary in the code.
Other than that, LGTM.

lib/Target/PowerPC/PPCInstrVSX.td

3163

I am curious why we need another CodeGenOnly instruction here. It seems that for the version that doesn't require the splat, you can just accomplish what is necessary with a COPY_TO_REGCLASS. Why can't the output pattern here be something like:
(f128 (XSCVSDQP (COPY_TO_REGCLASS (XXPERMDI $src, $src, 3), VFRC)))

[lei]

Remove extra CodeGenOnly pattern and update pattern with EXTRACT_SUBREG.

lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
     XXPERM,
     XXPERMR,
     XXSLDWI,
     XXSPLTIB,
     XXSPLTW,
     XXSPLTWs,
     XXPERMDI,
     XXPERMDIs,
+    XXPERMDIq,
     VADDCUQ,
     VADDECUQ,
     VADDEUQM,
     VADDUQM,
     VMUL10CUQ,
     VMUL10ECUQ,
     VMUL10EUQ,
     VMUL10UQ,

lib/Target/PowerPC/PPCInstrVSX.td

let Uses = [RM] in {
   def XXPERMDI : XX3Form_2<60, 10,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
                        "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm,
                        [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
                          imm32SExt16:$DM))]>;
   let isCodeGenOnly = 1 in
   def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
+  let isCodeGenOnly = 1 in
+  def XXPERMDIq : XX3Form_2s<60, 10, (outs vsfrc:$XT), (ins vsrc:$XA, u2imm:$DM),
+                             "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
   def XXSEL : XX4Form<60, 3,
                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
                       "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
 
   def XXSLDWI : XX3Form_2<60, 2,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
                        "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm,
                        [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB,

 def : InstAlias<"xxswapd $XT, $XB",
                 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
 def : InstAlias<"xxspltd $XT, $XB, 0",
                 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;
 def : InstAlias<"xxspltd $XT, $XB, 1",
                 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
 def : InstAlias<"xxswapd $XT, $XB",
                 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
+def : InstAlias<"xxspltd $XT, $XB, 0",
+                (XXPERMDIq vsfrc:$XT, vsrc:$XB, 0)>;
+def : InstAlias<"xxspltd $XT, $XB, 1",
+                (XXPERMDIq vsfrc:$XT, vsrc:$XB, 3)>;
 
 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
 
 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
 let Predicates = [IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
def DFSTOREf64 : Pseudo<(outs), (ins vsfrc:$XT, memrix:$dst),
                             "#DFSTOREf64",
                             [(store f64:$XT, ixaddr:$dst)]>;
   }
   def : Pat<(f64 (extloadf32 ixaddr:$src)),
             (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>;
   def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
             (f32 (DFLOADf32 ixaddr:$src))>;
 
+  let Predicates = [IsBigEndian] in {
+    def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
+              (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+    def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
+              (f128 (XSCVSDQP (XXPERMDIq $src, 3)))>;
+    def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
+              (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+    def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
+              (f128 (XSCVUDQP (XXPERMDIq $src, 3)))>;
+  }
+
+  let Predicates = [IsLittleEndian] in {
+    def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
+              (f128 (XSCVSDQP (XXPERMDIq $src, 3)))>;
+    def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
+              (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+    def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
+              (f128 (XSCVUDQP (XXPERMDIq $src, 3)))>;
+    def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
+              (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+  }
+
   // Convert (Un)Signed DWord in memory -> QP
   def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))),
             (f128 (XSCVSDQP (LXSDX xaddr:$src)))>;
   def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))),
             (f128 (XSCVSDQP (LXSD ixaddr:$src)))>;
   def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))),
             (f128 (XSCVUDQP (LXSDX xaddr:$src)))>;
   def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))),

test/CodeGen/PowerPC/f128-vecExtractNconv.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs -enable-ppc-quad-precision < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
+; RUN:   -verify-machineinstrs -enable-ppc-quad-precision < %s | \
+; RUN:   FileCheck %s -check-prefix=CHECK-BE
+
+@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
+@udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
+
+; Function Attrs: norecurse nounwind
+define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
+; CHECK-LABEL: sdwVecConv2qp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxspltd 34, 34, 1
+; CHECK-NEXT:    xscvsdqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+
+; CHECK-BE-LABEL: sdwVecConv2qp:
+; CHECK-BE:    xscvsdqp 2, 2
+; CHECK-BE-NEXT:    stxv 34, 0(3)
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <2 x i64> %b, i32 0
+  %conv = sitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) {
+; CHECK-LABEL: sdwVecConv2qp1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvsdqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+
+; CHECK-BE-LABEL: sdwVecConv2qp1:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxspltd 34, 34, 1
+; CHECK-BE-NEXT:    xscvsdqp 2, 2
+; CHECK-BE-NEXT:    stxv 34, 0(3)
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <2 x i64> %b, i32 1
+  %conv = sitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwVecConv2qp_02(fp128* nocapture %a) {
+; CHECK-LABEL: sdwVecConv2qp_02:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 4, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 4, .LC0@toc@l(4)
+; CHECK-NEXT:    lxsd 2, 0(4)
+; CHECK-NEXT:    xscvsdqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <2 x i64>, <2 x i64>* @sdwVecMem, align 16
+  %vecext = extractelement <2 x i64> %0, i32 0
+  %conv = sitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwVecConv2qp1_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) {
+; CHECK-LABEL: sdwVecConv2qp1_03:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxsd 2, 8(4)
+; CHECK-NEXT:    xscvsdqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %b, align 16
+  %vecext = extractelement <2 x i64> %0, i32 1
+  %conv = sitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
+; CHECK-LABEL: udwVecConv2qp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxspltd 34, 34, 1
+; CHECK-NEXT:    xscvudqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+
+; CHECK-BE-LABEL: udwVecConv2qp:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xscvudqp 2, 2
+; CHECK-BE-NEXT:    stxv 34, 0(3)
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <2 x i64> %b, i32 0
+  %conv = uitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) {
+; CHECK-LABEL: udwVecConv2qp1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvudqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+
+; CHECK-BE-LABEL: udwVecConv2qp1:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxspltd 34, 34, 1
+; CHECK-BE-NEXT:    xscvudqp 2, 2
+; CHECK-BE-NEXT:    stxv 34, 0(3)
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <2 x i64> %b, i32 1
+  %conv = uitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwVecConv2qp1_02(fp128* nocapture %a) {
+; CHECK-LABEL: udwVecConv2qp1_02:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 4, .LC1@toc@l(4)
+; CHECK-NEXT:    lxsd 2, 8(4)
+; CHECK-NEXT:    xscvudqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <2 x i64>, <2 x i64>* @udwVecMem, align 16
+  %vecext = extractelement <2 x i64> %0, i32 1
+  %conv = uitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwVecConv2qp_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) {
+; CHECK-LABEL: udwVecConv2qp_03:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxsd 2, 0(4)
+; CHECK-NEXT:    xscvudqp 2, 2
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %b, align 16
+  %vecext = extractelement <2 x i64> %0, i32 0
+  %conv = uitofp i64 %vecext to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+}