Correctly assemble unsized call instructions.

[jrmuizel]

Summary

This adds a new kind X86MemOperand that will only match MemOperands with no
size if the default size (i.e. mode) matches the size of the memory operand.
This keeps us from matching the 16 bit call instruction when we're in 32 bit
mode.

[rnk]

Oops, I wrote these comments and never sent them. :(

lib/Target/X86/AsmParser/X86AsmParser.cpp

1557

I assume this is intended to be uncommented?

lib/Target/X86/AsmParser/X86Operand.h

213

Returning true for Size == 0 seems suspect to me. What tests fail if we remove that clause? My guess is that we start failing to match instructions like 'mov %eax, (%ebx)', because now isMem32 will return false for '(%ebx)'.

I think maybe the real fix is to remove this clause, and then add an 'isMemUnsized()' predicate, which the asm matcher uses to figure out memory operand sizes when the size is implied by the at&t size suffix (movll, movw) or the size of another operand (mov %eax, (%ebx)).

test/MC/X86/intel-syntax-unsized-operand.s

11

What do we do for other instructions that take a single memory operand, like 'inc' and 'dec'?

[jrmuizel]

lib/Target/X86/AsmParser/X86Operand.h

213

Correct. We start to fail to match mov eax, [ebx].

The asm matcher currently only looks at one operand at a time, from left to right so I'm not sure how we'd do the matching for something like mov [ebx], eax?

test/MC/X86/intel-syntax-unsized-operand.s

11

Currently they probably end up as incw, decw. mov [eax], 1 ends up as mov word ptr [eax] 1. In MSVC they all become 'byte pointer' accesses, other assemblers including ml seem to reject them.

[lhames]

Ping - what's the state of this? Can we close it?

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
     if (Op.isMem())
       InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
   }
 }
 
 class X86AddressSanitizer32 : public X86AddressSanitizer {
 public:
   static const long kShadowOffset = 0x20000000;
+  static const unsigned kDefaultMemSize = 32;
 
   X86AddressSanitizer32(const MCSubtargetInfo &STI)
       : X86AddressSanitizer(STI) {}
   virtual ~X86AddressSanitizer32() {}
 
   virtual void InstrumentMemOperandSmallImpl(
       X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
       MCStreamer &Out) override;
EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
                            .addReg(X86::ECX).addImm(3));
 
   {
     MCInst Inst;
     Inst.setOpcode(X86::MOV8rm);
     Inst.addOperand(MCOperand::CreateReg(X86::CL));
     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     EmitInstruction(Out, Inst);
   }
 
   EmitInstruction(Out,
                   MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL));
   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
case 1:
     break;
   case 2: {
     MCInst Inst;
     Inst.setOpcode(X86::LEA32r);
     Inst.addOperand(MCOperand::CreateReg(X86::EDX));
 
     const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     EmitInstruction(Out, Inst);
     break;
   }
   case 4:
     EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX)
                              .addReg(X86::EDX).addImm(3));
     break;
switch (AccessSize) {
         Inst.setOpcode(X86::CMP16mi);
         break;
       default:
         assert(false && "Incorrect access size");
         break;
     }
     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     Inst.addOperand(MCOperand::CreateImm(0));
     EmitInstruction(Out, Inst);
   }
   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 
public:
   virtual ~X86AddressSanitizer64() {}
 
   virtual void InstrumentMemOperandSmallImpl(
       X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
       MCStreamer &Out) override;
   virtual void InstrumentMemOperandLargeImpl(
       X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
       MCStreamer &Out) override;
+  static const unsigned kDefaultMemSize = 64;
 
 private:
   void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
     MCInst Inst;
     Inst.setOpcode(X86::LEA64r);
     Inst.addOperand(MCOperand::CreateReg(X86::RSP));
 
     const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     EmitInstruction(Out, Inst);
   }
 
   void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
                           bool IsWrite) {
     EmitInstruction(Out, MCInstBuilder(X86::CLD));
     EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
   EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
                            .addReg(X86::RAX).addImm(3));
   {
     MCInst Inst;
     Inst.setOpcode(X86::MOV8rm);
     Inst.addOperand(MCOperand::CreateReg(X86::AL));
     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     EmitInstruction(Out, Inst);
   }
 
   EmitInstruction(Out,
                   MCInstBuilder(X86::TEST8rr).addReg(X86::AL).addReg(X86::AL));
   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
case 1:
     break;
   case 2: {
     MCInst Inst;
     Inst.setOpcode(X86::LEA32r);
     Inst.addOperand(MCOperand::CreateReg(X86::ECX));
 
     const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     EmitInstruction(Out, Inst);
     break;
   }
   case 4:
     EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX)
                              .addReg(X86::ECX).addImm(3));
     break;
case 16:
       Inst.setOpcode(X86::CMP16mi);
       break;
     default:
       assert(false && "Incorrect access size");
       break;
     }
     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
     std::unique_ptr<X86Operand> Op(
-        X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
+        X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc(), kDefaultMemSize));
     Op->addMemOperands(Inst, 5);
     Inst.addOperand(MCOperand::CreateImm(0));
     EmitInstruction(Out, Inst);
   }
 
   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));

lib/Target/X86/AsmParser/X86AsmParser.cpp

private:
   bool is32BitMode() const {
     // FIXME: Can tablegen auto-generate this?
     return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
   }
   bool is16BitMode() const {
     // FIXME: Can tablegen auto-generate this?
     return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
   }
+
+  unsigned DefaultMemSize() const {
+    return is64BitMode() ? 64 : (is32BitMode() ? 32 : 16);
+  }
   void SwitchMode(uint64_t mode) {
     uint64_t oldMode = STI.getFeatureBits() &
         (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
     setAvailableFeatures(FB);
     assert(mode == (STI.getFeatureBits() &
                     (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
   }
bool X86AsmParser::ParseRegister(unsigned &RegNo,
   return false;
 }
 
 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
   unsigned basereg =
     is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
   const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
   return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
-                               /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
+                               /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, DefaultMemSize(), 0);
 }
 
 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
   unsigned basereg =
     is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
   const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
   return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
-                               /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
+                               /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, DefaultMemSize(), 0);
 }
 
 std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
   if (isParsingIntelSyntax())
     return ParseIntelOperand();
   return ParseATTOperand();
 }
 
if (IsSymRef) {
     }
   }
 
   // When parsing inline assembly we set the base register to a non-zero value
   // if we don't know the actual value at this time.  This is necessary to
   // get the matching correct in some cases.
   BaseReg = BaseReg ? BaseReg : 1;
   return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
-                               End, Size, Identifier, Info.OpDecl);
+                               End, DefaultMemSize(), Size, Identifier, Info.OpDecl);
 }
 
 static void
 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
                            StringRef SymName, int64_t ImmDisp,
                            int64_t FinalImmDisp, SMLoc &BracLoc,
                            SMLoc &StartInBrac, SMLoc &End) {
   // Remove the '[' and ']' from the IR string.
X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
   int IndexReg = SM.getIndexReg();
   int Scale = SM.getScale();
   if (!isParsingInlineAsm()) {
     // handle [-42]
     if (!BaseReg && !IndexReg) {
       if (!SegReg)
         return X86Operand::CreateMem(Disp, Start, End, Size);
       else
-        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
+        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, DefaultMemSize(), Size);
     }
     StringRef ErrMsg;
     if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
       Error(StartInBrac, ErrMsg);
       return nullptr;
     }
     return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
-                                 End, Size);
+                                 End, DefaultMemSize(), Size);
   }
 
   InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
   return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
                                End, Size, SM.getSymName(), Info);
 }
 
 // Inline assembly may use variable names with namespace alias qualifiers.
if (getLexer().is(AsmToken::Integer)) {
 
     if (getLexer().isNot(AsmToken::LBrac)) {
       // An immediate following a 'segment register', 'colon' token sequence can
       // be followed by a bracketed expression.  If it isn't we know we have our
       // final segment override.
       const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
       return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
                                    /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
-                                   Size);
+                                   DefaultMemSize(), Size);
     }
   }
 
   if (getLexer().is(AsmToken::LBrac))
     return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
 
   const MCExpr *Val;
   SMLoc End;
if (SM.getIndexReg()) {
     return nullptr;
   }
 
   const MCExpr *Disp = MCConstantExpr::Create(SM.getImm(), getContext());
   // BaseReg is non-zero to avoid assertions.  In the context of inline asm,
   // we're pointing to a local variable in memory, so the base register is
   // really the frame or stack pointer.
   return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/1, /*IndexReg=*/0,
-                               /*Scale=*/1, Start, End, Size, Identifier,
+                               /*Scale=*/1, Start, End, DefaultMemSize(), Size, Identifier,
                                Info.OpDecl);
 }
 
 /// Parse the '.' operator.
 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
                                                 const MCExpr *&NewDisp) {
   const AsmToken &Tok = Parser.getTok();
   int64_t OrigDispVal, DotDispVal;
std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
   }
 
   unsigned Size = getIntelMemOperandSize(Tok.getString());
   if (Size) {
     Parser.Lex(); // Eat operand size (e.g., byte, word).
     if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
       return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
     Parser.Lex(); // Eat ptr.
+  } else {
+  //  Size = is64BitMode() ? 64 : (is32BitMode() ? 32 : 16);
   }
   Start = Tok.getLoc();
 
   // Immediate.
   if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
       getLexer().is(AsmToken::Tilde) || getLexer().is(AsmToken::LParen)) {
     AsmToken StartTok = Tok;
     IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
if (getLexer().isNot(AsmToken::LParen)) {
     SMLoc ExprEnd;
     if (getParser().parseExpression(Disp, ExprEnd)) return nullptr;
 
     // After parsing the base expression we could either have a parenthesized
     // memory address or not.  If not, return now.  If so, eat the (.
     if (getLexer().isNot(AsmToken::LParen)) {
       // Unless we have a segment register, treat this as an immediate.
       if (SegReg == 0)
-        return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
-      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
+        return X86Operand::CreateMem(Disp, MemStart, ExprEnd, DefaultMemSize());
+      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd, DefaultMemSize());
     }
 
     // Eat the '('.
     Parser.Lex();
   } else {
     // Okay, we have a '('.  We don't know if this is an expression or not, but
     // so we have to eat the ( to see beyond it.
     SMLoc LParenLoc = Parser.getTok().getLoc();
if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
       if (getParser().parseParenExpression(Disp, ExprEnd))
         return nullptr;
 
       // After parsing the base expression we could either have a parenthesized
       // memory address or not.  If not, return now.  If so, eat the (.
       if (getLexer().isNot(AsmToken::LParen)) {
         // Unless we have a segment register, treat this as an immediate.
         if (SegReg == 0)
-          return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
-        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
+          return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd, DefaultMemSize());
+        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd, DefaultMemSize());
       }
 
       // Eat the '('.
       Parser.Lex();
     }
   }
 
   // If we reached here, then we just ate the ( of the memory operand.  Process
std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
 
   StringRef ErrMsg;
   if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
     Error(BaseLoc, ErrMsg);
     return nullptr;
   }
 
   return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
-                               MemStart, MemEnd);
+                               MemStart, MemEnd, DefaultMemSize());
 }
 
 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                                     SMLoc NameLoc, OperandVector &Operands) {
   InstInfo = &Info;
   StringRef PatchedName = Name;
 
   // FIXME: Hack to recognize setneb as setne.

lib/Target/X86/AsmParser/X86Operand.h

struct X86Operand : public MCParsedAsmOperand {
 
   struct MemOp {
     unsigned SegReg;
     const MCExpr *Disp;
     unsigned BaseReg;
     unsigned IndexReg;
     unsigned Scale;
     unsigned Size;
+    unsigned DefaultSize;
   };
 
   union {
     struct TokOp Tok;
     struct RegOp Reg;
     struct ImmOp Imm;
     struct MemOp Mem;
   };
bool needAddressOf() const override {
     return AddressOf;
   }
 
   bool isMem() const override { return Kind == Memory; }
   bool isMem8() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 8);
   }
   bool isMem16() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 16);
   }
+  bool isMem16Default() const {
+    return Kind == Memory && ((!Mem.Size && Mem.DefaultSize == 16) || Mem.Size == 16);
+  }
   bool isMem32() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 32);
   }
+  bool isMem32Default() const {
+    return Kind == Memory && ((!Mem.Size && Mem.DefaultSize == 32) || Mem.Size == 32);
+  }
   bool isMem64() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 64);
   }
   bool isMem80() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 80);
   }
   bool isMem128() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 128);
static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
                                                SMLoc StartLoc, SMLoc EndLoc) {
     auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
     Res->Imm.Val = Val;
     return Res;
   }
 
   /// Create an absolute memory operand.
   static std::unique_ptr<X86Operand>
-  CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0,
+  CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned DefaultSize, unsigned Size = 0,
             StringRef SymName = StringRef(), void *OpDecl = nullptr) {
     auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
     Res->Mem.SegReg   = 0;
     Res->Mem.Disp     = Disp;
     Res->Mem.BaseReg  = 0;
     Res->Mem.IndexReg = 0;
     Res->Mem.Scale    = 1;
+    Res->Mem.DefaultSize = DefaultSize;
     Res->Mem.Size     = Size;
     Res->SymName      = SymName;
     Res->OpDecl       = OpDecl;
     Res->AddressOf    = false;
     return Res;
   }
 
   /// Create a generalized memory operand.
   static std::unique_ptr<X86Operand>
   CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
             unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
-            unsigned Size = 0, StringRef SymName = StringRef(),
+            unsigned DefaultSize, unsigned Size = 0, StringRef SymName = StringRef(),
             void *OpDecl = nullptr) {
     // We should never just have a displacement, that should be parsed as an
     // absolute memory operand.
     assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
 
     // The scale should always be one of {1,2,4,8}.
     assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
            "Invalid scale!");
     auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
     Res->Mem.SegReg   = SegReg;
     Res->Mem.Disp     = Disp;
     Res->Mem.BaseReg  = BaseReg;
     Res->Mem.IndexReg = IndexReg;
     Res->Mem.Scale    = Scale;
+    Res->Mem.DefaultSize = DefaultSize;
     Res->Mem.Size     = Size;
     Res->SymName      = SymName;
     Res->OpDecl       = OpDecl;
     Res->AddressOf    = false;
     return Res;
   }
 };
 
 } // End of namespace llvm
 
 #endif // X86_OPERAND

lib/Target/X86/X86InstrControl.td

def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
                       Requires<[Not64BitMode]>, Sched<[WriteJump]>;
     def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
                            (outs), (ins i16imm_pcrel:$dst),
                            "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
                       Sched<[WriteJump]>;
     def CALL16r     : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
                         "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
                       OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
-    def CALL16m     : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
+    def CALL16m     : I<0xFF, MRM2m, (outs), (ins i16memdefault:$dst),
                         "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
                         IIC_CALL_MEM>, OpSize16,
                       Requires<[Not64BitMode,FavorMemIndirectCall]>,
                       Sched<[WriteJumpLd]>;
     def CALL32r     : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
                         "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
                       OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
-    def CALL32m     : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
+    def CALL32m     : I<0xFF, MRM2m, (outs), (ins i32memdefault:$dst),
                         "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
                         IIC_CALL_MEM>, OpSize32,
                       Requires<[Not64BitMode,FavorMemIndirectCall]>,
                       Sched<[WriteJumpLd]>;
 
     def FARCALL16i  : Iseg16<0x9A, RawFrmImm16, (outs),
                              (ins i16imm:$off, i16imm:$seg),
                              "lcall{w}\t{$seg, $off|$off, $seg}", [],

lib/Target/X86/X86InstrInfo.td

  let Name = "Mem";
 }
 def X86Mem8AsmOperand : AsmOperandClass {
   let Name = "Mem8"; let RenderMethod = "addMemOperands";
 }
 def X86Mem16AsmOperand : AsmOperandClass {
   let Name = "Mem16"; let RenderMethod = "addMemOperands";
 }
+def X86Mem16DefaultAsmOperand : AsmOperandClass {
+  let Name = "Mem16Default"; let RenderMethod = "addMemOperands";
+}
 def X86Mem32AsmOperand : AsmOperandClass {
   let Name = "Mem32"; let RenderMethod = "addMemOperands";
 }
+def X86Mem32DefaultAsmOperand : AsmOperandClass {
+  let Name = "Mem32Default"; let RenderMethod = "addMemOperands";
+}
 def X86Mem64AsmOperand : AsmOperandClass {
   let Name = "Mem64"; let RenderMethod = "addMemOperands";
 }
 def X86Mem80AsmOperand : AsmOperandClass {
   let Name = "Mem80"; let RenderMethod = "addMemOperands";
 }
 def X86Mem128AsmOperand : AsmOperandClass {
   let Name = "Mem128"; let RenderMethod = "addMemOperands";

 def opaque48mem : X86MemOperand<"printopaquemem">;
 def opaque80mem : X86MemOperand<"printopaquemem">;
 def opaque512mem : X86MemOperand<"printopaquemem">;
 
 def i8mem   : X86MemOperand<"printi8mem"> {
   let ParserMatchClass = X86Mem8AsmOperand; }
 def i16mem  : X86MemOperand<"printi16mem"> {
   let ParserMatchClass = X86Mem16AsmOperand; }
+def i16memdefault  : X86MemOperand<"printi16mem"> {
+  let ParserMatchClass = X86Mem16DefaultAsmOperand; }
 def i32mem  : X86MemOperand<"printi32mem"> {
   let ParserMatchClass = X86Mem32AsmOperand; }
+def i32memdefault  : X86MemOperand<"printi32mem"> {
+  let ParserMatchClass = X86Mem32DefaultAsmOperand; }
 def i64mem  : X86MemOperand<"printi64mem"> {
   let ParserMatchClass = X86Mem64AsmOperand; }
 def i128mem : X86MemOperand<"printi128mem"> {
   let ParserMatchClass = X86Mem128AsmOperand; }
 def i256mem : X86MemOperand<"printi256mem"> {
   let ParserMatchClass = X86Mem256AsmOperand; }
 def i512mem : X86MemOperand<"printi512mem"> {
   let ParserMatchClass = X86Mem512AsmOperand; }

test/MC/X86/intel-syntax-unsized-operand.s

+// RUN: llvm-mc -triple i386-unknown-unknown -x86-asm-syntax=intel %s | FileCheck -check-prefix=CHECK-32 %s
+// RUN: llvm-mc -triple i386-unknown-unknown-code16 -x86-asm-syntax=intel %s | FileCheck -check-prefix=CHECK-16 %s
+// CHECK-32: calll *(%edx)
+// CHECK-16: callw *(%edx)
+// CHECK-32: calll *(%edx)
+// CHECK-16: calll *(%edx)
+// CHECK-32: callw *(%edx)
+// CHECK-16: callw *(%edx)
+call [edx]
+call dword ptr [edx]
+call word ptr [edx]

utils/TableGen/X86RecognizableInstr.cpp

if(OpSize == X86Local::OpSize16) {
     TYPE("GR16",              TYPE_Rv)
     TYPE("i16imm",            TYPE_IMMv)
   } else if(OpSize == X86Local::OpSize32) {
     // For OpSize32 instructions, a declared 32-bit register or
     // immediate encoding is special.
     TYPE("GR32",              TYPE_Rv)
   }
   TYPE("i16mem",              TYPE_Mv)
+  TYPE("i16memdefault",       TYPE_Mv)
   TYPE("i16imm",              TYPE_IMM16)
   TYPE("i16i8imm",            TYPE_IMMv)
   TYPE("GR16",                TYPE_R16)
   TYPE("i32mem",              TYPE_Mv)
+  TYPE("i32memdefault",       TYPE_Mv)
   TYPE("i32imm",              TYPE_IMMv)
   TYPE("i32i8imm",            TYPE_IMM32)
   TYPE("u32u8imm",            TYPE_IMM32)
   TYPE("GR32",                TYPE_R32)
   TYPE("GR32orGR64",          TYPE_R32)
   TYPE("i64mem",              TYPE_Mv)
   TYPE("i64i32imm",           TYPE_IMM64)
   TYPE("i64i8imm",            TYPE_IMM64)
RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
   errs() << "Unhandled mask register encoding " << s << "\n";
   llvm_unreachable("Unhandled mask register encoding");
 }
 
 OperandEncoding
 RecognizableInstr::memoryEncodingFromString(const std::string &s,
                                             uint8_t OpSize) {
   ENCODING("i16mem",          ENCODING_RM)
+  ENCODING("i16memdefault",   ENCODING_RM)
   ENCODING("i32mem",          ENCODING_RM)
+  ENCODING("i32memdefault",   ENCODING_RM)
   ENCODING("i64mem",          ENCODING_RM)
   ENCODING("i8mem",           ENCODING_RM)
   ENCODING("ssmem",           ENCODING_RM)
   ENCODING("sdmem",           ENCODING_RM)
   ENCODING("f128mem",         ENCODING_RM)
   ENCODING("f256mem",         ENCODING_RM)
   ENCODING("f512mem",         ENCODING_RM)
   ENCODING("f64mem",          ENCODING_RM)