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Differential D46117

[mips] Correct the predicates of sign extension instructions
ClosedPublic

Authored by sdardis on Apr 26 2018, 5:49 AM.

Details

Reviewers
smaksimovic
abeserminji
atanasyan
Commits
rG65b0492f0daa: [mips] Correct the predicates of sign extension instructions
rL331526: [mips] Correct the predicates of sign extension instructions
Summary

And elimination the duplication of those instructions for microMIPS32r6.

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.Apr 26 2018, 5:49 AM
Herald added a subscriber: arichardson. · View Herald TranscriptApr 26 2018, 5:49 AM
sdardis added a comment.May 3 2018, 2:23 AM

Ping.

atanasyan accepted this revision.May 3 2018, 5:03 AM

LGTM

This revision is now accepted and ready to land.May 3 2018, 5:03 AM
Closed by commit rL331526: [mips] Correct the predicates of sign extension instructions (authored by sdardis). · Explain WhyMay 4 2018, 8:04 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
14 lines
10 lines
8 lines
2 lines
test/
MC/
Mips/
micromips/
4 lines
mips32r2/
4 lines
mips32r3/
4 lines
mips32r5/
4 lines
mips32r6/
4 lines
mips64r2/
4 lines
mips64r3/
4 lines
mips64r5/
4 lines
mips64r6/
12 lines

Diff 145195

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Linesclass LBU32_FM_MMR6 : MipsR6Inst {
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0b000101; let Inst{31-26} = 0b000101;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = base; let Inst{20-16} = base;
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm> {
bits<5> rd;
bits<5> rt;
bits<32> Inst;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rd;
let Inst{20-16} = rt;
let Inst{15-6} = funct;
let Inst{5-0} = 0b111100;
}
class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst { class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
bits<5> rt; bits<5> rt;
bits<19> imm; bits<19> imm;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0b011110; let Inst{31-26} = 0b011110;
let Inst{25-21} = rt; let Inst{25-21} = rt;
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llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

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class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>; class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>; class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>; class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>; class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>; class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>; class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>; class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>; class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>; class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>; class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>; class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>; class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>; class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Linesclass AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm); dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
list<dag> Pattern = []; list<dag> Pattern = [];
InstrItinClass Itinerary = Itin; InstrItinClass Itinerary = Itin;
} }
class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>; class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
InstrItinClass Itin> : MMR6Arch<instr_asm> { InstrItinClass Itin> : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt); dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins simm16:$imm); dag InOperandList = (ins simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
list<dag> Pattern = []; list<dag> Pattern = [];
InstrItinClass Itinerary = Itin; InstrItinClass Itinerary = Itin;
} }
▲ Show 20 Lines • Show All 835 Lines • ▼ Show 20 Lines
def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6; def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6; def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6; def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6; def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6; def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6; def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6; def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6; def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6; def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6; def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6; def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 260 Lines • ▼ Show 20 Linesdef : MipsInstAlias<"xor $rs, $rt, $imm",
(XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"xor $rs, $imm", def : MipsInstAlias<"xor $rs, $imm",
(XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"not $rt, $rs", def : MipsInstAlias<"not $rt, $rs",
(NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm", def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>, (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
// //
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llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Count Leading /// Count Leading
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>, def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
ISA_MIPS32; ISA_MIPS32;
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>, def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
ISA_MIPS32; ISA_MIPS32;
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM_MM<0x0ac>, ISA_MIPS32R2; SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM_MM<0x0ec>, ISA_MIPS32R2; SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
/// Word Swap Bytes Within Halfwords /// Word Swap Bytes Within Halfwords
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
SEB_FM_MM<0x1ec>, ISA_MIPS32R2; SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5, def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>; immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
▲ Show 20 Lines • Show All 379 Lines • ▼ Show 20 Lines def : MipsInstAlias<"not $rt",
ISA_MICROMIPS; ISA_MICROMIPS;
def : MipsInstAlias<"bnez $rs,$offset", def : MipsInstAlias<"bnez $rs,$offset",
(BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
ISA_MICROMIPS; ISA_MICROMIPS;
def : MipsInstAlias<"beqz $rs,$offset", def : MipsInstAlias<"beqz $rs,$offset",
(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
ISA_MICROMIPS; ISA_MICROMIPS;
def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2_NOT_32R6_64R6; ISA_MICROMIPS;
def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2_NOT_32R6_64R6; ISA_MICROMIPS;
def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS; def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>, def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
ISA_MICROMIPS; ISA_MICROMIPS;
def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>, def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
} }
def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>, def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>,
ISA_MICROMIPS32R5, ASE_VIRT; ISA_MICROMIPS32R5, ASE_VIRT;
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llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

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def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
AdditionalPredicates = [NotInMicroMips] in { AdditionalPredicates = [NotInMicroMips] in {
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
}
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2; SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2; SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
}
/// Count Leading /// Count Leading
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
ISA_MIPS32_NOT_32R6_64R6; ISA_MIPS32_NOT_32R6_64R6;
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,
ISA_MIPS32_NOT_32R6_64R6; ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
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llvm/trunk/test/MC/Mips/micromips/valid.s

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maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c] maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c]
msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c] msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c] msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c]
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b] neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c] clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c] clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c] seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c] seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c] seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c] seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c] wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c]
ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec] ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc] ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc]
j 1328 # CHECK: j 1328 # encoding: [0xd4,0x00,0x02,0x98] j 1328 # CHECK: j 1328 # encoding: [0xd4,0x00,0x02,0x98]
jal 1328 # CHECK: jal 1328 # encoding: [0xf4,0x00,0x02,0x98] jal 1328 # CHECK: jal 1328 # encoding: [0xf4,0x00,0x02,0x98]
jalr $ra, $6 # CHECK: jalr $ra, $6 # encoding: [0x03,0xe6,0x0f,0x3c] jalr $ra, $6 # CHECK: jalr $ra, $6 # encoding: [0x03,0xe6,0x0f,0x3c]
jr $7 # CHECK: jr $7 # encoding: [0x00,0x07,0x0f,0x3c] jr $7 # CHECK: jr $7 # encoding: [0x00,0x07,0x0f,0x3c]
beq $9, $6, 1332 # CHECK: beq $9, $6, 1332 # encoding: [0x94,0xc9,0x02,0x9a] beq $9, $6, 1332 # CHECK: beq $9, $6, 1332 # encoding: [0x94,0xc9,0x02,0x9a]
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Linesa:
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15) sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r3/valid.s

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Linesa:
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15) sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r5/valid.s

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Linesa:
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15) sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Linesa:
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Linesa:
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15) sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 293 Lines • ▼ Show 20 Linesa:
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sh $14,-6704($15) sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
▲ Show 20 Lines • Show All 139 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Linesa:
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15) sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Linesa:
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20] seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines