[mips] Fix how compiler fuse instructions to fmadd/fmsub

[abeserminji]

Summary

When no -fp-contract option is provided (default behavior), compiler is fusing fmul and fadd/fsub into fmadd/fmsub.
GCC does not do that, so this patch makes LLVM behave like GCC.

Also, this patch makes LLVM take care of -fp-contract=fast option which enables fusing.

[sdardis]

lib/Target/Mips/MipsInstrInfo.td

252–254 ↗

(On Diff #143904)

Add an adjective like 'FPOP_FUSION_FAST' which uses this predicate in the AdditionalPredicates field of PredicateControl.

lib/Target/Mips/MipsMSAInstrInfo.td

3138 ↗

(On Diff #143904)

Use the new adjective here instead of Requires<[..]>.

test/CodeGen/Mips/fp-contract.ll

9 ↗

(On Diff #143904)

Can you try simplifiying the test case here? There's a lot of meta data that shouldn't have an effect.

Also, add a short comment explaining the test case's purpose.

[abeserminji]

Comments resolved.

[sdardis]

LGTM.

lib/Target/Mips/MipsInstrInfo.td

253 ↗

(On Diff #144095)

You can drop the parentheses here, they're spurious.

[abeserminji]

Comments resolved.
Rebase before commit.
Fixed one failing test.

llvm/trunk/lib/Target/Mips/MipsISelLowering.h

enum NodeType : unsigned {
       GotHi,
 
       // Handle gp_rel (small data/bss sections) relocation.
       GPRel,
 
       // Thread Pointer
       ThreadPointer,
 
+      // Vector Floating Point Multiply and Subtract
+      FMS,
+
       // Floating Point Branch Conditional
       FPBrcond,
 
       // Floating Point Compare
       FPCmp,
 
       // Floating point select
       FSELECT,

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case MipsISD::Hi:                return "MipsISD::Hi";
   case MipsISD::Lo:                return "MipsISD::Lo";
   case MipsISD::GotHi:             return "MipsISD::GotHi";
   case MipsISD::GPRel:             return "MipsISD::GPRel";
   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
   case MipsISD::Ret:               return "MipsISD::Ret";
   case MipsISD::ERet:              return "MipsISD::ERet";
   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
+  case MipsISD::FMS:               return "MipsISD::FMS";
   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
   case MipsISD::FSELECT:           return "MipsISD::FSELECT";
   case MipsISD::MTC1_D64:          return "MipsISD::MTC1_D64";
   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
   case MipsISD::MFHI:              return "MipsISD::MFHI";

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,
                             AssemblerPredicate<"FeatureUseIndirectJumpsHazard">;
 def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">,
                            AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">;
 def HasCRC   : Predicate<"Subtarget->hasCRC()">,
                AssemblerPredicate<"FeatureCRC">;
 def HasVirt  : Predicate<"Subtarget->hasVirt()">,
                AssemblerPredicate<"FeatureVirt">;
+// TODO: Add support for FPOpFusion::Standard
+def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion =="
+                                " FPOpFusion::Fast">;
 //===----------------------------------------------------------------------===//
 // Mips GPR size adjectives.
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 
 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
 

 class ABI_N64 {
   list<Predicate> AdditionalPredicates = [IsN64];
 }
 
 class ABI_NOT_N64 {
   list<Predicate> AdditionalPredicates = [IsNotN64];
 }
 
+class FPOP_FUSION_FAST {
+  list <Predicate> AdditionalPredicates = [AllowFPOpFusion];
+}
+
 //===----------------------------------------------------------------------===//
 
 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
   let EncodingPredicates = [HasStdEnc];
 }
 
 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
   InstAlias<Asm, Result, Emit>, PredicateControl;

llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td

 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
 def MipsILVL  : SDNode<"MipsISD::ILVL",  SDT_ILV>;
 def MipsILVR  : SDNode<"MipsISD::ILVR",  SDT_ILV>;
 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
+def MipsFMS   : SDNode<"MipsISD::FMS", SDTFPTernaryOp>;
 
 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
 
 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
     SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
     SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;

 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
                       (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
                       (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
                       (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
                                          node:$wt))>;
 
-def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
-                  (fsub node:$wd, (fmul node:$ws, node:$wt))>;
-
 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
                      (add node:$wd, (mul node:$ws, node:$wt))>;
 
 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
                      (sub node:$wd, (mul node:$ws, node:$wt))>;
 
 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
                         (fmul node:$ws, (fexp2 node:$wt))>;

 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
 
 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
                                         MSA128WOpnd>;
 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
                                         MSA128DOpnd>;
 
-class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
-class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
+class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>;
+class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>;
 
 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
 
 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
 
 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;

 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
 
 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
 
 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
 
+def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
+              (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
+              FPOP_FUSION_FAST;
+def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
+              (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
+              FPOP_FUSION_FAST;
+
+def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
+              (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
+              FPOP_FUSION_FAST;
+def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
+              (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
+              FPOP_FUSION_FAST;
+
 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
 
 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
 

llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp

SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
   case Intrinsic::mips_fmul_w:
   case Intrinsic::mips_fmul_d:
     // TODO: If intrinsics have fast-math-flags, propagate them.
     return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
                        Op->getOperand(2));
   case Intrinsic::mips_fmsub_w:
   case Intrinsic::mips_fmsub_d: {
     // TODO: If intrinsics have fast-math-flags, propagate them.
-    EVT ResTy = Op->getValueType(0);
-    return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
-                       DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
-                                   Op->getOperand(2), Op->getOperand(3)));
+    return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
+                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
   }
   case Intrinsic::mips_frint_w:
   case Intrinsic::mips_frint_d:
     return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
   case Intrinsic::mips_fsqrt_w:
   case Intrinsic::mips_fsqrt_d:
     return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
   case Intrinsic::mips_fsub_w:

llvm/trunk/test/CodeGen/Mips/fp-contract.ll

+; Test that the compiled does not fuse fmul and fadd into fmadd when no -fp-contract=fast
+; option is set (the same applies for fmul, fsub and fmsub).
+
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 -fp-contract=off < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
+; RUN: llc -march=mips -mattr=+msa,+fp64 -fp-contract=fast < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-FAST
+
+declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>)
+
+define void @foo(<4 x float>* %agg.result, <4 x float>* %acc, <4 x float>* %a, <4 x float>* %b) {
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %1 = load <4 x float>, <4 x float>* %b, align 16
+  %2 = call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
+  %3 = load <4 x float>, <4 x float>* %acc, align 16
+  %4 = call <4 x float> @llvm.mips.fadd.w(<4 x float> %3, <4 x float> %2)
+  store <4 x float> %4, <4 x float>* %agg.result, align 16
+  ret void
+  ; CHECK-CONTRACT-OFF: fmul.w
+  ; CHECK-CONTRACT-OFF: fadd.w
+  ; CHECK-CONTRACT-FAST: fmadd.w
+}
+
+define void @boo(<4 x float>* %agg.result, <4 x float>* %acc, <4 x float>* %a, <4 x float>* %b) {
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %1 = load <4 x float>, <4 x float>* %b, align 16
+  %2 = call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
+  %3 = load <4 x float>, <4 x float>* %acc, align 16
+  %4 = call <4 x float> @llvm.mips.fsub.w(<4 x float> %3, <4 x float> %2)
+  store <4 x float> %4, <4 x float>* %agg.result, align 16
+  ret void
+  ; CHECK-CONTRACT-OFF: fmul.w
+  ; CHECK-CONTRACT-OFF: fsub.w
+  ; CHECK-CONTRACT-FAST: fmsub.w
+}

llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll

define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
   ; CHECK-DAG: fmadd.d [[R1]], [[R2]], [[R3]]
   store <2 x double> %4, <2 x double>* %d
   ; CHECK-DAG: st.d [[R1]], 0($4)
 
   ret void
   ; CHECK: .size fma_v2f64
 }
 
-define void @fmsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
+define void @fmlu_fsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
                        <4 x float>* %c) nounwind {
-  ; CHECK: fmsub_v4f32:
+  ; CHECK: fmlu_fsub_v4f32:
 
-  %1 = load <4 x float>, <4 x float>* %a
-  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>, <4 x float>* %b
-  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x float>, <4 x float>* %c
-  ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
-  %4 = fmul <4 x float> %2, %3
-  %5 = fsub <4 x float> %1, %4
-  ; CHECK-DAG: fmsub.w [[R1]], [[R2]], [[R3]]
+  %1 = load <4 x float>, <4 x float>* %b
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($6)
+  %2 = load <4 x float>, <4 x float>* %c
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($7)
+  %3 = fmul <4 x float> %1, %2
+  ; CHECK-DAG: fmul.w [[R2]], [[R1]], [[R2]]
+  %4 = load <4 x float>, <4 x float>* %a
+  ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($5)
+  %5 = fsub <4 x float> %4, %3
+  ; CHECK-DAG: fsub.w [[R2]], [[R3]], [[R2]]
   store <4 x float> %5, <4 x float>* %d
-  ; CHECK-DAG: st.w [[R1]], 0($4)
+  ; CHECK-DAG: st.w [[R2]], 0($4)
 
   ret void
-  ; CHECK: .size fmsub_v4f32
+  ; CHECK: .size fmlu_fsub_v4f32
 }
 
-define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
+define void @fmul_fsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
                        <2 x double>* %c) nounwind {
-  ; CHECK: fmsub_v2f64:
+  ; CHECK: fmul_fsub_v2f64:
 
-  %1 = load <2 x double>, <2 x double>* %a
-  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>, <2 x double>* %b
+  %1 = load <2 x double>, <2 x double>* %b
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($7)
+  %2 = load <2 x double>, <2 x double>* %c
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x double>, <2 x double>* %c
-  ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
-  %4 = fmul <2 x double> %2, %3
-  %5 = fsub <2 x double> %1, %4
-  ; CHECK-DAG: fmsub.d [[R1]], [[R2]], [[R3]]
+  %3 = fmul <2 x double> %1, %2
+  ; CHECK-DAG: fmul.d [[R1]], [[R2]], [[R1]]
+  %4 = load <2 x double>, <2 x double>* %a
+  ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($5)
+  %5 = fsub <2 x double> %4, %3
+  ; CHECK-DAG: fsub.d [[R1]], [[R3]], [[R1]]
   store <2 x double> %5, <2 x double>* %d
   ; CHECK-DAG: st.d [[R1]], 0($4)
 
   ret void
-  ; CHECK: .size fmsub_v2f64
+  ; CHECK: .size fmul_fsub_v2f64
 }
 
 define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: fdiv_v4f32:
 
   %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = load <4 x float>, <4 x float>* %b