[mips] Correct the patterns for bswap

[sdardis]

Summary

Guard the MIPS64 variant correctly for i64, mark the MIPS32 version as not
in microMIPS and provide the microMIPS version.

Additionally, remove a related stale XFAIL'd test as bswap has its own test
case providing coverage.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

let Predicates = [InMicroMips] in {
   def : MipsPat<(load addrimm4lsl2:$addr),
                 (LW16_MM addrimm4lsl2:$addr)>;
   def : MipsPat<(load addr:$addr),
                 (LW_MM addr:$addr)>;
   def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
                 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
 }
 
+def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
+      ISA_MICROMIPS;
+
 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
               (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
               (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
 let AddedComplexity = 40 in {
   def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
                 (LH_MM addrRegImm:$a)>;

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

def : MipsPat<(i64 (zext (i32 (shl GPR32:$rt, immZExt5:$imm)))),
         ASE_MIPS64_CNMIPS;
 }
 
 // Sign extend in register
 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
               (SLL64_64 GPR64:$src)>;
 
 // bswap MipsPattern
-def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
+def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2;
 
 // Carry pattern
 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
                 (DSUBu GPR64:$lhs, GPR64:$rhs)>;
   def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
                 (DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP;
   def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
   defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
   defm : SetlePats<GPR32, XORi, SLT, SLTu>;
   defm : SetgtPats<GPR32, SLT, SLTu>;
   defm : SetgePats<GPR32, XORi, SLT, SLTu>;
   defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>;
-}
 
   // bswap pattern
-def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
+  def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2;
+}
 
 // Load halfword/word patterns.
 let AddedComplexity = 40 in {
   def : LoadRegImmPat<LBu, i32, zextloadi8>;
   let AdditionalPredicates = [NotInMicroMips] in {
     def : LoadRegImmPat<LH, i32, sextloadi16>;
     def : LoadRegImmPat<LW, i32, load>;
   }

llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll

-; DISABLED: llc < %s | grep wsbw | count 1
-; RUN: false
-; XFAIL: *
-
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
-target triple = "psp"
-
-define i32 @__bswapsi2(i32 %u) nounwind {
-entry:
-  tail call i32 @llvm.bswap.i32( i32 %u )    ; <i32>:0 [#uses=1]
-  ret i32 %0
-}
-
-declare i32 @llvm.bswap.i32(i32) nounwind readnone

llvm/trunk/test/CodeGen/Mips/bswap.ll

 ; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc  < %s -mtriple=mipsel-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips | FileCheck %s -check-prefix=MM
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
 ; RUN: llc  < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 | FileCheck %s -check-prefix=MIPS16
 
 define i32 @bswap32(i32 signext %x) nounwind readnone {
 entry:
 ; MIPS32-LABEL: bswap32:
 ; MIPS32: wsbh $[[R0:[0-9]+]]
 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
 
+; MM-LABEL: bswap32:
+; MM: wsbh $[[R0:[0-9]+]]
+; MM: rotr ${{[0-9]+}}, $[[R0]], 16
+
 ; MIPS64-LABEL: bswap32:
 ; MIPS64: wsbh $[[R0:[0-9]+]]
 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
 
 ; MIPS16-LABEL: bswap32:
 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
 ; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8

 define i64 @bswap64(i64 signext %x) nounwind readnone {
 entry:
 ; MIPS32-LABEL: bswap64:
 ; MIPS32: wsbh $[[R0:[0-9]+]]
 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS32: wsbh $[[R0:[0-9]+]]
 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
 
+; MM-LABEL: bswap64:
+; MM: wsbh $[[R0:[0-9]+]]
+; MM: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM: wsbh $[[R0:[0-9]+]]
+; MM: rotr ${{[0-9]+}}, $[[R0]], 16
+
 ; MIPS64-LABEL: bswap64:
 ; MIPS64: dsbh $[[R0:[0-9]+]]
 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
 
 ; MIPS16-LABEL: bswap64:
 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
 ; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8

 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 
+; MM-LABEL: bswapv4i32:
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+
 ; MIPS64-LABEL: bswapv4i32:
 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
 ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
 ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
 ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]]