[Power9]Legalize and emit code for truncate and convert Quad-Precision to Double-Word

[lei]

Summary

Legalize and emit code for:

• xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword
• xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword

[inouehrs]

lib/Target/PowerPC/PPCISelLowering.cpp

9411

I feel it is better to do this check in LowerFP_TO_INT for ease of reading.

[lei]

update as per review comment.

[nemanjai]

lib/Target/PowerPC/PPCISelLowering.cpp

6928

This sentence makes it sound like this is legal in a judicial sense. Perhaps:
// FP to INT conversions are legal for f128.

lib/Target/PowerPC/PPCInstrVSX.td

3153

Don't forget periods on comments.

3154

This seems very wrong. The STXSD will need a reg and an immediate and xoaddr will force it to use reg+reg. We should have two versions here (xaddr -> STXSDX and ixaddr -> STXSD). And we should also have test cases for both store instructions.

test/CodeGen/PowerPC/f128-truncateNconv.ll

3

Don't forget -verify-machineinstrs in test cases. We want to make sure we don't introduce new machine verifier failures (which I think this patch does).

[lei]

address review comments.

[lei]

Rebased on patch: https://reviews.llvm.org/D46102

[nemanjai]

LGTM. Of course, after the dependent patch lands.

lib/Target/PowerPC/PPCISelLowering.cpp

case MVT::i64:
     break;
   }
   return Tmp;
 }
 
 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
                                           const SDLoc &dl) const {
   // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
   // PPC (the libcall is not available).
   if (Op.getOperand(0).getValueType() == MVT::ppcf128) {
     if (Op.getValueType() == MVT::i32) {
       if (Op.getOpcode() == ISD::FP_TO_SINT) {
         SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
                                  MVT::f64, Op.getOperand(0),
                                  DAG.getIntPtrConstant(0, dl));
         SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
                                  MVT::f64, Op.getOperand(0),
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::EH_SJLJ_SETJMP:     return lowerEH_SJLJ_SETJMP(Op, DAG);
   case ISD::EH_SJLJ_LONGJMP:    return lowerEH_SJLJ_LONGJMP(Op, DAG);
 
   case ISD::LOAD:               return LowerLOAD(Op, DAG);
   case ISD::STORE:              return LowerSTORE(Op, DAG);
   case ISD::TRUNCATE:           return LowerTRUNCATE(Op, DAG);
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
   case ISD::FP_TO_UINT:
-  case ISD::FP_TO_SINT:         return LowerFP_TO_INT(Op, DAG,
-                                                      SDLoc(Op));
+  case ISD::FP_TO_SINT:
+    // Legalize instruction for converting f128 to integer types
+    if (EnableQuadPrecision && (Op->getOperand(0).getValueType() == MVT::f128))
+      return Op;
+    return LowerFP_TO_INT(Op, DAG, SDLoc(Op));
   case ISD::UINT_TO_FP:
   case ISD::SINT_TO_FP:
     // Legalize instruction for f128 result type
     if (EnableQuadPrecision && (Op->getValueType(0) == MVT::f128))
       return Op;
     return LowerINT_TO_FP(Op, DAG);
 
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
   def XSCVQPDP  : X_VT5_XO5_VB5   <63, 20, 836, "xscvqpdp" , []>;
   def XSCVQPDPO : X_VT5_XO5_VB5_Ro<63, 20, 836, "xscvqpdpo", []>;
 
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
+  def : Pat<(i64 (fp_to_sint f128:$src)),
+            (i64 (MFVRD (XSCVQPSDZ $src)))>;
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
   def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
+  def : Pat<(i64 (fp_to_uint f128:$src)),
+            (i64 (MFVRD (XSCVQPUDZ $src)))>;
   def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz", []>;
 
   // Convert (Un)Signed DWord -> QP
   def XSCVSDQP  : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
   def : Pat<(f128 (sint_to_fp i64:$src)),
             (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
   def XSCVUDQP  : X_VT5_XO5_VB5_TyVB<63,  2, 836, "xscvudqp", vfrc, []>;
   def : Pat<(f128 (uint_to_fp i64:$src)),
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // Convert Unsigned HWord in memory -> QP
   def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)),
             (f128 (XSCVUDQP (LXSIHZX xaddr:$src)))>;
 
   // Convert Unsigned Byte in memory -> QP
   def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),
             (f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>;
 
+  // Truncate & Convert QP -> (Un)Signed DWord in memory
+  def : Pat<(store (i64 (fp_to_sint f128:$src)), xoaddr:$dst),
+            (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ $src), VFRC), xoaddr:$dst)>;
+  def : Pat<(store (i64 (fp_to_uint f128:$src)), xoaddr:$dst),
+            (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ $src), VFRC), xoaddr:$dst)>;
+
 } // end HasP9Vector, AddedComplexity
 
 let Predicates = [HasP9Vector] in {
   let isPseudo = 1 in {
     let mayStore = 1 in {
       def SPILLTOVSR_STX : Pseudo<(outs), (ins spilltovsrrc:$XT, memrr:$dst),
                                 "#SPILLTOVSR_STX", []>;
       def SPILLTOVSR_ST : Pseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),

test/CodeGen/PowerPC/f128-truncateNconv.ll

+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
+                                 fp128 0xLF000000000000000400808AB851EB851,
+                                 fp128 0xL5000000000000000400E0C26324C8366,
+                                 fp128 0xL8000000000000000400A24E2E147AE14],
+                                align 16
+
+; Function Attrs: norecurse nounwind readonly
+define i64 @qpConv2sdw(fp128* nocapture readonly %a) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptosi fp128 %0 to i64
+  ret i64 %conv
+
+; CHECK-LABEL: qpConv2sdw
+; CHECK: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpsdz [[REG]], [[REG]]
+; CHECK-NEXT: mfvsrd 3, [[REG]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sdw_02(i64* nocapture %res) local_unnamed_addr #1 {
+entry:
+  %0 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 2), align 16
+  %conv = fptosi fp128 %0 to i64
+  store i64 %conv, i64* %res, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2sdw_02
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
+; CHECK-NEXT: xscvqpsdz [[REG]], [[REG]]
+; CHECK-NEXT: stxsd [[REG]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define i64 @qpConv2sdw_03(fp128* nocapture readonly %a) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 1), align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptosi fp128 %add to i64
+  ret i64 %conv
+
+; CHECK-LABEL: qpConv2sdw_03
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK-DAG: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpsdz [[REG]], [[REG]]
+; CHECK-NEXT: mfvsrd 3, [[REG]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sdw_04(fp128* nocapture readonly %a,
+                           fp128* nocapture readonly %b, i64* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptosi fp128 %add to i64
+  store i64 %conv, i64* %res, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2sdw_04
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpsdz [[REG]], [[REG]]
+; CHECK-NEXT: stxsd [[REG]], 0(5)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define i64 @qpConv2udw(fp128* nocapture readonly %a) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptoui fp128 %0 to i64
+  ret i64 %conv
+
+; CHECK-LABEL: qpConv2udw
+; CHECK: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpudz [[REG]], [[REG]]
+; CHECK-NEXT: mfvsrd 3, [[REG]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2udw_02(i64* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 2), align 16
+  %conv = fptoui fp128 %0 to i64
+  store i64 %conv, i64* %res, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2udw_02
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
+; CHECK-NEXT: xscvqpudz [[REG]], [[REG]]
+; CHECK-NEXT: stxsd [[REG]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define i64 @qpConv2udw_03(fp128* nocapture readonly %a) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 1), align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptoui fp128 %add to i64
+  ret i64 %conv
+
+; CHECK-LABEL: qpConv2udw_03
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK-DAG: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpudz [[REG]], [[REG]]
+; CHECK-NEXT: mfvsrd 3, [[REG]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2udw_04(fp128* nocapture readonly %a,
+                           fp128* nocapture readonly %b, i64* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptoui fp128 %add to i64
+  store i64 %conv, i64* %res, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2udw_04
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpudz [[REG]], [[REG]]
+; CHECK-NEXT: stxsd [[REG]], 0(5)
+; CHECK-NEXT: blr
+}