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Differential D45404

[X86] Add variable shuffle schedule classes
ClosedPublic

Authored by RKSimon on Apr 7 2018, 9:10 AM.

Details

Reviewers
craig.topper
zvi
andreadb
spatel
Commits
rG89c8a10f7c2e: [X86] Add variable shuffle schedule classes
rL329806: [X86] Add variable shuffle schedule classes
Summary

Split variable index shuffles from immediate index shuffles

WriteFVarShuffle - variable 'in-lane' shuffles (VPERMILPS/VPERMIL2PS etc.)
WriteVarShuffle - variable 'in-lane' shuffles (PSHUFB etc.)

WriteFVarShuffle256 - variable 'cross-lane' shuffles (VPERMPS etc.)
WriteVarShuffle256 - variable 'cross-lane' shuffles (VPERMD etc.)

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon created this revision.Apr 7 2018, 9:10 AM
RKSimon added a comment.Apr 11 2018, 2:20 AM

ping?

andreadb accepted this revision.Apr 11 2018, 3:07 AM

LGTM.

Thanks!

This revision is now accepted and ready to land.Apr 11 2018, 3:07 AM
Closed by commit rL329806: [X86] Add variable shuffle schedule classes (authored by RKSimon). · Explain WhyApr 11 2018, 6:53 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 141998

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
avx512vl_i32_info, VK16>; avx512vl_i32_info, VK16>;
defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
avx512vl_i64_info, VK8>, VEX_W; avx512vl_i64_info, VK8>, VEX_W;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// -- VPERMI2 - 3 source operands form -- // -- VPERMI2 - 3 source operands form --
let Sched = WriteFShuffle256 in let Sched = WriteFVarShuffle256 in
def AVX512_PERM2_F : OpndItins< def AVX512_PERM2_F : OpndItins<
IIC_SSE_SHUFP, IIC_SSE_SHUFP IIC_SSE_SHUFP, IIC_SSE_SHUFP
>; >;
let Sched = WriteShuffle256 in let Sched = WriteVarShuffle256 in
def AVX512_PERM2_I : OpndItins< def AVX512_PERM2_I : OpndItins<
IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
>; >;
multiclass avx512_perm_i<bits<8> opc, string OpcodeStr, OpndItins itins, multiclass avx512_perm_i<bits<8> opc, string OpcodeStr, OpndItins itins,
X86VectorVTInfo _> { X86VectorVTInfo _> {
let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
// The index operand in the pattern should really be an integer type. However, // The index operand in the pattern should really be an integer type. However,
▲ Show 20 Lines • Show All 7,222 Lines • ▼ Show 20 Lines def : Pat<(v16i16 (sext (v16i1 VK16:$src))),
(VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; (VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AVX-512 - COMPRESS and EXPAND // AVX-512 - COMPRESS and EXPAND
// //
// FIXME: Is there a better scheduler itinerary for VPCOMPRESS/VPEXPAND? // FIXME: Is there a better scheduler itinerary for VPCOMPRESS/VPEXPAND?
let Sched = WriteShuffle256 in { let Sched = WriteVarShuffle256 in {
def AVX512_COMPRESS : OpndItins< def AVX512_COMPRESS : OpndItins<
IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
>; >;
def AVX512_EXPAND : OpndItins< def AVX512_EXPAND : OpndItins<
IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
>; >;
} }
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llvm/trunk/lib/Target/X86/X86InstrMMX.td

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def MMX_UNPCK_L_ITINS : OpndItins< def MMX_UNPCK_L_ITINS : OpndItins<
IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L
>; >;
def MMX_PCK_ITINS : OpndItins< def MMX_PCK_ITINS : OpndItins<
IIC_MMX_PCK_RR, IIC_MMX_PCK_RM IIC_MMX_PCK_RR, IIC_MMX_PCK_RM
>; >;
} // Sched
let Sched = WriteVarShuffle in
def MMX_PSHUF_ITINS : OpndItins< def MMX_PSHUF_ITINS : OpndItins<
IIC_MMX_PSHUF, IIC_MMX_PSHUF IIC_MMX_PSHUF, IIC_MMX_PSHUF
>; >;
} // Sched
let Sched = WriteCvtF2I in { let Sched = WriteCvtF2I in {
def MMX_CVT_PD_ITINS : OpndItins< def MMX_CVT_PD_ITINS : OpndItins<
IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM
>; >;
def MMX_CVT_PS_ITINS : OpndItins< def MMX_CVT_PS_ITINS : OpndItins<
IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM
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llvm/trunk/lib/Target/X86/X86InstrSSE.td

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>; >;
def SSE_PHADDSUBSW : OpndItins< def SSE_PHADDSUBSW : OpndItins<
IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
>; >;
def SSE_PHADDSUBW : OpndItins< def SSE_PHADDSUBW : OpndItins<
IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
>; >;
} }
let Sched = WriteShuffle in let Sched = WriteVarShuffle in
def SSE_PSHUFB : OpndItins< def SSE_PSHUFB : OpndItins<
IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
>; >;
let Sched = WriteVecALU in let Sched = WriteVecALU in
def SSE_PSIGN : OpndItins< def SSE_PSIGN : OpndItins<
IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
>; >;
let Sched = WriteVecIMul in let Sched = WriteVecIMul in
▲ Show 20 Lines • Show All 2,621 Lines • ▼ Show 20 Linesdefm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
int_x86_avx_maskload_pd_256, int_x86_avx_maskload_pd_256,
int_x86_avx_maskstore_pd, int_x86_avx_maskstore_pd,
int_x86_avx_maskstore_pd_256>; int_x86_avx_maskstore_pd_256>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VPERMIL - Permute Single and Double Floating-Point Values // VPERMIL - Permute Single and Double Floating-Point Values
// //
let Sched = WriteFShuffle in let Sched = WriteFVarShuffle in
def AVX_VPERMILV : OpndItins< def AVX_VPERMILV : OpndItins<
IIC_SSE_SHUFP, IIC_SSE_SHUFP IIC_SSE_SHUFP, IIC_SSE_SHUFP
>; >;
let Sched = WriteFShuffle in let Sched = WriteFShuffle in
def AVX_VPERMIL : OpndItins< def AVX_VPERMIL : OpndItins<
IIC_SSE_SHUFP, IIC_SSE_SHUFP IIC_SSE_SHUFP, IIC_SSE_SHUFP
>; >;
multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr, multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
RegisterClass RC, X86MemOperand x86memop_f, RegisterClass RC, X86MemOperand x86memop_f,
X86MemOperand x86memop_i, PatFrag i_frag, X86MemOperand x86memop_i, PatFrag i_frag,
ValueType f_vt, ValueType i_vt> { ValueType f_vt, ValueType i_vt> {
let Predicates = [HasAVX, NoVLX] in { let Predicates = [HasAVX, NoVLX] in {
def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst), def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2), (ins RC:$src1, RC:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (f_vt (X86VPermilpv RC:$src1, (i_vt RC:$src2))))]>, VEX_4V, [(set RC:$dst, (f_vt (X86VPermilpv RC:$src1, (i_vt RC:$src2))))]>, VEX_4V,
Sched<[WriteFShuffle]>; Sched<[WriteFVarShuffle]>;
def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst), def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop_i:$src2), (ins RC:$src1, x86memop_i:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (f_vt (X86VPermilpv RC:$src1, [(set RC:$dst, (f_vt (X86VPermilpv RC:$src1,
(i_vt (bitconvert (i_frag addr:$src2))))))]>, VEX_4V, (i_vt (bitconvert (i_frag addr:$src2))))))]>, VEX_4V,
Sched<[WriteFShuffleLd, ReadAfterLd]>; Sched<[WriteFVarShuffleLd, ReadAfterLd]>;
def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst), def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, u8imm:$src2), (ins RC:$src1, u8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (f_vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX, [(set RC:$dst, (f_vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
Sched<[WriteFShuffle]>; Sched<[WriteFShuffle]>;
def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst), def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
(ins x86memop_f:$src1, u8imm:$src2), (ins x86memop_f:$src1, u8imm:$src2),
▲ Show 20 Lines • Show All 451 Lines • ▼ Show 20 Lines def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"), "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR256:$dst, [(set VR256:$dst,
(OpVT (X86VPermv VR256:$src1, (OpVT (X86VPermv VR256:$src1,
(bitconvert (mem_frag addr:$src2)))))]>, (bitconvert (mem_frag addr:$src2)))))]>,
Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L; Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
} }
} }
defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256, defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteVarShuffle256,
i256mem>; i256mem>;
let ExeDomain = SSEPackedSingle in let ExeDomain = SSEPackedSingle in
defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256, defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFVarShuffle256,
f256mem>; f256mem>;
multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag, multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
ValueType OpVT, X86FoldableSchedWrite Sched, ValueType OpVT, X86FoldableSchedWrite Sched,
X86MemOperand memOp> { X86MemOperand memOp> {
let Predicates = [HasAVX2, NoVLX] in { let Predicates = [HasAVX2, NoVLX] in {
def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst), def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, u8imm:$src2), (ins VR256:$src1, u8imm:$src2),
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llvm/trunk/lib/Target/X86/X86InstrXOP.td

Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Linesmulticlass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType vt128> { ValueType vt128> {
def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst), def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3), (ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst, [(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2), (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
(vt128 VR128:$src3))))]>, (vt128 VR128:$src3))))]>,
XOP_4V, Sched<[WriteShuffle]>; XOP_4V, Sched<[WriteVarShuffle]>;
def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst), def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i128mem:$src3), (ins VR128:$src1, VR128:$src2, i128mem:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst, [(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2), (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
(vt128 (bitconvert (loadv2i64 addr:$src3))))))]>, (vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
XOP_4V, VEX_W, Sched<[WriteShuffleLd, ReadAfterLd, ReadAfterLd]>; XOP_4V, VEX_W, Sched<[WriteVarShuffleLd, ReadAfterLd, ReadAfterLd]>;
def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst), def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, VR128:$src3), (ins VR128:$src1, i128mem:$src2, VR128:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst, [(set VR128:$dst,
(v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))), (v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
(vt128 VR128:$src3))))]>, (vt128 VR128:$src3))))]>,
XOP_4V, Sched<[WriteShuffleLd, ReadAfterLd, XOP_4V, Sched<[WriteVarShuffleLd, ReadAfterLd,
// 128mem:$src2 // 128mem:$src2
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
ReadDefault, ReadDefault,
// VR128:$src3 // VR128:$src3
ReadAfterLd]>; ReadAfterLd]>;
// For disassembler // For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst), def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3), (ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_4V, VEX_W, Sched<[WriteShuffle]>, FoldGenData<NAME#rrr>; []>, XOP_4V, VEX_W, Sched<[WriteVarShuffle]>, FoldGenData<NAME#rrr>;
} }
let ExeDomain = SSEPackedInt in { let ExeDomain = SSEPackedInt in {
defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8>; defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8>;
} }
// Instruction where either second or third source can be memory // Instruction where either second or third source can be memory
multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC, multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesmulticlass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
ValueType VT, PatFrag FPLdFrag, ValueType VT, PatFrag FPLdFrag,
PatFrag IntLdFrag> { PatFrag IntLdFrag> {
def rr : IXOP5<Opc, MRMSrcReg, (outs RC:$dst), def rr : IXOP5<Opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4), (ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
[(set RC:$dst, [(set RC:$dst,
(VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>, (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>,
Sched<[WriteFShuffle]>; Sched<[WriteFVarShuffle]>;
def rm : IXOP5<Opc, MRMSrcMemOp4, (outs RC:$dst), def rm : IXOP5<Opc, MRMSrcMemOp4, (outs RC:$dst),
(ins RC:$src1, RC:$src2, intmemop:$src3, u8imm:$src4), (ins RC:$src1, RC:$src2, intmemop:$src3, u8imm:$src4),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
[(set RC:$dst, [(set RC:$dst,
(VT (X86vpermil2 RC:$src1, RC:$src2, (VT (X86vpermil2 RC:$src1, RC:$src2,
(bitconvert (IntLdFrag addr:$src3)), (bitconvert (IntLdFrag addr:$src3)),
(i8 imm:$src4))))]>, VEX_W, (i8 imm:$src4))))]>, VEX_W,
Sched<[WriteFShuffleLd, ReadAfterLd, ReadAfterLd]>; Sched<[WriteFVarShuffleLd, ReadAfterLd, ReadAfterLd]>;
def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst), def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4), (ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
[(set RC:$dst, [(set RC:$dst,
(VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2), (VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
RC:$src3, (i8 imm:$src4))))]>, RC:$src3, (i8 imm:$src4))))]>,
Sched<[WriteFShuffleLd, ReadAfterLd, Sched<[WriteFVarShuffleLd, ReadAfterLd,
// fpmemop:$src2 // fpmemop:$src2
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
// RC:$src3 // RC:$src3
ReadAfterLd]>; ReadAfterLd]>;
// For disassembler // For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rr_REV : IXOP5<Opc, MRMSrcRegOp4, (outs RC:$dst), def rr_REV : IXOP5<Opc, MRMSrcRegOp4, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4), (ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
[]>, VEX_W, Sched<[WriteFShuffle]>, FoldGenData<NAME#rr>; []>, VEX_W, Sched<[WriteFVarShuffle]>, FoldGenData<NAME#rr>;
} }
let ExeDomain = SSEPackedDouble in { let ExeDomain = SSEPackedDouble in {
defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem, defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem,
v2f64, loadv2f64, loadv2i64>; v2f64, loadv2f64, loadv2i64>;
defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem, defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem,
v4f64, loadv4f64, loadv4i64>, VEX_L; v4f64, loadv4f64, loadv4i64>, VEX_L;
} }
let ExeDomain = SSEPackedSingle in { let ExeDomain = SSEPackedSingle in {
defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem, defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem,
v4f32, loadv4f32, loadv2i64>; v4f32, loadv4f32, loadv2i64>;
defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem, defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem,
v8f32, loadv8f32, loadv4i64>, VEX_L; v8f32, loadv8f32, loadv4i64>, VEX_L;
} }

llvm/trunk/lib/Target/X86/X86SchedBroadwell.td

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare. defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication. defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division. defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root. defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate. defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate. defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add. defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles. defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1>; // Floating point vector variable shuffles.
defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends. defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2]>; // Fp vector variable blends. defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2]>; // Fp vector variable blends.
// FMA Scheduling helper class. // FMA Scheduling helper class.
// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
// Vector integer operations. // Vector integer operations.
def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; } def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>; def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
def : WriteRes<WriteVecMove, [BWPort015]>; def : WriteRes<WriteVecMove, [BWPort015]>;
defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals. defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts. defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply. defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles. defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1>; // Vector variable shuffles.
defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends. defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends. defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD. defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
// Vector bitwise operations. // Vector bitwise operations.
// These are often used on both floating point and integer vectors. // These are often used on both floating point and integer vectors.
defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor. defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
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// Carry-less multiplication instructions. // Carry-less multiplication instructions.
defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>; defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
// Catch-all for expensive system instructions. // Catch-all for expensive system instructions.
def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
// AVX2. // AVX2.
defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles. defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3>; // Fp 256-bit width vector variable shuffles.
defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles. defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3>; // 256-bit width vector variable shuffles.
defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts. defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
// Old microcoded instructions that nobody use. // Old microcoded instructions that nobody use.
def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
// Fence instructions. // Fence instructions.
def : WriteRes<WriteFence, [BWPort23, BWPort4]>; def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Linesdef BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr", def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr", "MMX_MOVQ2DQrr",
"MMX_PALIGNRrri", "MMX_PALIGNRrri",
"MMX_PSHUFBrr",
"MMX_PSHUFWri", "MMX_PSHUFWri",
"MMX_PUNPCKHBWirr", "MMX_PUNPCKHBWirr",
"MMX_PUNPCKHDQirr", "MMX_PUNPCKHDQirr",
"MMX_PUNPCKHWDirr", "MMX_PUNPCKHWDirr",
"MMX_PUNPCKLBWirr", "MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr", "MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr", "MMX_PUNPCKLWDirr",
"(V?)ANDNPD(Y?)rr", "(V?)ANDNPD(Y?)rr",
Show All 21 Linesdef: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"(V?)PACKSSWB(Y?)rr", "(V?)PACKSSWB(Y?)rr",
"(V?)PACKUSDW(Y?)rr", "(V?)PACKUSDW(Y?)rr",
"(V?)PACKUSWB(Y?)rr", "(V?)PACKUSWB(Y?)rr",
"(V?)PALIGNR(Y?)rri", "(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri", "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPD(Y?)ri", "VPERMILPD(Y?)ri",
"VPERMILPD(Y?)rr",
"VPERMILPS(Y?)ri", "VPERMILPS(Y?)ri",
"VPERMILPS(Y?)rr",
"(V?)PMOVSXBDrr", "(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr", "(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr", "(V?)PMOVSXBWrr",
"(V?)PMOVSXDQrr", "(V?)PMOVSXDQrr",
"(V?)PMOVSXWDrr", "(V?)PMOVSXWDrr",
"(V?)PMOVSXWQrr", "(V?)PMOVSXWQrr",
"(V?)PMOVZXBDrr", "(V?)PMOVZXBDrr",
"(V?)PMOVZXBQrr", "(V?)PMOVZXBQrr",
"(V?)PMOVZXBWrr", "(V?)PMOVZXBWrr",
"(V?)PMOVZXDQrr", "(V?)PMOVZXDQrr",
"(V?)PMOVZXWDrr", "(V?)PMOVZXWDrr",
"(V?)PMOVZXWQrr", "(V?)PMOVZXWQrr",
"(V?)PSHUFB(Y?)rr",
"(V?)PSHUFD(Y?)ri", "(V?)PSHUFD(Y?)ri",
"(V?)PSHUFHW(Y?)ri", "(V?)PSHUFHW(Y?)ri",
"(V?)PSHUFLW(Y?)ri", "(V?)PSHUFLW(Y?)ri",
"(V?)PSLLDQ(Y?)ri", "(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri",
"(V?)PUNPCKHBW(Y?)rr", "(V?)PUNPCKHBW(Y?)rr",
"(V?)PUNPCKHDQ(Y?)rr", "(V?)PUNPCKHDQ(Y?)rr",
"(V?)PUNPCKHQDQ(Y?)rr", "(V?)PUNPCKHQDQ(Y?)rr",
▲ Show 20 Lines • Show All 455 Lines • ▼ Show 20 Linesdef: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
"VINSERTF128rr", "VINSERTF128rr",
"VINSERTI128rr", "VINSERTI128rr",
"VPBROADCASTB(Y?)rr", "VPBROADCASTB(Y?)rr",
"VPBROADCASTDYrr", "VPBROADCASTDYrr",
"VPBROADCASTQYrr", "VPBROADCASTQYrr",
"VPBROADCASTW(Y?)rr", "VPBROADCASTW(Y?)rr",
"VPERM2F128rr", "VPERM2F128rr",
"VPERM2I128rr", "VPERM2I128rr",
"VPERMDYrr",
"VPERMPDYri", "VPERMPDYri",
"VPERMPSYrr",
"VPERMQYri", "VPERMQYri",
"VPMOVSXBDYrr", "VPMOVSXBDYrr",
"VPMOVSXBQYrr", "VPMOVSXBQYrr",
"VPMOVSXBWYrr", "VPMOVSXBWYrr",
"VPMOVSXDQYrr", "VPMOVSXDQYrr",
"VPMOVSXWDYrr", "VPMOVSXWDYrr",
"VPMOVSXWQYrr", "VPMOVSXWQYrr",
"VPMOVZXBDYrr", "VPMOVZXBDYrr",
▲ Show 20 Lines • Show All 1,904 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86SchedHaswell.td

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
defm : HWWriteResPair<WriteFRcp, [HWPort0], 5>; defm : HWWriteResPair<WriteFRcp, [HWPort0], 5>;
defm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5>; defm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5>;
defm : HWWriteResPair<WriteFSqrt, [HWPort0], 15>; defm : HWWriteResPair<WriteFSqrt, [HWPort0], 15>;
defm : HWWriteResPair<WriteCvtF2I, [HWPort1], 3>; defm : HWWriteResPair<WriteCvtF2I, [HWPort1], 3>;
defm : HWWriteResPair<WriteCvtI2F, [HWPort1], 4>; defm : HWWriteResPair<WriteCvtI2F, [HWPort1], 4>;
defm : HWWriteResPair<WriteCvtF2F, [HWPort1], 3>; defm : HWWriteResPair<WriteCvtF2F, [HWPort1], 3>;
defm : HWWriteResPair<WriteFMA, [HWPort01], 5>; defm : HWWriteResPair<WriteFMA, [HWPort01], 5>;
defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1>; defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1>;
defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1>;
defm : HWWriteResPair<WriteFBlend, [HWPort015], 1>; defm : HWWriteResPair<WriteFBlend, [HWPort015], 1>;
defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3>;
defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3>;
defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>;
// Vector integer operations. // Vector integer operations.
def : WriteRes<WriteVecStore, [HWPort237, HWPort4]>; def : WriteRes<WriteVecStore, [HWPort237, HWPort4]>;
def : WriteRes<WriteVecLoad, [HWPort23]> { let Latency = 5; } def : WriteRes<WriteVecLoad, [HWPort23]> { let Latency = 5; }
def : WriteRes<WriteVecMove, [HWPort015]>; def : WriteRes<WriteVecMove, [HWPort015]>;
defm : HWWriteResPair<WriteVecShift, [HWPort0], 1>; defm : HWWriteResPair<WriteVecShift, [HWPort0], 1>;
defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1>; defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1>;
defm : HWWriteResPair<WriteVecALU, [HWPort15], 1>; defm : HWWriteResPair<WriteVecALU, [HWPort15], 1>;
defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5>; defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5>;
defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>;
defm : HWWriteResPair<WriteShuffle, [HWPort5], 1>; defm : HWWriteResPair<WriteShuffle, [HWPort5], 1>;
defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1>;
defm : HWWriteResPair<WriteBlend, [HWPort15], 1>; defm : HWWriteResPair<WriteBlend, [HWPort15], 1>;
defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3>;
defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3>;
defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2]>; defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2]>;
defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 2, [2, 1]>; defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 2, [2, 1]>;
defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 6, [1, 2]>; defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 6, [1, 2]>;
// String instructions. // String instructions.
// Packed Compare Implicit Length Strings, Return Mask // Packed Compare Implicit Length Strings, Return Mask
def : WriteRes<WritePCmpIStrM, [HWPort0]> { def : WriteRes<WritePCmpIStrM, [HWPort0]> {
▲ Show 20 Lines • Show All 532 Lines • ▼ Show 20 Linesdef HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr", def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr", "MMX_MOVQ2DQrr",
"MMX_PALIGNRrri", "MMX_PALIGNRrri",
"MMX_PSHUFBrr",
"MMX_PSHUFWri", "MMX_PSHUFWri",
"MMX_PUNPCKHBWirr", "MMX_PUNPCKHBWirr",
"MMX_PUNPCKHDQirr", "MMX_PUNPCKHDQirr",
"MMX_PUNPCKHWDirr", "MMX_PUNPCKHWDirr",
"MMX_PUNPCKLBWirr", "MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr", "MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr", "MMX_PUNPCKLWDirr",
"(V?)ANDNPD(Y?)rr", "(V?)ANDNPD(Y?)rr",
Show All 21 Linesdef: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"(V?)PACKSSWB(Y?)rr", "(V?)PACKSSWB(Y?)rr",
"(V?)PACKUSDW(Y?)rr", "(V?)PACKUSDW(Y?)rr",
"(V?)PACKUSWB(Y?)rr", "(V?)PACKUSWB(Y?)rr",
"(V?)PALIGNR(Y?)rri", "(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri", "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPD(Y?)ri", "VPERMILPD(Y?)ri",
"VPERMILPD(Y?)rr",
"VPERMILPS(Y?)ri", "VPERMILPS(Y?)ri",
"VPERMILPS(Y?)rr",
"(V?)PMOVSXBDrr", "(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr", "(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr", "(V?)PMOVSXBWrr",
"(V?)PMOVSXDQrr", "(V?)PMOVSXDQrr",
"(V?)PMOVSXWDrr", "(V?)PMOVSXWDrr",
"(V?)PMOVSXWQrr", "(V?)PMOVSXWQrr",
"(V?)PMOVZXBDrr", "(V?)PMOVZXBDrr",
"(V?)PMOVZXBQrr", "(V?)PMOVZXBQrr",
"(V?)PMOVZXBWrr", "(V?)PMOVZXBWrr",
"(V?)PMOVZXDQrr", "(V?)PMOVZXDQrr",
"(V?)PMOVZXWDrr", "(V?)PMOVZXWDrr",
"(V?)PMOVZXWQrr", "(V?)PMOVZXWQrr",
"(V?)PSHUFB(Y?)rr",
"(V?)PSHUFD(Y?)ri", "(V?)PSHUFD(Y?)ri",
"(V?)PSHUFHW(Y?)ri", "(V?)PSHUFHW(Y?)ri",
"(V?)PSHUFLW(Y?)ri", "(V?)PSHUFLW(Y?)ri",
"(V?)PSLLDQ(Y?)ri", "(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri",
"(V?)PUNPCKHBW(Y?)rr", "(V?)PUNPCKHBW(Y?)rr",
"(V?)PUNPCKHDQ(Y?)rr", "(V?)PUNPCKHDQ(Y?)rr",
"(V?)PUNPCKHQDQ(Y?)rr", "(V?)PUNPCKHQDQ(Y?)rr",
▲ Show 20 Lines • Show All 986 Lines • ▼ Show 20 Linesdef: InstRW<[HWWriteResGroup51], (instregex "VBROADCASTSDYrr",
"VPBROADCASTBYrr", "VPBROADCASTBYrr",
"VPBROADCASTBrr", "VPBROADCASTBrr",
"VPBROADCASTDYrr", "VPBROADCASTDYrr",
"VPBROADCASTQYrr", "VPBROADCASTQYrr",
"VPBROADCASTWYrr", "VPBROADCASTWYrr",
"VPBROADCASTWrr", "VPBROADCASTWrr",
"VPERM2F128rr", "VPERM2F128rr",
"VPERM2I128rr", "VPERM2I128rr",
"VPERMDYrr",
"VPERMPDYri", "VPERMPDYri",
"VPERMPSYrr",
"VPERMQYri", "VPERMQYri",
"VPMOVSXBDYrr", "VPMOVSXBDYrr",
"VPMOVSXBQYrr", "VPMOVSXBQYrr",
"VPMOVSXBWYrr", "VPMOVSXBWYrr",
"VPMOVSXDQYrr", "VPMOVSXDQYrr",
"VPMOVSXWDYrr", "VPMOVSXWDYrr",
"VPMOVSXWQYrr", "VPMOVSXWQYrr",
"VPMOVZXBDYrr", "VPMOVZXBDYrr",
▲ Show 20 Lines • Show All 1,312 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
defm : SBWriteResPair<WriteFDiv, [SBPort0], 24>; defm : SBWriteResPair<WriteFDiv, [SBPort0], 24>;
defm : SBWriteResPair<WriteFRcp, [SBPort0], 5>; defm : SBWriteResPair<WriteFRcp, [SBPort0], 5>;
defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5>; defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5>;
defm : SBWriteResPair<WriteFSqrt, [SBPort0], 14>; defm : SBWriteResPair<WriteFSqrt, [SBPort0], 14>;
defm : SBWriteResPair<WriteCvtF2I, [SBPort1], 3>; defm : SBWriteResPair<WriteCvtF2I, [SBPort1], 3>;
defm : SBWriteResPair<WriteCvtI2F, [SBPort1], 4>; defm : SBWriteResPair<WriteCvtI2F, [SBPort1], 4>;
defm : SBWriteResPair<WriteCvtF2F, [SBPort1], 3>; defm : SBWriteResPair<WriteCvtF2F, [SBPort1], 3>;
defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1>; defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteFBlend, [SBPort05], 1>; defm : SBWriteResPair<WriteFBlend, [SBPort05], 1>;
defm : SBWriteResPair<WriteFVarBlend, [SBPort0, SBPort5], 2>; defm : SBWriteResPair<WriteFVarBlend, [SBPort0, SBPort5], 2>;
// Vector integer operations. // Vector integer operations.
def : WriteRes<WriteVecStore, [SBPort23, SBPort4]>; def : WriteRes<WriteVecStore, [SBPort23, SBPort4]>;
def : WriteRes<WriteVecLoad, [SBPort23]> { let Latency = 6; } def : WriteRes<WriteVecLoad, [SBPort23]> { let Latency = 6; }
def : WriteRes<WriteVecMove, [SBPort05]>; def : WriteRes<WriteVecMove, [SBPort05]>;
defm : SBWriteResPair<WriteVecShift, [SBPort5], 1>; defm : SBWriteResPair<WriteVecShift, [SBPort5], 1>;
defm : SBWriteResPair<WriteVecLogic, [SBPort5], 1>; defm : SBWriteResPair<WriteVecLogic, [SBPort5], 1>;
defm : SBWriteResPair<WriteVecALU, [SBPort1], 3>; defm : SBWriteResPair<WriteVecALU, [SBPort1], 3>;
defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5>; defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5>;
defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; // TODO this is probably wrong for 256/512-bit for the "generic" model defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; // TODO this is probably wrong for 256/512-bit for the "generic" model
defm : SBWriteResPair<WriteShuffle, [SBPort5], 1>; defm : SBWriteResPair<WriteShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1>;
defm : SBWriteResPair<WriteBlend, [SBPort15], 1>; defm : SBWriteResPair<WriteBlend, [SBPort15], 1>;
defm : SBWriteResPair<WriteVarBlend, [SBPort1, SBPort5], 2>; defm : SBWriteResPair<WriteVarBlend, [SBPort1, SBPort5], 2>;
defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 5, [1,2], 3>; defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 5, [1,2], 3>;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions. // Horizontal add/sub instructions.
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteFence, [SBPort23, SBPort4]>; def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
def : WriteRes<WriteNop, []>; def : WriteRes<WriteNop, []>;
// AVX2/FMA is not supported on that architecture, but we should define the basic // AVX2/FMA is not supported on that architecture, but we should define the basic
// scheduling resources anyway. // scheduling resources anyway.
defm : SBWriteResPair<WriteFShuffle256, [SBPort0], 1>; defm : SBWriteResPair<WriteFShuffle256, [SBPort0], 1>;
defm : SBWriteResPair<WriteFVarShuffle256, [SBPort0], 1>;
defm : SBWriteResPair<WriteShuffle256, [SBPort0], 1>; defm : SBWriteResPair<WriteShuffle256, [SBPort0], 1>;
defm : SBWriteResPair<WriteVarShuffle256, [SBPort0], 1>;
defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1>; defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1>;
defm : SBWriteResPair<WriteFMA, [SBPort01], 5>; defm : SBWriteResPair<WriteFMA, [SBPort01], 5>;
// Remaining SNB instrs. // Remaining SNB instrs.
def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linesdef: InstRW<[SBWriteResGroup2], (instregex "FDECSTP",
"(V?)MOVSLDUP(Y?)rr", "(V?)MOVSLDUP(Y?)rr",
"(V?)MOVSSrr", "(V?)MOVSSrr",
"(V?)MOVUPD(Y?)rr", "(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr", "(V?)MOVUPS(Y?)rr",
"(V?)ORPD(Y?)rr", "(V?)ORPD(Y?)rr",
"(V?)ORPS(Y?)rr", "(V?)ORPS(Y?)rr",
"VPERM2F128rr", "VPERM2F128rr",
"VPERMILPD(Y?)ri", "VPERMILPD(Y?)ri",
"VPERMILPD(Y?)rr",
"VPERMILPS(Y?)ri", "VPERMILPS(Y?)ri",
"VPERMILPS(Y?)rr",
"(V?)SHUFPD(Y?)rri", "(V?)SHUFPD(Y?)rri",
"(V?)SHUFPS(Y?)rri", "(V?)SHUFPS(Y?)rri",
"(V?)UNPCKHPD(Y?)rr", "(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr", "(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr", "(V?)UNPCKLPD(Y?)rr",
"(V?)UNPCKLPS(Y?)rr", "(V?)UNPCKLPS(Y?)rr",
"(V?)XORPD(Y?)rr", "(V?)XORPD(Y?)rr",
"(V?)XORPS(Y?)rr")>; "(V?)XORPS(Y?)rr")>;
Show All 37 Linesdef SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr", def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr",
"MMX_PABSDrr", "MMX_PABSDrr",
"MMX_PABSWrr", "MMX_PABSWrr",
"MMX_PADDQirr", "MMX_PADDQirr",
"MMX_PALIGNRrri", "MMX_PALIGNRrri",
"MMX_PSHUFBrr",
"MMX_PSIGNBrr", "MMX_PSIGNBrr",
"MMX_PSIGNDrr", "MMX_PSIGNDrr",
"MMX_PSIGNWrr", "MMX_PSIGNWrr",
"(V?)PABSBrr", "(V?)PABSBrr",
"(V?)PABSDrr", "(V?)PABSDrr",
"(V?)PABSWrr", "(V?)PABSWrr",
"(V?)PACKSSDWrr", "(V?)PACKSSDWrr",
"(V?)PACKSSWBrr", "(V?)PACKSSWBrr",
Show All 37 Linesdef: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr",
"(V?)PMOVSXWDrr", "(V?)PMOVSXWDrr",
"(V?)PMOVSXWQrr", "(V?)PMOVSXWQrr",
"(V?)PMOVZXBDrr", "(V?)PMOVZXBDrr",
"(V?)PMOVZXBQrr", "(V?)PMOVZXBQrr",
"(V?)PMOVZXBWrr", "(V?)PMOVZXBWrr",
"(V?)PMOVZXDQrr", "(V?)PMOVZXDQrr",
"(V?)PMOVZXWDrr", "(V?)PMOVZXWDrr",
"(V?)PMOVZXWQrr", "(V?)PMOVZXWQrr",
"(V?)PSHUFBrr",
"(V?)PSHUFDri", "(V?)PSHUFDri",
"(V?)PSHUFHWri", "(V?)PSHUFHWri",
"(V?)PSHUFLWri", "(V?)PSHUFLWri",
"(V?)PSIGNBrr", "(V?)PSIGNBrr",
"(V?)PSIGNDrr", "(V?)PSIGNDrr",
"(V?)PSIGNWrr", "(V?)PSIGNWrr",
"(V?)PSLLDQri", "(V?)PSLLDQri",
"(V?)PSRLDQri", "(V?)PSRLDQri",
▲ Show 20 Lines • Show All 1,541 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3>; // Floating point add/sub/compare. defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3>; // Floating point add/sub/compare.
defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication. defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication.
defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12>; // 10-14 cycles. // Floating point division. defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12>; // 10-14 cycles. // Floating point division.
defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square root. defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square root.
defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate. defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate.
defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate. defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate.
defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add. defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add.
defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles. defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles.
defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1>; // Floating point vector shuffles.
defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends. defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends.
defm : SKLWriteResPair<WriteFVarBlend, [SKLPort5], 2, [2]>; // Fp vector variable blends. defm : SKLWriteResPair<WriteFVarBlend, [SKLPort5], 2, [2]>; // Fp vector variable blends.
// FMA Scheduling helper class. // FMA Scheduling helper class.
// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
// Vector integer operations. // Vector integer operations.
def : WriteRes<WriteVecLoad, [SKLPort23]> { let Latency = 6; } def : WriteRes<WriteVecLoad, [SKLPort23]> { let Latency = 6; }
def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>; def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>;
def : WriteRes<WriteVecMove, [SKLPort015]>; def : WriteRes<WriteVecMove, [SKLPort015]>;
defm : SKLWriteResPair<WriteVecALU, [SKLPort15], 1>; // Vector integer ALU op, no logicals. defm : SKLWriteResPair<WriteVecALU, [SKLPort15], 1>; // Vector integer ALU op, no logicals.
defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1>; // Vector integer shifts. defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1>; // Vector integer shifts.
defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply. defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply.
defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>;
defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1>; // Vector shuffles. defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1>; // Vector shuffles.
defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1>; // Vector shuffles.
defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends. defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends.
defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable blends. defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable blends.
defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD. defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD.
// Vector bitwise operations. // Vector bitwise operations.
// These are often used on both floating point and integer vectors. // These are often used on both floating point and integer vectors.
defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1>; // Vector and/or/xor. defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1>; // Vector and/or/xor.
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesdef : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
// Catch-all for expensive system instructions. // Catch-all for expensive system instructions.
def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
// AVX2. // AVX2.
defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3>; // Fp 256-bit width vector shuffles. defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3>; // Fp 256-bit width vector shuffles.
defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3>; // Fp 256-bit width vector variable shuffles.
defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3>; // 256-bit width vector shuffles. defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3>; // 256-bit width vector shuffles.
defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3>; // 256-bit width vector variable shuffles.
defm : SKLWriteResPair<WriteVarVecShift, [SKLPort0, SKLPort5], 2, [2, 1]>; // Variable vector shifts. defm : SKLWriteResPair<WriteVarVecShift, [SKLPort0, SKLPort5], 2, [2, 1]>; // Variable vector shifts.
// Old microcoded instructions that nobody use. // Old microcoded instructions that nobody use.
def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
// Fence instructions. // Fence instructions.
def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesdef SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r", def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"COM_FST0r", "COM_FST0r",
"MMX_MOVD64rr", "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MMX_PALIGNRrri", "MMX_PALIGNRrri",
"MMX_PSHUFBrr",
"MMX_PSHUFWri", "MMX_PSHUFWri",
"MMX_PUNPCKHBWirr", "MMX_PUNPCKHBWirr",
"MMX_PUNPCKHDQirr", "MMX_PUNPCKHDQirr",
"MMX_PUNPCKHWDirr", "MMX_PUNPCKHWDirr",
"MMX_PUNPCKLBWirr", "MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr", "MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr", "MMX_PUNPCKLWDirr",
"UCOM_FPr", "UCOM_FPr",
Show All 13 Linesdef: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"(V?)PACKSSWB(Y?)rr", "(V?)PACKSSWB(Y?)rr",
"(V?)PACKUSDW(Y?)rr", "(V?)PACKUSDW(Y?)rr",
"(V?)PACKUSWB(Y?)rr", "(V?)PACKUSWB(Y?)rr",
"(V?)PALIGNR(Y?)rri", "(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri", "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPD(Y?)ri", "VPERMILPD(Y?)ri",
"VPERMILPD(Y?)rr",
"VPERMILPS(Y?)ri", "VPERMILPS(Y?)ri",
"VPERMILPS(Y?)rr",
"(V?)PMOVSXBDrr", "(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr", "(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr", "(V?)PMOVSXBWrr",
"(V?)PMOVSXDQrr", "(V?)PMOVSXDQrr",
"(V?)PMOVSXWDrr", "(V?)PMOVSXWDrr",
"(V?)PMOVSXWQrr", "(V?)PMOVSXWQrr",
"(V?)PMOVZXBDrr", "(V?)PMOVZXBDrr",
"(V?)PMOVZXBQrr", "(V?)PMOVZXBQrr",
"(V?)PMOVZXBWrr", "(V?)PMOVZXBWrr",
"(V?)PMOVZXDQrr", "(V?)PMOVZXDQrr",
"(V?)PMOVZXWDrr", "(V?)PMOVZXWDrr",
"(V?)PMOVZXWQrr", "(V?)PMOVZXWQrr",
"(V?)PSHUFB(Y?)rr",
"(V?)PSHUFD(Y?)ri", "(V?)PSHUFD(Y?)ri",
"(V?)PSHUFHW(Y?)ri", "(V?)PSHUFHW(Y?)ri",
"(V?)PSHUFLW(Y?)ri", "(V?)PSHUFLW(Y?)ri",
"(V?)PSLLDQ(Y?)ri", "(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri",
"(V?)PUNPCKHBW(Y?)rr", "(V?)PUNPCKHBW(Y?)rr",
"(V?)PUNPCKHDQ(Y?)rr", "(V?)PUNPCKHDQ(Y?)rr",
"(V?)PUNPCKHQDQ(Y?)rr", "(V?)PUNPCKHQDQ(Y?)rr",
▲ Show 20 Lines • Show All 455 Lines • ▼ Show 20 Linesdef: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0",
"VINSERTI128rr", "VINSERTI128rr",
"VPBROADCASTB(Y?)rr", "VPBROADCASTB(Y?)rr",
"VPBROADCASTDYrr", "VPBROADCASTDYrr",
"VPBROADCASTQYrr", "VPBROADCASTQYrr",
"VPBROADCASTW(Y?)rr", "VPBROADCASTW(Y?)rr",
"(V?)PCMPGTQ(Y?)rr", "(V?)PCMPGTQ(Y?)rr",
"VPERM2F128rr", "VPERM2F128rr",
"VPERM2I128rr", "VPERM2I128rr",
"VPERMDYrr",
"VPERMPDYri", "VPERMPDYri",
"VPERMPSYrr",
"VPERMQYri", "VPERMQYri",
"VPMOVSXBDYrr", "VPMOVSXBDYrr",
"VPMOVSXBQYrr", "VPMOVSXBQYrr",
"VPMOVSXBWYrr", "VPMOVSXBWYrr",
"VPMOVSXDQYrr", "VPMOVSXDQYrr",
"VPMOVSXWDYrr", "VPMOVSXWDYrr",
"VPMOVSXWQYrr", "VPMOVSXWQYrr",
"VPMOVZXBDYrr", "VPMOVZXBDYrr",
▲ Show 20 Lines • Show All 2,024 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
defm : SKXWriteResPair<WriteFAdd, [SKXPort1], 3>; // Floating point add/sub/compare. defm : SKXWriteResPair<WriteFAdd, [SKXPort1], 3>; // Floating point add/sub/compare.
defm : SKXWriteResPair<WriteFMul, [SKXPort0], 5>; // Floating point multiplication. defm : SKXWriteResPair<WriteFMul, [SKXPort0], 5>; // Floating point multiplication.
defm : SKXWriteResPair<WriteFDiv, [SKXPort0], 12>; // 10-14 cycles. // Floating point division. defm : SKXWriteResPair<WriteFDiv, [SKXPort0], 12>; // 10-14 cycles. // Floating point division.
defm : SKXWriteResPair<WriteFSqrt, [SKXPort0], 15>; // Floating point square root. defm : SKXWriteResPair<WriteFSqrt, [SKXPort0], 15>; // Floating point square root.
defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 5>; // Floating point reciprocal estimate. defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 5>; // Floating point reciprocal estimate.
defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 5>; // Floating point reciprocal square root estimate. defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 5>; // Floating point reciprocal square root estimate.
defm : SKXWriteResPair<WriteFMA, [SKXPort015], 4>; // Fused Multiply Add. defm : SKXWriteResPair<WriteFMA, [SKXPort015], 4>; // Fused Multiply Add.
defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1>; // Floating point vector shuffles. defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1>; // Floating point vector shuffles.
defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1>; // Floating point vector variable shuffles.
defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1>; // Floating point vector blends. defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1>; // Floating point vector blends.
defm : SKXWriteResPair<WriteFVarBlend, [SKXPort5], 2, [2]>; // Fp vector variable blends. defm : SKXWriteResPair<WriteFVarBlend, [SKXPort5], 2, [2]>; // Fp vector variable blends.
// FMA Scheduling helper class. // FMA Scheduling helper class.
// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
// Vector integer operations. // Vector integer operations.
def : WriteRes<WriteVecLoad, [SKXPort23]> { let Latency = 5; } def : WriteRes<WriteVecLoad, [SKXPort23]> { let Latency = 5; }
def : WriteRes<WriteVecStore, [SKXPort237, SKXPort4]>; def : WriteRes<WriteVecStore, [SKXPort237, SKXPort4]>;
def : WriteRes<WriteVecMove, [SKXPort015]>; def : WriteRes<WriteVecMove, [SKXPort015]>;
defm : SKXWriteResPair<WriteVecALU, [SKXPort15], 1>; // Vector integer ALU op, no logicals. defm : SKXWriteResPair<WriteVecALU, [SKXPort15], 1>; // Vector integer ALU op, no logicals.
defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1>; // Vector integer shifts. defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1>; // Vector integer shifts.
defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5>; // Vector integer multiply. defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5>; // Vector integer multiply.
defm : SKXWriteResPair<WritePMULLD, [SKXPort015], 10, [2], 2, 6>; // Vector integer multiply. defm : SKXWriteResPair<WritePMULLD, [SKXPort015], 10, [2], 2, 6>; // Vector integer multiply.
defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1>; // Vector shuffles. defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1>; // Vector shuffles.
defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1>; // Vector variable shuffles.
defm : SKXWriteResPair<WriteBlend, [SKXPort15], 1>; // Vector blends. defm : SKXWriteResPair<WriteBlend, [SKXPort15], 1>; // Vector blends.
defm : SKXWriteResPair<WriteVarBlend, [SKXPort5], 2, [2]>; // Vector variable blends. defm : SKXWriteResPair<WriteVarBlend, [SKXPort5], 2, [2]>; // Vector variable blends.
defm : SKXWriteResPair<WriteMPSAD, [SKXPort0, SKXPort5], 6, [1, 2]>; // Vector MPSAD. defm : SKXWriteResPair<WriteMPSAD, [SKXPort0, SKXPort5], 6, [1, 2]>; // Vector MPSAD.
// Vector bitwise operations. // Vector bitwise operations.
// These are often used on both floating point and integer vectors. // These are often used on both floating point and integer vectors.
defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1>; // Vector and/or/xor. defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1>; // Vector and/or/xor.
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesdef : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
// Catch-all for expensive system instructions. // Catch-all for expensive system instructions.
def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
// AVX2. // AVX2.
defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3>; // Fp 256-bit width vector shuffles. defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3>; // Fp 256-bit width vector shuffles.
defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3>; // Fp 256-bit width vector variable shuffles.
defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3>; // 256-bit width vector shuffles. defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3>; // 256-bit width vector shuffles.
defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3>; // 256-bit width vector variable shuffles.
defm : SKXWriteResPair<WriteVarVecShift, [SKXPort0, SKXPort5], 2, [2, 1]>; // Variable vector shifts. defm : SKXWriteResPair<WriteVarVecShift, [SKXPort0, SKXPort5], 2, [2, 1]>; // Variable vector shifts.
// Old microcoded instructions that nobody use. // Old microcoded instructions that nobody use.
def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
// Fence instructions. // Fence instructions.
def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>; def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Linesdef: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"INSERTPSrr", "INSERTPSrr",
"KMOVBkr", "KMOVBkr",
"KMOVDkr", "KMOVDkr",
"KMOVQkr", "KMOVQkr",
"KMOVWkr", "KMOVWkr",
"MMX_MOVD64rr", "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MMX_PALIGNRrri", "MMX_PALIGNRrri",
"MMX_PSHUFBrr",
"MMX_PSHUFWri", "MMX_PSHUFWri",
"MMX_PUNPCKHBWirr", "MMX_PUNPCKHBWirr",
"MMX_PUNPCKHDQirr", "MMX_PUNPCKHDQirr",
"MMX_PUNPCKHWDirr", "MMX_PUNPCKHWDirr",
"MMX_PUNPCKLBWirr", "MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr", "MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr", "MMX_PUNPCKLWDirr",
"MOV64toPQIrr", "MOV64toPQIrr",
Show All 18 Linesdef: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"PMOVSXWDrr", "PMOVSXWDrr",
"PMOVSXWQrr", "PMOVSXWQrr",
"PMOVZXBDrr", "PMOVZXBDrr",
"PMOVZXBQrr", "PMOVZXBQrr",
"PMOVZXBWrr", "PMOVZXBWrr",
"PMOVZXDQrr", "PMOVZXDQrr",
"PMOVZXWDrr", "PMOVZXWDrr",
"PMOVZXWQrr", "PMOVZXWQrr",
"PSHUFBrr",
"PSHUFDri", "PSHUFDri",
"PSHUFHWri", "PSHUFHWri",
"PSHUFLWri", "PSHUFLWri",
"PSLLDQri", "PSLLDQri",
"PSRLDQri", "PSRLDQri",
"PUNPCKHBWrr", "PUNPCKHBWrr",
"PUNPCKHDQrr", "PUNPCKHDQrr",
"PUNPCKHQDQrr", "PUNPCKHQDQrr",
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesdef: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"VPALIGNRZ256rri", "VPALIGNRZ256rri",
"VPALIGNRZrri", "VPALIGNRZrri",
"VPALIGNRrri", "VPALIGNRrri",
"VPBLENDWYrri", "VPBLENDWYrri",
"VPBLENDWrri", "VPBLENDWrri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPDYri", "VPERMILPDYri",
"VPERMILPDYrr",
"VPERMILPDZ128ri", "VPERMILPDZ128ri",
"VPERMILPDZ128rr",
"VPERMILPDZ256ri", "VPERMILPDZ256ri",
"VPERMILPDZ256rr",
"VPERMILPDZri", "VPERMILPDZri",
"VPERMILPDZrr",
"VPERMILPDri", "VPERMILPDri",
"VPERMILPDrr",
"VPERMILPSYri", "VPERMILPSYri",
"VPERMILPSYrr",
"VPERMILPSZ128ri", "VPERMILPSZ128ri",
"VPERMILPSZ128rr",
"VPERMILPSZ256ri", "VPERMILPSZ256ri",
"VPERMILPSZ256rr",
"VPERMILPSZri", "VPERMILPSZri",
"VPERMILPSZrr",
"VPERMILPSri", "VPERMILPSri",
"VPERMILPSrr",
"VPMOVSXBDrr", "VPMOVSXBDrr",
"VPMOVSXBQrr", "VPMOVSXBQrr",
"VPMOVSXBWrr", "VPMOVSXBWrr",
"VPMOVSXDQrr", "VPMOVSXDQrr",
"VPMOVSXWDrr", "VPMOVSXWDrr",
"VPMOVSXWQrr", "VPMOVSXWQrr",
"VPMOVZXBDrr", "VPMOVZXBDrr",
"VPMOVZXBQrr", "VPMOVZXBQrr",
"VPMOVZXBWrr", "VPMOVZXBWrr",
"VPMOVZXDQrr", "VPMOVZXDQrr",
"VPMOVZXWDrr", "VPMOVZXWDrr",
"VPMOVZXWQrr", "VPMOVZXWQrr",
"VPSHUFBYrr",
"VPSHUFBZ128rr",
"VPSHUFBZ256rr",
"VPSHUFBZrr",
"VPSHUFBrr",
"VPSHUFDYri", "VPSHUFDYri",
"VPSHUFDZ128ri", "VPSHUFDZ128ri",
"VPSHUFDZ256ri", "VPSHUFDZ256ri",
"VPSHUFDZri", "VPSHUFDZri",
"VPSHUFDri", "VPSHUFDri",
"VPSHUFHWYri", "VPSHUFHWYri",
"VPSHUFHWZ128ri", "VPSHUFHWZ128ri",
"VPSHUFHWZ256ri", "VPSHUFHWZ256ri",
▲ Show 20 Lines • Show All 1,277 Lines • ▼ Show 20 Linesdef: InstRW<[SKXWriteResGroup32], (instregex "ADD_FPrST0",
"VPCMPUWZ128rri", "VPCMPUWZ128rri",
"VPCMPUWZ256rri", "VPCMPUWZ256rri",
"VPCMPUWZrri", "VPCMPUWZrri",
"VPCMPWZ128rri", "VPCMPWZ128rri",
"VPCMPWZ256rri", "VPCMPWZ256rri",
"VPCMPWZrri", "VPCMPWZrri",
"VPERM2F128rr", "VPERM2F128rr",
"VPERM2I128rr", "VPERM2I128rr",
"VPERMDYrr",
"VPERMDZ256rr",
"VPERMDZrr",
"VPERMI2D128rr",
"VPERMI2D256rr",
"VPERMI2Drr",
"VPERMI2PD128rr",
"VPERMI2PD256rr",
"VPERMI2PDrr",
"VPERMI2PS128rr",
"VPERMI2PS256rr",
"VPERMI2PSrr",
"VPERMI2Q128rr",
"VPERMI2Q256rr",
"VPERMI2Qrr",
"VPERMPDYri", "VPERMPDYri",
"VPERMPDZ256ri", "VPERMPDZ256ri",
"VPERMPDZ256rr",
"VPERMPDZri", "VPERMPDZri",
"VPERMPDZrr",
"VPERMPSYrr",
"VPERMPSZ256rr",
"VPERMPSZrr",
"VPERMQYri", "VPERMQYri",
"VPERMQZ256ri", "VPERMQZ256ri",
"VPERMQZ256rr",
"VPERMQZri", "VPERMQZri",
"VPERMQZrr",
"VPERMT2D128rr",
"VPERMT2D256rr",
"VPERMT2Drr",
"VPERMT2PD128rr",
"VPERMT2PD256rr",
"VPERMT2PDrr",
"VPERMT2PS128rr",
"VPERMT2PS256rr",
"VPERMT2PSrr",
"VPERMT2Q128rr",
"VPERMT2Q256rr",
"VPERMT2Qrr",
"VPMAXSQZ128rr", "VPMAXSQZ128rr",
"VPMAXSQZ256rr", "VPMAXSQZ256rr",
"VPMAXSQZrr", "VPMAXSQZrr",
"VPMAXUQZ128rr", "VPMAXUQZ128rr",
"VPMAXUQZ256rr", "VPMAXUQZ256rr",
"VPMAXUQZrr", "VPMAXUQZrr",
"VPMINSQZ128rr", "VPMINSQZ128rr",
"VPMINSQZ256rr", "VPMINSQZ256rr",
▲ Show 20 Lines • Show All 4,161 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86Schedule.td

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare. defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare.
defm WriteFMul : X86SchedWritePair; // Floating point multiplication. defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
defm WriteFDiv : X86SchedWritePair; // Floating point division. defm WriteFDiv : X86SchedWritePair; // Floating point division.
defm WriteFSqrt : X86SchedWritePair; // Floating point square root. defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate. defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate.
defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate. defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
defm WriteFMA : X86SchedWritePair; // Fused Multiply Add. defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles. defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
defm WriteFVarShuffle : X86SchedWritePair; // Floating point vector variable shuffles.
defm WriteFBlend : X86SchedWritePair; // Floating point vector blends. defm WriteFBlend : X86SchedWritePair; // Floating point vector blends.
defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends. defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends.
// FMA Scheduling helper class. // FMA Scheduling helper class.
class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
// Horizontal Add/Sub (float and integer) // Horizontal Add/Sub (float and integer)
defm WriteFHAdd : X86SchedWritePair; defm WriteFHAdd : X86SchedWritePair;
defm WritePHAdd : X86SchedWritePair; defm WritePHAdd : X86SchedWritePair;
// Vector integer operations. // Vector integer operations.
def WriteVecLoad : SchedWrite; def WriteVecLoad : SchedWrite;
def WriteVecStore : SchedWrite; def WriteVecStore : SchedWrite;
def WriteVecMove : SchedWrite; def WriteVecMove : SchedWrite;
defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals. defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals.
defm WriteVecShift : X86SchedWritePair; // Vector integer shifts. defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply. defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply.
defm WritePMULLD : X86SchedWritePair; // PMULLD defm WritePMULLD : X86SchedWritePair; // PMULLD
defm WriteShuffle : X86SchedWritePair; // Vector shuffles. defm WriteShuffle : X86SchedWritePair; // Vector shuffles.
defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles.
defm WriteBlend : X86SchedWritePair; // Vector blends. defm WriteBlend : X86SchedWritePair; // Vector blends.
defm WriteVarBlend : X86SchedWritePair; // Vector variable blends. defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD. defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
// Vector bitwise operations. // Vector bitwise operations.
// These are often used on both floating point and integer vectors. // These are often used on both floating point and integer vectors.
defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor. defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
Show All 28 Lines
// Carry-less multiplication instructions. // Carry-less multiplication instructions.
defm WriteCLMul : X86SchedWritePair; defm WriteCLMul : X86SchedWritePair;
// Catch-all for expensive system instructions. // Catch-all for expensive system instructions.
def WriteSystem : SchedWrite; def WriteSystem : SchedWrite;
// AVX2. // AVX2.
defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles. defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
defm WriteFVarShuffle256 : X86SchedWritePair; // Fp 256-bit width variable shuffles.
defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles. defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
defm WriteVarShuffle256 : X86SchedWritePair; // 256-bit width vector variable shuffles.
defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts. defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts.
// Old microcoded instructions that nobody use. // Old microcoded instructions that nobody use.
def WriteMicrocoded : SchedWrite; def WriteMicrocoded : SchedWrite;
// Fence instructions. // Fence instructions.
def WriteFence : SchedWrite; def WriteFence : SchedWrite;
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llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines
defm : JWriteResFpuPair<WriteFAdd, [JFPU0, JFPA], 3>; defm : JWriteResFpuPair<WriteFAdd, [JFPU0, JFPA], 3>;
defm : JWriteResFpuPair<WriteFMul, [JFPU1, JFPM], 2>; defm : JWriteResFpuPair<WriteFMul, [JFPU1, JFPM], 2>;
defm : JWriteResFpuPair<WriteFMA, [JFPU1, JFPM], 2>; // NOTE: Doesn't exist on Jaguar. defm : JWriteResFpuPair<WriteFMA, [JFPU1, JFPM], 2>; // NOTE: Doesn't exist on Jaguar.
defm : JWriteResFpuPair<WriteFRcp, [JFPU1, JFPM], 2>; defm : JWriteResFpuPair<WriteFRcp, [JFPU1, JFPM], 2>;
defm : JWriteResFpuPair<WriteFRsqrt, [JFPU1, JFPM], 2>; defm : JWriteResFpuPair<WriteFRsqrt, [JFPU1, JFPM], 2>;
defm : JWriteResFpuPair<WriteFDiv, [JFPU1, JFPM], 19, [1, 19]>; defm : JWriteResFpuPair<WriteFDiv, [JFPU1, JFPM], 19, [1, 19]>;
defm : JWriteResFpuPair<WriteFSqrt, [JFPU1, JFPM], 21, [1, 21]>; defm : JWriteResFpuPair<WriteFSqrt, [JFPU1, JFPM], 21, [1, 21]>;
defm : JWriteResFpuPair<WriteFShuffle, [JFPU01, JFPX], 1>; defm : JWriteResFpuPair<WriteFShuffle, [JFPU01, JFPX], 1>;
defm : JWriteResFpuPair<WriteFVarShuffle, [JFPU01, JFPX], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteFBlend, [JFPU01, JFPX], 1>; defm : JWriteResFpuPair<WriteFBlend, [JFPU01, JFPX], 1>;
defm : JWriteResFpuPair<WriteFVarBlend, [JFPU01, JFPX], 2, [1, 4], 3>; defm : JWriteResFpuPair<WriteFVarBlend, [JFPU01, JFPX], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteFShuffle256, [JFPU01, JFPX], 1>; defm : JWriteResFpuPair<WriteFShuffle256, [JFPU01, JFPX], 1>;
defm : JWriteResFpuPair<WriteFVarShuffle256, [JFPU01, JFPX], 1>; // NOTE: Doesn't exist on Jaguar.
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Conversions. // Conversions.
// FIXME: integer pipes // FIXME: integer pipes
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
defm : JWriteResFpuPair<WriteCvtF2I, [JFPU1, JSTC], 3>; // Float -> Integer. defm : JWriteResFpuPair<WriteCvtF2I, [JFPU1, JSTC], 3>; // Float -> Integer.
defm : JWriteResFpuPair<WriteCvtI2F, [JFPU1, JSTC], 3>; // Integer -> Float. defm : JWriteResFpuPair<WriteCvtI2F, [JFPU1, JSTC], 3>; // Integer -> Float.
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def : WriteRes<WriteVecMove, [JFPU01, JVALU]>; def : WriteRes<WriteVecMove, [JFPU01, JVALU]>;
defm : JWriteResFpuPair<WriteVecALU, [JFPU01, JVALU], 1>; defm : JWriteResFpuPair<WriteVecALU, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVecShift, [JFPU01, JVALU], 1>; defm : JWriteResFpuPair<WriteVecShift, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVecIMul, [JFPU0, JVIMUL], 2>; defm : JWriteResFpuPair<WriteVecIMul, [JFPU0, JVIMUL], 2>;
defm : JWriteResFpuPair<WritePMULLD, [JFPU0, JFPU01, JVIMUL, JVALU], 4, [2, 1, 2, 1], 3>; defm : JWriteResFpuPair<WritePMULLD, [JFPU0, JFPU01, JVIMUL, JVALU], 4, [2, 1, 2, 1], 3>;
defm : JWriteResFpuPair<WriteMPSAD, [JFPU0, JVIMUL], 3, [1, 2]>; defm : JWriteResFpuPair<WriteMPSAD, [JFPU0, JVIMUL], 3, [1, 2]>;
defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>; defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarShuffle, [JFPU01, JVALU], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>; defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarBlend, [JFPU01, JVALU], 2, [1, 4], 3>; defm : JWriteResFpuPair<WriteVarBlend, [JFPU01, JVALU], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteVecLogic, [JFPU01, JVALU], 1>; defm : JWriteResFpuPair<WriteVecLogic, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteShuffle256, [JFPU01, JVALU], 1>; defm : JWriteResFpuPair<WriteShuffle256, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarShuffle256, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar.
defm : JWriteResFpuPair<WriteVarVecShift, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar. defm : JWriteResFpuPair<WriteVarVecShift, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar.
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Vector Extraction instructions. // Vector Extraction instructions.
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
def JWritePEXTR : SchedWriteRes<[JFPU0, JFPA, JALU0]> { let Latency = 3; } def JWritePEXTR : SchedWriteRes<[JFPU0, JFPA, JALU0]> { let Latency = 3; }
def : InstRW<[JWritePEXTR], (instrs MMX_PEXTRWrr, def : InstRW<[JWritePEXTR], (instrs MMX_PEXTRWrr,
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def JWriteVCVTPDYLd: SchedWriteRes<[JLAGU, JFPU1, JSTC, JFPX]> { def JWriteVCVTPDYLd: SchedWriteRes<[JLAGU, JFPU1, JSTC, JFPX]> {
let Latency = 11; let Latency = 11;
let ResourceCycles = [2, 2, 2, 4]; let ResourceCycles = [2, 2, 2, 4];
let NumMicroOps = 3; let NumMicroOps = 3;
} }
def : InstRW<[JWriteVCVTPDYLd, ReadAfterLd], (instrs VCVTPD2DQYrm, VCVTTPD2DQYrm, VCVTPD2PSYrm)>; def : InstRW<[JWriteVCVTPDYLd, ReadAfterLd], (instrs VCVTPD2DQYrm, VCVTTPD2DQYrm, VCVTPD2PSYrm)>;
def JWritePSHUFB: SchedWriteRes<[JFPU01, JVALU]> {
let Latency = 2;
let ResourceCycles = [1, 4];
let NumMicroOps = 3;
}
def : InstRW<[JWritePSHUFB], (instrs MMX_PSHUFBrr, PSHUFBrr, VPSHUFBrr)>;
def JWritePSHUFBLd: SchedWriteRes<[JLAGU, JFPU01, JVALU]> {
let Latency = 7;
let ResourceCycles = [1, 1, 4];
let NumMicroOps = 3;
}
def : InstRW<[JWritePSHUFBLd, ReadAfterLd], (instrs MMX_PSHUFBrm, PSHUFBrm, VPSHUFBrm)>;
def JWriteVPERM: SchedWriteRes<[JFPU01, JFPX]> {
let Latency = 2;
let ResourceCycles = [1, 4];
let NumMicroOps = 3;
}
def : InstRW<[JWriteVPERM], (instrs VPERMILPDrr, VPERMILPSrr)>;
def JWriteVPERMLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
let Latency = 7;
let ResourceCycles = [1, 1, 4];
let NumMicroOps = 3;
}
def : InstRW<[JWriteVPERMLd, ReadAfterLd], (instrs VPERMILPDrm, VPERMILPSrm)>;
def JWriteVPERMY: SchedWriteRes<[JFPU01, JFPX]> { def JWriteVPERMY: SchedWriteRes<[JFPU01, JFPX]> {
let Latency = 3; let Latency = 3;
let ResourceCycles = [2, 6]; let ResourceCycles = [2, 6];
let NumMicroOps = 6; let NumMicroOps = 6;
} }
def : InstRW<[JWriteVPERMY], (instrs VBLENDVPDYrr, VBLENDVPSYrr, VPERMILPDYrr, VPERMILPSYrr)>; def : InstRW<[JWriteVPERMY], (instrs VBLENDVPDYrr, VBLENDVPSYrr, VPERMILPDYrr, VPERMILPSYrr)>;
def JWriteVPERMYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> { def JWriteVPERMYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86ScheduleSLM.td

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,34]>; defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,34]>;
defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>; defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>;
defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>; defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>;
defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0], 15>; defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0], 15>;
defm : SLMWriteResPair<WriteCvtF2I, [SLM_FPC_RSV01], 4>; defm : SLMWriteResPair<WriteCvtF2I, [SLM_FPC_RSV01], 4>;
defm : SLMWriteResPair<WriteCvtI2F, [SLM_FPC_RSV01], 4>; defm : SLMWriteResPair<WriteCvtI2F, [SLM_FPC_RSV01], 4>;
defm : SLMWriteResPair<WriteCvtF2F, [SLM_FPC_RSV01], 4>; defm : SLMWriteResPair<WriteCvtF2F, [SLM_FPC_RSV01], 4>;
defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;
// Vector integer operations. // Vector integer operations.
def : WriteRes<WriteVecStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>; def : WriteRes<WriteVecStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; } def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; }
def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>; def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>;
defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>; defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>; defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>; defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;
// FIXME: The below is closer to correct, but caused some perf regressions. // FIXME: The below is closer to correct, but caused some perf regressions.
//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>; //defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>;
defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>; defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>;
defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>; defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions. // Horizontal add/sub instructions.
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>; defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>;
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def : WriteRes<WriteNop, []>; def : WriteRes<WriteNop, []>;
// AVX/FMA is not supported on that architecture, but we should define the basic // AVX/FMA is not supported on that architecture, but we should define the basic
// scheduling resources anyway. // scheduling resources anyway.
def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>; def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFShuffle256, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteFShuffle256, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarShuffle256, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteShuffle256, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteShuffle256, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVarShuffle256, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFMA, [SLM_FPC_RSV0], 1>; defm : SLMWriteResPair<WriteFMA, [SLM_FPC_RSV0], 1>;
// Instruction overrides // Instruction overrides
def SLMriteResGroup1 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> { def SLMriteResGroup1 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
let Latency = 69; let Latency = 69;
let NumMicroOps = 1; let NumMicroOps = 1;
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llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

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defm : ZnWriteResFpuPair<WriteFBlend, [ZnFPU01], 1>; defm : ZnWriteResFpuPair<WriteFBlend, [ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteFVarBlend, [ZnFPU01], 1>; defm : ZnWriteResFpuPair<WriteFVarBlend, [ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteVarBlend, [ZnFPU0], 1>; defm : ZnWriteResFpuPair<WriteVarBlend, [ZnFPU0], 1>;
defm : ZnWriteResFpuPair<WriteCvtI2F, [ZnFPU3], 5>; defm : ZnWriteResFpuPair<WriteCvtI2F, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteCvtF2F, [ZnFPU3], 5>; defm : ZnWriteResFpuPair<WriteCvtF2F, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteCvtF2I, [ZnFPU3], 5>; defm : ZnWriteResFpuPair<WriteCvtF2I, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteFDiv, [ZnFPU3], 15>; defm : ZnWriteResFpuPair<WriteFDiv, [ZnFPU3], 15>;
defm : ZnWriteResFpuPair<WriteFShuffle, [ZnFPU12], 1>; defm : ZnWriteResFpuPair<WriteFShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFVarShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU0], 5>; defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU0], 5>;
defm : ZnWriteResFpuPair<WriteFMA, [ZnFPU03], 5>; defm : ZnWriteResFpuPair<WriteFMA, [ZnFPU03], 5>;
defm : ZnWriteResFpuPair<WriteFRcp, [ZnFPU01], 5>; defm : ZnWriteResFpuPair<WriteFRcp, [ZnFPU01], 5>;
defm : ZnWriteResFpuPair<WriteFRsqrt, [ZnFPU01], 5>; defm : ZnWriteResFpuPair<WriteFRsqrt, [ZnFPU01], 5>;
defm : ZnWriteResFpuPair<WriteFSqrt, [ZnFPU3], 20>; defm : ZnWriteResFpuPair<WriteFSqrt, [ZnFPU3], 20>;
// Vector integer operations which uses FPU units // Vector integer operations which uses FPU units
def : WriteRes<WriteVecStore, [ZnAGU]>; def : WriteRes<WriteVecStore, [ZnAGU]>;
def : WriteRes<WriteVecMove, [ZnFPU]>; def : WriteRes<WriteVecMove, [ZnFPU]>;
def : WriteRes<WriteVecLoad, [ZnAGU]> { let Latency = 8; } def : WriteRes<WriteVecLoad, [ZnAGU]> { let Latency = 8; }
defm : ZnWriteResFpuPair<WriteVecShift, [ZnFPU], 1>; defm : ZnWriteResFpuPair<WriteVecShift, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecLogic, [ZnFPU], 1>; defm : ZnWriteResFpuPair<WriteVecLogic, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WritePHAdd, [ZnFPU], 1>; defm : ZnWriteResFpuPair<WritePHAdd, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecALU, [ZnFPU], 1>; defm : ZnWriteResFpuPair<WriteVecALU, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecIMul, [ZnFPU0], 4>; defm : ZnWriteResFpuPair<WriteVecIMul, [ZnFPU0], 4>;
defm : ZnWriteResFpuPair<WritePMULLD, [ZnFPU0], 4>; // FIXME defm : ZnWriteResFpuPair<WritePMULLD, [ZnFPU0], 4>; // FIXME
defm : ZnWriteResFpuPair<WriteShuffle, [ZnFPU], 1>; defm : ZnWriteResFpuPair<WriteShuffle, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVarShuffle, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>; defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>; defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>;
defm : ZnWriteResFpuPair<WriteVarShuffle256, [ZnFPU], 2>;
// Vector Shift Operations // Vector Shift Operations
defm : ZnWriteResFpuPair<WriteVarVecShift, [ZnFPU12], 1>; defm : ZnWriteResFpuPair<WriteVarVecShift, [ZnFPU12], 1>;
// MOVMSK Instructions. // MOVMSK Instructions.
def : WriteRes<WriteFMOVMSK, [ZnFPU2]>; def : WriteRes<WriteFMOVMSK, [ZnFPU2]>;
def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>; def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>;
def : WriteRes<WriteMMXMOVMSK, [ZnFPU2]>; def : WriteRes<WriteMMXMOVMSK, [ZnFPU2]>;
// AES Instructions. // AES Instructions.
defm : ZnWriteResFpuPair<WriteAESDecEnc, [ZnFPU01], 4>; defm : ZnWriteResFpuPair<WriteAESDecEnc, [ZnFPU01], 4>;
defm : ZnWriteResFpuPair<WriteAESIMC, [ZnFPU01], 4>; defm : ZnWriteResFpuPair<WriteAESIMC, [ZnFPU01], 4>;
defm : ZnWriteResFpuPair<WriteAESKeyGen, [ZnFPU01], 4>; defm : ZnWriteResFpuPair<WriteAESKeyGen, [ZnFPU01], 4>;
def : WriteRes<WriteFence, [ZnAGU]>; def : WriteRes<WriteFence, [ZnAGU]>;
def : WriteRes<WriteNop, []>; def : WriteRes<WriteNop, []>;
// Following instructions with latency=100 are microcoded. // Following instructions with latency=100 are microcoded.
// We set long latency so as to block the entire pipeline. // We set long latency so as to block the entire pipeline.
defm : ZnWriteResFpuPair<WriteFShuffle256, [ZnFPU], 100>; defm : ZnWriteResFpuPair<WriteFShuffle256, [ZnFPU], 100>;
defm : ZnWriteResFpuPair<WriteFVarShuffle256, [ZnFPU], 100>;
//Microcoded Instructions //Microcoded Instructions
let Latency = 100 in { let Latency = 100 in {
def : WriteRes<WriteMicrocoded, []>; def : WriteRes<WriteMicrocoded, []>;
def : WriteRes<WriteSystem, []>; def : WriteRes<WriteSystem, []>;
def : WriteRes<WriteMPSAD, []>; def : WriteRes<WriteMPSAD, []>;
def : WriteRes<WriteMPSADLd, []>; def : WriteRes<WriteMPSADLd, []>;
def : WriteRes<WriteCLMul, []>; def : WriteRes<WriteCLMul, []>;
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llvm/trunk/test/CodeGen/X86/avx2-schedule.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,125 Lines • ▼ Show 20 Lines; ZNVER1-NEXT: retq # sched: [1:0.50]
%4 = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %2, <32 x i8> %3) %4 = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %2, <32 x i8> %3)
ret <4 x i64> %4 ret <4 x i64> %4
} }
declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone
define <32 x i8> @test_pshufb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> *%a2) { define <32 x i8> @test_pshufb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> *%a2) {
; GENERIC-LABEL: test_pshufb: ; GENERIC-LABEL: test_pshufb:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:1.00] ; GENERIC-NEXT: vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
; GENERIC-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [6:1.00] ; GENERIC-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pshufb: ; HASWELL-LABEL: test_pshufb:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:1.00] ; HASWELL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
; HASWELL-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [8:1.00] ; HASWELL-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00] ; HASWELL-NEXT: retq # sched: [7:1.00]
; ;
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llvm/trunk/test/CodeGen/X86/avx512-schedule.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,583 Lines • ▼ Show 20 Lines
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%ret = select <32 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <32 x i16> %x, <32 x i16> zeroinitializer %ret = select <32 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <32 x i16> %x, <32 x i16> zeroinitializer
ret <32 x i16> %ret ret <32 x i16> %ret
} }
define <64 x i8> @test_build_vec_v64i1(<64 x i8> %x) { define <64 x i8> @test_build_vec_v64i1(<64 x i8> %x) {
; GENERIC-LABEL: test_build_vec_v64i1: ; GENERIC-LABEL: test_build_vec_v64i1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zero,zero,zmm0[2],zero,zero,zero,zmm0[6],zero,zmm0[8],zero,zmm0[10],zero,zmm0[12],zero,zero,zmm0[15],zero,zero,zmm0[18],zero,zmm0[20],zero,zmm0[22],zero,zmm0[24],zero,zero,zmm0[27],zero,zero,zmm0[30],zero,zmm0[32],zero,zmm0[34],zero,zero,zero,zmm0[38],zero,zmm0[40],zero,zero,zmm0[43,44],zero,zmm0[46],zero,zmm0[48],zero,zmm0[50],zero,zero,zero,zmm0[54],zero,zmm0[56],zero,zero,zmm0[59,60],zero,zmm0[62],zero sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zero,zero,zmm0[2],zero,zero,zero,zmm0[6],zero,zmm0[8],zero,zmm0[10],zero,zmm0[12],zero,zero,zmm0[15],zero,zero,zmm0[18],zero,zmm0[20],zero,zmm0[22],zero,zmm0[24],zero,zero,zmm0[27],zero,zero,zmm0[30],zero,zmm0[32],zero,zmm0[34],zero,zero,zero,zmm0[38],zero,zmm0[40],zero,zero,zmm0[43,44],zero,zmm0[46],zero,zmm0[48],zero,zmm0[50],zero,zero,zero,zmm0[54],zero,zmm0[56],zero,zero,zmm0[59,60],zero,zmm0[62],zero sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_build_vec_v64i1: ; SKX-LABEL: test_build_vec_v64i1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zero,zero,zmm0[2],zero,zero,zero,zmm0[6],zero,zmm0[8],zero,zmm0[10],zero,zmm0[12],zero,zero,zmm0[15],zero,zero,zmm0[18],zero,zmm0[20],zero,zmm0[22],zero,zmm0[24],zero,zero,zmm0[27],zero,zero,zmm0[30],zero,zmm0[32],zero,zmm0[34],zero,zero,zero,zmm0[38],zero,zmm0[40],zero,zero,zmm0[43,44],zero,zmm0[46],zero,zmm0[48],zero,zmm0[50],zero,zero,zero,zmm0[54],zero,zmm0[56],zero,zero,zmm0[59,60],zero,zmm0[62],zero sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zero,zero,zmm0[2],zero,zero,zero,zmm0[6],zero,zmm0[8],zero,zmm0[10],zero,zmm0[12],zero,zero,zmm0[15],zero,zero,zmm0[18],zero,zmm0[20],zero,zmm0[22],zero,zmm0[24],zero,zero,zmm0[27],zero,zero,zmm0[30],zero,zmm0[32],zero,zmm0[34],zero,zero,zero,zmm0[38],zero,zmm0[40],zero,zero,zmm0[43,44],zero,zmm0[46],zero,zmm0[48],zero,zmm0[50],zero,zero,zero,zmm0[54],zero,zmm0[56],zero,zero,zmm0[59,60],zero,zmm0[62],zero sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%ret = select <64 x i1> <i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <64 x i8> %x, <64 x i8> zeroinitializer %ret = select <64 x i1> <i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false>, <64 x i8> %x, <64 x i8> zeroinitializer
ret <64 x i8> %ret ret <64 x i8> %ret
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llvm/trunk/test/CodeGen/X86/avx512-shuffle-schedule.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,529 Lines • ▼ Show 20 Lines
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 8, i32 6, i32 12, i32 4, i32 7, i32 9, i32 14, i32 8, i32 4, i32 12, i32 9, i32 4, i32 14, i32 15, i32 12, i32 14> %res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 8, i32 6, i32 12, i32 4, i32 7, i32 9, i32 14, i32 8, i32 4, i32 12, i32 9, i32 4, i32 14, i32 15, i32 12, i32 14>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mask0(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mask0(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mask0: ; GENERIC-LABEL: test_masked_16xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mask0: ; SKX-LABEL: test_masked_16xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [7:1.00]
; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 8, i32 6, i32 12, i32 4, i32 7, i32 9, i32 14, i32 8, i32 4, i32 12, i32 9, i32 4, i32 14, i32 15, i32 12, i32 14> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 8, i32 6, i32 12, i32 4, i32 7, i32 9, i32 14, i32 8, i32 4, i32 12, i32 9, i32 4, i32 14, i32 15, i32 12, i32 14>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mask0(<16 x i8> %vec, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mask0(<16 x i8> %vec, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mask0: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mask0: ; SKX-LABEL: test_masked_z_16xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[8,6,12,4,7,9,14,8,4,12,9,4,14,15,12,14] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 8, i32 6, i32 12, i32 4, i32 7, i32 9, i32 14, i32 8, i32 4, i32 12, i32 9, i32 4, i32 14, i32 15, i32 12, i32 14> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 8, i32 6, i32 12, i32 4, i32 7, i32 9, i32 14, i32 8, i32 4, i32 12, i32 9, i32 4, i32 14, i32 15, i32 12, i32 14>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mask1(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mask1(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mask1: ; GENERIC-LABEL: test_masked_16xi8_perm_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mask1: ; SKX-LABEL: test_masked_16xi8_perm_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [7:1.00]
; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 4, i32 11, i32 14, i32 10, i32 7, i32 1, i32 6, i32 9, i32 14, i32 15, i32 7, i32 13, i32 4, i32 12, i32 8, i32 0> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 4, i32 11, i32 14, i32 10, i32 7, i32 1, i32 6, i32 9, i32 14, i32 15, i32 7, i32 13, i32 4, i32 12, i32 8, i32 0>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mask1(<16 x i8> %vec, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mask1(<16 x i8> %vec, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mask1: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mask1: ; SKX-LABEL: test_masked_z_16xi8_perm_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[4,11,14,10,7,1,6,9,14,15,7,13,4,12,8,0] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 4, i32 11, i32 14, i32 10, i32 7, i32 1, i32 6, i32 9, i32 14, i32 15, i32 7, i32 13, i32 4, i32 12, i32 8, i32 0> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 4, i32 11, i32 14, i32 10, i32 7, i32 1, i32 6, i32 9, i32 14, i32 15, i32 7, i32 13, i32 4, i32 12, i32 8, i32 0>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mask2(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mask2(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mask2: ; GENERIC-LABEL: test_masked_16xi8_perm_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mask2: ; SKX-LABEL: test_masked_16xi8_perm_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [7:1.00]
; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 11, i32 6, i32 13, i32 10, i32 0, i32 7, i32 13, i32 3, i32 5, i32 13, i32 3, i32 9, i32 3, i32 15, i32 12, i32 7> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 11, i32 6, i32 13, i32 10, i32 0, i32 7, i32 13, i32 3, i32 5, i32 13, i32 3, i32 9, i32 3, i32 15, i32 12, i32 7>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mask2(<16 x i8> %vec, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mask2(<16 x i8> %vec, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mask2: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mask2: ; SKX-LABEL: test_masked_z_16xi8_perm_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[11,6,13,10,0,7,13,3,5,13,3,9,3,15,12,7] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 11, i32 6, i32 13, i32 10, i32 0, i32 7, i32 13, i32 3, i32 5, i32 13, i32 3, i32 9, i32 3, i32 15, i32 12, i32 7> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 11, i32 6, i32 13, i32 10, i32 0, i32 7, i32 13, i32 3, i32 5, i32 13, i32 3, i32 9, i32 3, i32 15, i32 12, i32 7>
Show All 13 Lines
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 5, i32 8, i32 14, i32 1, i32 8, i32 11, i32 8, i32 13, i32 8, i32 15, i32 9, i32 9, i32 7, i32 9, i32 6> %res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 5, i32 8, i32 14, i32 1, i32 8, i32 11, i32 8, i32 13, i32 8, i32 15, i32 9, i32 9, i32 7, i32 9, i32 6>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mask3(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mask3(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mask3: ; GENERIC-LABEL: test_masked_16xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mask3: ; SKX-LABEL: test_masked_16xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm2, %xmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm1 {%k1} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [7:1.00]
; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %xmm1, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 5, i32 8, i32 14, i32 1, i32 8, i32 11, i32 8, i32 13, i32 8, i32 15, i32 9, i32 9, i32 7, i32 9, i32 6> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 5, i32 8, i32 14, i32 1, i32 8, i32 11, i32 8, i32 13, i32 8, i32 15, i32 9, i32 9, i32 7, i32 9, i32 6>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mask3(<16 x i8> %vec, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mask3(<16 x i8> %vec, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mask3: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mask3: ; SKX-LABEL: test_masked_z_16xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm0[1,5,8,14,1,8,11,8,13,8,15,9,9,7,9,6] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 5, i32 8, i32 14, i32 1, i32 8, i32 11, i32 8, i32 13, i32 8, i32 15, i32 9, i32 9, i32 7, i32 9, i32 6> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 5, i32 8, i32 14, i32 1, i32 8, i32 11, i32 8, i32 13, i32 8, i32 15, i32 9, i32 9, i32 7, i32 9, i32 6>
Show All 17 Lines; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 10, i32 7, i32 1, i32 12, i32 14, i32 14, i32 13, i32 14, i32 14, i32 8, i32 6, i32 11, i32 4, i32 12, i32 13> %res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 10, i32 7, i32 1, i32 12, i32 14, i32 14, i32 13, i32 14, i32 14, i32 8, i32 6, i32 11, i32 4, i32 12, i32 13>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mem_mask0(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mem_mask0(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask0: ; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mem_mask0: ; SKX-LABEL: test_masked_16xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 10, i32 7, i32 1, i32 12, i32 14, i32 14, i32 13, i32 14, i32 14, i32 8, i32 6, i32 11, i32 4, i32 12, i32 13> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 10, i32 7, i32 1, i32 12, i32 14, i32 14, i32 13, i32 14, i32 14, i32 8, i32 6, i32 11, i32 4, i32 12, i32 13>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mem_mask0(<16 x i8>* %vp, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mem_mask0(<16 x i8>* %vp, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask0: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask0: ; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,10,7,1,12,14,14,13,14,14,8,6,11,4,12,13] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 10, i32 7, i32 1, i32 12, i32 14, i32 14, i32 13, i32 14, i32 14, i32 8, i32 6, i32 11, i32 4, i32 12, i32 13> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 10, i32 7, i32 1, i32 12, i32 14, i32 14, i32 13, i32 14, i32 14, i32 8, i32 6, i32 11, i32 4, i32 12, i32 13>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mem_mask1(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mem_mask1(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask1: ; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mem_mask1: ; SKX-LABEL: test_masked_16xi8_perm_mem_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 14, i32 9, i32 15, i32 9, i32 7, i32 10, i32 15, i32 14, i32 12, i32 1, i32 9, i32 7, i32 10, i32 13, i32 3, i32 11> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 14, i32 9, i32 15, i32 9, i32 7, i32 10, i32 15, i32 14, i32 12, i32 1, i32 9, i32 7, i32 10, i32 13, i32 3, i32 11>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mem_mask1(<16 x i8>* %vp, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mem_mask1(<16 x i8>* %vp, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask1: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask1: ; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[14,9,15,9,7,10,15,14,12,1,9,7,10,13,3,11] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 14, i32 9, i32 15, i32 9, i32 7, i32 10, i32 15, i32 14, i32 12, i32 1, i32 9, i32 7, i32 10, i32 13, i32 3, i32 11> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 14, i32 9, i32 15, i32 9, i32 7, i32 10, i32 15, i32 14, i32 12, i32 1, i32 9, i32 7, i32 10, i32 13, i32 3, i32 11>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mem_mask2(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mem_mask2(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask2: ; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mem_mask2: ; SKX-LABEL: test_masked_16xi8_perm_mem_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 3, i32 12, i32 5, i32 13, i32 1, i32 2, i32 11, i32 0, i32 9, i32 14, i32 8, i32 10, i32 0, i32 10, i32 9> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 1, i32 3, i32 12, i32 5, i32 13, i32 1, i32 2, i32 11, i32 0, i32 9, i32 14, i32 8, i32 10, i32 0, i32 10, i32 9>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mem_mask2(<16 x i8>* %vp, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mem_mask2(<16 x i8>* %vp, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask2: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask2: ; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[1,3,12,5,13,1,2,11,0,9,14,8,10,0,10,9] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
Show All 20 Lines; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 6, i32 5, i32 15, i32 0, i32 0, i32 15, i32 2, i32 1, i32 3, i32 12, i32 14, i32 0, i32 6, i32 1, i32 4> %res = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 6, i32 5, i32 15, i32 0, i32 0, i32 15, i32 2, i32 1, i32 3, i32 12, i32 14, i32 0, i32 6, i32 1, i32 4>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_16xi8_perm_mem_mask3(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) { define <16 x i8> @test_masked_16xi8_perm_mem_mask3(<16 x i8>* %vp, <16 x i8> %vec2, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask3: ; GENERIC-LABEL: test_masked_16xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_16xi8_perm_mem_mask3: ; SKX-LABEL: test_masked_16xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm2 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm1, %xmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} = xmm2[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 6, i32 5, i32 15, i32 0, i32 0, i32 15, i32 2, i32 1, i32 3, i32 12, i32 14, i32 0, i32 6, i32 1, i32 4> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 6, i32 5, i32 15, i32 0, i32 0, i32 15, i32 2, i32 1, i32 3, i32 12, i32 14, i32 0, i32 6, i32 1, i32 4>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i8> @test_masked_z_16xi8_perm_mem_mask3(<16 x i8>* %vp, <16 x i8> %mask) { define <16 x i8> @test_masked_z_16xi8_perm_mem_mask3(<16 x i8>* %vp, <16 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask3: ; GENERIC-LABEL: test_masked_z_16xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask3: ; SKX-LABEL: test_masked_z_16xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50] ; SKX-NEXT: vmovdqa (%rdi), %xmm1 # sched: [6:0.50]
; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %xmm0, %xmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [7:1.00] ; SKX-NEXT: vpshufb {{.*#+}} xmm0 {%k1} {z} = xmm1[9,6,5,15,0,0,15,2,1,3,12,14,0,6,1,4] sched: [7:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <16 x i8>, <16 x i8>* %vp %vec = load <16 x i8>, <16 x i8>* %vp
%shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 6, i32 5, i32 15, i32 0, i32 0, i32 15, i32 2, i32 1, i32 3, i32 12, i32 14, i32 0, i32 6, i32 1, i32 4> %shuf = shufflevector <16 x i8> %vec, <16 x i8> undef, <16 x i32> <i32 9, i32 6, i32 5, i32 15, i32 0, i32 0, i32 15, i32 2, i32 1, i32 3, i32 12, i32 14, i32 0, i32 6, i32 1, i32 4>
%cmp = icmp eq <16 x i8> %mask, zeroinitializer %cmp = icmp eq <16 x i8> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> zeroinitializer
ret <16 x i8> %res ret <16 x i8> %res
} }
define <32 x i8> @test_32xi8_perm_mask0(<32 x i8> %vec) { define <32 x i8> @test_32xi8_perm_mask0(<32 x i8> %vec) {
; GENERIC-LABEL: test_32xi8_perm_mask0: ; GENERIC-LABEL: test_32xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_32xi8_perm_mask0: ; SKX-LABEL: test_32xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 8, i32 0, i32 1, i32 15, i32 3, i32 5, i32 11, i32 13, i32 14, i32 2, i32 10, i32 15, i32 0, i32 10, i32 13, i32 5, i32 20, i32 25, i32 23, i32 18, i32 23, i32 22, i32 25, i32 24, i32 20, i32 21, i32 29, i32 20, i32 24, i32 16, i32 27, i32 21> %res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 8, i32 0, i32 1, i32 15, i32 3, i32 5, i32 11, i32 13, i32 14, i32 2, i32 10, i32 15, i32 0, i32 10, i32 13, i32 5, i32 20, i32 25, i32 23, i32 18, i32 23, i32 22, i32 25, i32 24, i32 20, i32 21, i32 29, i32 20, i32 24, i32 16, i32 27, i32 21>
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mask0(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mask0(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mask0: ; GENERIC-LABEL: test_masked_32xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mask0: ; SKX-LABEL: test_masked_32xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [8:1.00]
; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 8, i32 0, i32 1, i32 15, i32 3, i32 5, i32 11, i32 13, i32 14, i32 2, i32 10, i32 15, i32 0, i32 10, i32 13, i32 5, i32 20, i32 25, i32 23, i32 18, i32 23, i32 22, i32 25, i32 24, i32 20, i32 21, i32 29, i32 20, i32 24, i32 16, i32 27, i32 21> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 8, i32 0, i32 1, i32 15, i32 3, i32 5, i32 11, i32 13, i32 14, i32 2, i32 10, i32 15, i32 0, i32 10, i32 13, i32 5, i32 20, i32 25, i32 23, i32 18, i32 23, i32 22, i32 25, i32 24, i32 20, i32 21, i32 29, i32 20, i32 24, i32 16, i32 27, i32 21>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mask0(<32 x i8> %vec, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mask0(<32 x i8> %vec, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mask0: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mask0: ; SKX-LABEL: test_masked_z_32xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[8,0,1,15,3,5,11,13,14,2,10,15,0,10,13,5,20,25,23,18,23,22,25,24,20,21,29,20,24,16,27,21] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 8, i32 0, i32 1, i32 15, i32 3, i32 5, i32 11, i32 13, i32 14, i32 2, i32 10, i32 15, i32 0, i32 10, i32 13, i32 5, i32 20, i32 25, i32 23, i32 18, i32 23, i32 22, i32 25, i32 24, i32 20, i32 21, i32 29, i32 20, i32 24, i32 16, i32 27, i32 21> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 8, i32 0, i32 1, i32 15, i32 3, i32 5, i32 11, i32 13, i32 14, i32 2, i32 10, i32 15, i32 0, i32 10, i32 13, i32 5, i32 20, i32 25, i32 23, i32 18, i32 23, i32 22, i32 25, i32 24, i32 20, i32 21, i32 29, i32 20, i32 24, i32 16, i32 27, i32 21>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mask1(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mask1(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mask1: ; GENERIC-LABEL: test_masked_32xi8_perm_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mask1: ; SKX-LABEL: test_masked_32xi8_perm_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [8:1.00]
; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 0, i32 4, i32 3, i32 15, i32 5, i32 4, i32 5, i32 15, i32 10, i32 9, i32 11, i32 6, i32 6, i32 10, i32 0, i32 3, i32 21, i32 19, i32 26, i32 22, i32 30, i32 25, i32 22, i32 22, i32 27, i32 22, i32 26, i32 16, i32 23, i32 20, i32 18, i32 24> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 0, i32 4, i32 3, i32 15, i32 5, i32 4, i32 5, i32 15, i32 10, i32 9, i32 11, i32 6, i32 6, i32 10, i32 0, i32 3, i32 21, i32 19, i32 26, i32 22, i32 30, i32 25, i32 22, i32 22, i32 27, i32 22, i32 26, i32 16, i32 23, i32 20, i32 18, i32 24>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mask1(<32 x i8> %vec, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mask1(<32 x i8> %vec, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mask1: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mask1: ; SKX-LABEL: test_masked_z_32xi8_perm_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[0,4,3,15,5,4,5,15,10,9,11,6,6,10,0,3,21,19,26,22,30,25,22,22,27,22,26,16,23,20,18,24] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 0, i32 4, i32 3, i32 15, i32 5, i32 4, i32 5, i32 15, i32 10, i32 9, i32 11, i32 6, i32 6, i32 10, i32 0, i32 3, i32 21, i32 19, i32 26, i32 22, i32 30, i32 25, i32 22, i32 22, i32 27, i32 22, i32 26, i32 16, i32 23, i32 20, i32 18, i32 24> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 0, i32 4, i32 3, i32 15, i32 5, i32 4, i32 5, i32 15, i32 10, i32 9, i32 11, i32 6, i32 6, i32 10, i32 0, i32 3, i32 21, i32 19, i32 26, i32 22, i32 30, i32 25, i32 22, i32 22, i32 27, i32 22, i32 26, i32 16, i32 23, i32 20, i32 18, i32 24>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mask2(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mask2(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mask2: ; GENERIC-LABEL: test_masked_32xi8_perm_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mask2: ; SKX-LABEL: test_masked_32xi8_perm_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [8:1.00]
; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 7, i32 8, i32 12, i32 14, i32 7, i32 4, i32 7, i32 12, i32 14, i32 12, i32 3, i32 15, i32 10, i32 1, i32 11, i32 15, i32 22, i32 26, i32 21, i32 19, i32 27, i32 16, i32 29, i32 24, i32 17, i32 17, i32 26, i32 29, i32 20, i32 31, i32 17, i32 29> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 7, i32 8, i32 12, i32 14, i32 7, i32 4, i32 7, i32 12, i32 14, i32 12, i32 3, i32 15, i32 10, i32 1, i32 11, i32 15, i32 22, i32 26, i32 21, i32 19, i32 27, i32 16, i32 29, i32 24, i32 17, i32 17, i32 26, i32 29, i32 20, i32 31, i32 17, i32 29>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mask2(<32 x i8> %vec, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mask2(<32 x i8> %vec, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mask2: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mask2: ; SKX-LABEL: test_masked_z_32xi8_perm_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[7,8,12,14,7,4,7,12,14,12,3,15,10,1,11,15,22,26,21,19,27,16,29,24,17,17,26,29,20,31,17,29] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 7, i32 8, i32 12, i32 14, i32 7, i32 4, i32 7, i32 12, i32 14, i32 12, i32 3, i32 15, i32 10, i32 1, i32 11, i32 15, i32 22, i32 26, i32 21, i32 19, i32 27, i32 16, i32 29, i32 24, i32 17, i32 17, i32 26, i32 29, i32 20, i32 31, i32 17, i32 29> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 7, i32 8, i32 12, i32 14, i32 7, i32 4, i32 7, i32 12, i32 14, i32 12, i32 3, i32 15, i32 10, i32 1, i32 11, i32 15, i32 22, i32 26, i32 21, i32 19, i32 27, i32 16, i32 29, i32 24, i32 17, i32 17, i32 26, i32 29, i32 20, i32 31, i32 17, i32 29>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_32xi8_perm_mask3(<32 x i8> %vec) { define <32 x i8> @test_32xi8_perm_mask3(<32 x i8> %vec) {
; GENERIC-LABEL: test_32xi8_perm_mask3: ; GENERIC-LABEL: test_32xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_32xi8_perm_mask3: ; SKX-LABEL: test_32xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 6, i32 1, i32 4, i32 7, i32 12, i32 13, i32 2, i32 8, i32 10, i32 5, i32 13, i32 4, i32 0, i32 0, i32 10, i32 8, i32 31, i32 31, i32 30, i32 16, i32 27, i32 27, i32 26, i32 27, i32 30, i32 26, i32 21, i32 24, i32 19, i32 25, i32 16, i32 18> %res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 6, i32 1, i32 4, i32 7, i32 12, i32 13, i32 2, i32 8, i32 10, i32 5, i32 13, i32 4, i32 0, i32 0, i32 10, i32 8, i32 31, i32 31, i32 30, i32 16, i32 27, i32 27, i32 26, i32 27, i32 30, i32 26, i32 21, i32 24, i32 19, i32 25, i32 16, i32 18>
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mask3(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mask3(<32 x i8> %vec, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mask3: ; GENERIC-LABEL: test_masked_32xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mask3: ; SKX-LABEL: test_masked_32xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm2, %ymm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm1 {%k1} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [8:1.00]
; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa %ymm1, %ymm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 6, i32 1, i32 4, i32 7, i32 12, i32 13, i32 2, i32 8, i32 10, i32 5, i32 13, i32 4, i32 0, i32 0, i32 10, i32 8, i32 31, i32 31, i32 30, i32 16, i32 27, i32 27, i32 26, i32 27, i32 30, i32 26, i32 21, i32 24, i32 19, i32 25, i32 16, i32 18> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 6, i32 1, i32 4, i32 7, i32 12, i32 13, i32 2, i32 8, i32 10, i32 5, i32 13, i32 4, i32 0, i32 0, i32 10, i32 8, i32 31, i32 31, i32 30, i32 16, i32 27, i32 27, i32 26, i32 27, i32 30, i32 26, i32 21, i32 24, i32 19, i32 25, i32 16, i32 18>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mask3(<32 x i8> %vec, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mask3(<32 x i8> %vec, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mask3: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mask3: ; SKX-LABEL: test_masked_z_32xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm0[6,1,4,7,12,13,2,8,10,5,13,4,0,0,10,8,31,31,30,16,27,27,26,27,30,26,21,24,19,25,16,18] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 6, i32 1, i32 4, i32 7, i32 12, i32 13, i32 2, i32 8, i32 10, i32 5, i32 13, i32 4, i32 0, i32 0, i32 10, i32 8, i32 31, i32 31, i32 30, i32 16, i32 27, i32 27, i32 26, i32 27, i32 30, i32 26, i32 21, i32 24, i32 19, i32 25, i32 16, i32 18> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 6, i32 1, i32 4, i32 7, i32 12, i32 13, i32 2, i32 8, i32 10, i32 5, i32 13, i32 4, i32 0, i32 0, i32 10, i32 8, i32 31, i32 31, i32 30, i32 16, i32 27, i32 27, i32 26, i32 27, i32 30, i32 26, i32 21, i32 24, i32 19, i32 25, i32 16, i32 18>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_32xi8_perm_mem_mask0(<32 x i8>* %vp) { define <32 x i8> @test_32xi8_perm_mem_mask0(<32 x i8>* %vp) {
; GENERIC-LABEL: test_32xi8_perm_mem_mask0: ; GENERIC-LABEL: test_32xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_32xi8_perm_mem_mask0: ; SKX-LABEL: test_32xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 9, i32 0, i32 2, i32 15, i32 4, i32 6, i32 8, i32 4, i32 7, i32 3, i32 0, i32 2, i32 8, i32 1, i32 6, i32 5, i32 22, i32 17, i32 30, i32 23, i32 29, i32 31, i32 21, i32 23, i32 27, i32 22, i32 20, i32 27, i32 30, i32 30, i32 26, i32 22> %res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 9, i32 0, i32 2, i32 15, i32 4, i32 6, i32 8, i32 4, i32 7, i32 3, i32 0, i32 2, i32 8, i32 1, i32 6, i32 5, i32 22, i32 17, i32 30, i32 23, i32 29, i32 31, i32 21, i32 23, i32 27, i32 22, i32 20, i32 27, i32 30, i32 30, i32 26, i32 22>
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mem_mask0(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mem_mask0(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask0: ; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mem_mask0: ; SKX-LABEL: test_masked_32xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 9, i32 0, i32 2, i32 15, i32 4, i32 6, i32 8, i32 4, i32 7, i32 3, i32 0, i32 2, i32 8, i32 1, i32 6, i32 5, i32 22, i32 17, i32 30, i32 23, i32 29, i32 31, i32 21, i32 23, i32 27, i32 22, i32 20, i32 27, i32 30, i32 30, i32 26, i32 22> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 9, i32 0, i32 2, i32 15, i32 4, i32 6, i32 8, i32 4, i32 7, i32 3, i32 0, i32 2, i32 8, i32 1, i32 6, i32 5, i32 22, i32 17, i32 30, i32 23, i32 29, i32 31, i32 21, i32 23, i32 27, i32 22, i32 20, i32 27, i32 30, i32 30, i32 26, i32 22>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mem_mask0(<32 x i8>* %vp, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mem_mask0(<32 x i8>* %vp, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask0: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask0: ; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[9,0,2,15,4,6,8,4,7,3,0,2,8,1,6,5,22,17,30,23,29,31,21,23,27,22,20,27,30,30,26,22] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 9, i32 0, i32 2, i32 15, i32 4, i32 6, i32 8, i32 4, i32 7, i32 3, i32 0, i32 2, i32 8, i32 1, i32 6, i32 5, i32 22, i32 17, i32 30, i32 23, i32 29, i32 31, i32 21, i32 23, i32 27, i32 22, i32 20, i32 27, i32 30, i32 30, i32 26, i32 22> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 9, i32 0, i32 2, i32 15, i32 4, i32 6, i32 8, i32 4, i32 7, i32 3, i32 0, i32 2, i32 8, i32 1, i32 6, i32 5, i32 22, i32 17, i32 30, i32 23, i32 29, i32 31, i32 21, i32 23, i32 27, i32 22, i32 20, i32 27, i32 30, i32 30, i32 26, i32 22>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mem_mask1(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mem_mask1(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask1: ; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mem_mask1: ; SKX-LABEL: test_masked_32xi8_perm_mem_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 15, i32 10, i32 1, i32 1, i32 11, i32 0, i32 0, i32 6, i32 8, i32 7, i32 7, i32 9, i32 10, i32 6, i32 5, i32 15, i32 20, i32 28, i32 22, i32 21, i32 17, i32 29, i32 27, i32 30, i32 23, i32 26, i32 17, i32 22, i32 19, i32 16, i32 31, i32 19> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 15, i32 10, i32 1, i32 1, i32 11, i32 0, i32 0, i32 6, i32 8, i32 7, i32 7, i32 9, i32 10, i32 6, i32 5, i32 15, i32 20, i32 28, i32 22, i32 21, i32 17, i32 29, i32 27, i32 30, i32 23, i32 26, i32 17, i32 22, i32 19, i32 16, i32 31, i32 19>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mem_mask1(<32 x i8>* %vp, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mem_mask1(<32 x i8>* %vp, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask1: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask1: ; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[15,10,1,1,11,0,0,6,8,7,7,9,10,6,5,15,20,28,22,21,17,29,27,30,23,26,17,22,19,16,31,19] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 15, i32 10, i32 1, i32 1, i32 11, i32 0, i32 0, i32 6, i32 8, i32 7, i32 7, i32 9, i32 10, i32 6, i32 5, i32 15, i32 20, i32 28, i32 22, i32 21, i32 17, i32 29, i32 27, i32 30, i32 23, i32 26, i32 17, i32 22, i32 19, i32 16, i32 31, i32 19> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 15, i32 10, i32 1, i32 1, i32 11, i32 0, i32 0, i32 6, i32 8, i32 7, i32 7, i32 9, i32 10, i32 6, i32 5, i32 15, i32 20, i32 28, i32 22, i32 21, i32 17, i32 29, i32 27, i32 30, i32 23, i32 26, i32 17, i32 22, i32 19, i32 16, i32 31, i32 19>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mem_mask2(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mem_mask2(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask2: ; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mem_mask2: ; SKX-LABEL: test_masked_32xi8_perm_mem_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 2, i32 3, i32 6, i32 8, i32 2, i32 15, i32 15, i32 2, i32 6, i32 10, i32 14, i32 7, i32 14, i32 5, i32 7, i32 7, i32 26, i32 19, i32 25, i32 19, i32 21, i32 31, i32 30, i32 29, i32 16, i32 18, i32 20, i32 28, i32 29, i32 25, i32 27, i32 28> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 2, i32 3, i32 6, i32 8, i32 2, i32 15, i32 15, i32 2, i32 6, i32 10, i32 14, i32 7, i32 14, i32 5, i32 7, i32 7, i32 26, i32 19, i32 25, i32 19, i32 21, i32 31, i32 30, i32 29, i32 16, i32 18, i32 20, i32 28, i32 29, i32 25, i32 27, i32 28>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mem_mask2(<32 x i8>* %vp, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mem_mask2(<32 x i8>* %vp, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask2: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask2: ; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[2,3,6,8,2,15,15,2,6,10,14,7,14,5,7,7,26,19,25,19,21,31,30,29,16,18,20,28,29,25,27,28] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 2, i32 3, i32 6, i32 8, i32 2, i32 15, i32 15, i32 2, i32 6, i32 10, i32 14, i32 7, i32 14, i32 5, i32 7, i32 7, i32 26, i32 19, i32 25, i32 19, i32 21, i32 31, i32 30, i32 29, i32 16, i32 18, i32 20, i32 28, i32 29, i32 25, i32 27, i32 28> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 2, i32 3, i32 6, i32 8, i32 2, i32 15, i32 15, i32 2, i32 6, i32 10, i32 14, i32 7, i32 14, i32 5, i32 7, i32 7, i32 26, i32 19, i32 25, i32 19, i32 21, i32 31, i32 30, i32 29, i32 16, i32 18, i32 20, i32 28, i32 29, i32 25, i32 27, i32 28>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_32xi8_perm_mem_mask3(<32 x i8>* %vp) { define <32 x i8> @test_32xi8_perm_mem_mask3(<32 x i8>* %vp) {
; GENERIC-LABEL: test_32xi8_perm_mem_mask3: ; GENERIC-LABEL: test_32xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_32xi8_perm_mem_mask3: ; SKX-LABEL: test_32xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm0 # sched: [7:0.50]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 13, i32 0, i32 3, i32 0, i32 0, i32 13, i32 5, i32 2, i32 2, i32 10, i32 15, i32 8, i32 14, i32 8, i32 25, i32 26, i32 28, i32 28, i32 31, i32 27, i32 30, i32 19, i32 24, i32 25, i32 29, i32 23, i32 28, i32 22, i32 25, i32 29> %res = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 13, i32 0, i32 3, i32 0, i32 0, i32 13, i32 5, i32 2, i32 2, i32 10, i32 15, i32 8, i32 14, i32 8, i32 25, i32 26, i32 28, i32 28, i32 31, i32 27, i32 30, i32 19, i32 24, i32 25, i32 29, i32 23, i32 28, i32 22, i32 25, i32 29>
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_32xi8_perm_mem_mask3(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) { define <32 x i8> @test_masked_32xi8_perm_mem_mask3(<32 x i8>* %vp, <32 x i8> %vec2, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask3: ; GENERIC-LABEL: test_masked_32xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_32xi8_perm_mem_mask3: ; SKX-LABEL: test_masked_32xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm2 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm1, %ymm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} = ymm2[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 13, i32 0, i32 3, i32 0, i32 0, i32 13, i32 5, i32 2, i32 2, i32 10, i32 15, i32 8, i32 14, i32 8, i32 25, i32 26, i32 28, i32 28, i32 31, i32 27, i32 30, i32 19, i32 24, i32 25, i32 29, i32 23, i32 28, i32 22, i32 25, i32 29> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 13, i32 0, i32 3, i32 0, i32 0, i32 13, i32 5, i32 2, i32 2, i32 10, i32 15, i32 8, i32 14, i32 8, i32 25, i32 26, i32 28, i32 28, i32 31, i32 27, i32 30, i32 19, i32 24, i32 25, i32 29, i32 23, i32 28, i32 22, i32 25, i32 29>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2 %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> %vec2
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_masked_z_32xi8_perm_mem_mask3(<32 x i8>* %vp, <32 x i8> %mask) { define <32 x i8> @test_masked_z_32xi8_perm_mem_mask3(<32 x i8>* %vp, <32 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask3: ; GENERIC-LABEL: test_masked_z_32xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; GENERIC-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask3: ; SKX-LABEL: test_masked_z_32xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50] ; SKX-NEXT: vmovdqa (%rdi), %ymm1 # sched: [7:0.50]
; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %ymm0, %ymm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} ymm0 {%k1} {z} = ymm1[1,1,13,0,3,0,0,13,5,2,2,10,15,8,14,8,25,26,28,28,31,27,30,19,24,25,29,23,28,22,25,29] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <32 x i8>, <32 x i8>* %vp %vec = load <32 x i8>, <32 x i8>* %vp
%shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 13, i32 0, i32 3, i32 0, i32 0, i32 13, i32 5, i32 2, i32 2, i32 10, i32 15, i32 8, i32 14, i32 8, i32 25, i32 26, i32 28, i32 28, i32 31, i32 27, i32 30, i32 19, i32 24, i32 25, i32 29, i32 23, i32 28, i32 22, i32 25, i32 29> %shuf = shufflevector <32 x i8> %vec, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 13, i32 0, i32 3, i32 0, i32 0, i32 13, i32 5, i32 2, i32 2, i32 10, i32 15, i32 8, i32 14, i32 8, i32 25, i32 26, i32 28, i32 28, i32 31, i32 27, i32 30, i32 19, i32 24, i32 25, i32 29, i32 23, i32 28, i32 22, i32 25, i32 29>
%cmp = icmp eq <32 x i8> %mask, zeroinitializer %cmp = icmp eq <32 x i8> %mask, zeroinitializer
%res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer %res = select <32 x i1> %cmp, <32 x i8> %shuf, <32 x i8> zeroinitializer
ret <32 x i8> %res ret <32 x i8> %res
} }
define <64 x i8> @test_64xi8_perm_mask0(<64 x i8> %vec) { define <64 x i8> @test_64xi8_perm_mask0(<64 x i8> %vec) {
; GENERIC-LABEL: test_64xi8_perm_mask0: ; GENERIC-LABEL: test_64xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_64xi8_perm_mask0: ; SKX-LABEL: test_64xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 8, i32 4, i32 1, i32 13, i32 15, i32 4, i32 6, i32 12, i32 0, i32 10, i32 2, i32 4, i32 13, i32 0, i32 0, i32 6, i32 23, i32 29, i32 27, i32 26, i32 18, i32 31, i32 22, i32 25, i32 22, i32 16, i32 23, i32 18, i32 16, i32 25, i32 26, i32 17, i32 40, i32 37, i32 38, i32 44, i32 39, i32 46, i32 41, i32 39, i32 42, i32 37, i32 33, i32 42, i32 41, i32 44, i32 34, i32 46, i32 60, i32 62, i32 61, i32 58, i32 60, i32 56, i32 60, i32 51, i32 60, i32 55, i32 60, i32 55, i32 60, i32 49, i32 48, i32 62> %res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 8, i32 4, i32 1, i32 13, i32 15, i32 4, i32 6, i32 12, i32 0, i32 10, i32 2, i32 4, i32 13, i32 0, i32 0, i32 6, i32 23, i32 29, i32 27, i32 26, i32 18, i32 31, i32 22, i32 25, i32 22, i32 16, i32 23, i32 18, i32 16, i32 25, i32 26, i32 17, i32 40, i32 37, i32 38, i32 44, i32 39, i32 46, i32 41, i32 39, i32 42, i32 37, i32 33, i32 42, i32 41, i32 44, i32 34, i32 46, i32 60, i32 62, i32 61, i32 58, i32 60, i32 56, i32 60, i32 51, i32 60, i32 55, i32 60, i32 55, i32 60, i32 49, i32 48, i32 62>
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mask0(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mask0(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mask0: ; GENERIC-LABEL: test_masked_64xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mask0: ; SKX-LABEL: test_masked_64xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [8:1.00]
; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 8, i32 4, i32 1, i32 13, i32 15, i32 4, i32 6, i32 12, i32 0, i32 10, i32 2, i32 4, i32 13, i32 0, i32 0, i32 6, i32 23, i32 29, i32 27, i32 26, i32 18, i32 31, i32 22, i32 25, i32 22, i32 16, i32 23, i32 18, i32 16, i32 25, i32 26, i32 17, i32 40, i32 37, i32 38, i32 44, i32 39, i32 46, i32 41, i32 39, i32 42, i32 37, i32 33, i32 42, i32 41, i32 44, i32 34, i32 46, i32 60, i32 62, i32 61, i32 58, i32 60, i32 56, i32 60, i32 51, i32 60, i32 55, i32 60, i32 55, i32 60, i32 49, i32 48, i32 62> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 8, i32 4, i32 1, i32 13, i32 15, i32 4, i32 6, i32 12, i32 0, i32 10, i32 2, i32 4, i32 13, i32 0, i32 0, i32 6, i32 23, i32 29, i32 27, i32 26, i32 18, i32 31, i32 22, i32 25, i32 22, i32 16, i32 23, i32 18, i32 16, i32 25, i32 26, i32 17, i32 40, i32 37, i32 38, i32 44, i32 39, i32 46, i32 41, i32 39, i32 42, i32 37, i32 33, i32 42, i32 41, i32 44, i32 34, i32 46, i32 60, i32 62, i32 61, i32 58, i32 60, i32 56, i32 60, i32 51, i32 60, i32 55, i32 60, i32 55, i32 60, i32 49, i32 48, i32 62>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mask0(<64 x i8> %vec, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mask0(<64 x i8> %vec, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mask0: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mask0: ; SKX-LABEL: test_masked_z_64xi8_perm_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[8,4,1,13,15,4,6,12,0,10,2,4,13,0,0,6,23,29,27,26,18,31,22,25,22,16,23,18,16,25,26,17,40,37,38,44,39,46,41,39,42,37,33,42,41,44,34,46,60,62,61,58,60,56,60,51,60,55,60,55,60,49,48,62] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 8, i32 4, i32 1, i32 13, i32 15, i32 4, i32 6, i32 12, i32 0, i32 10, i32 2, i32 4, i32 13, i32 0, i32 0, i32 6, i32 23, i32 29, i32 27, i32 26, i32 18, i32 31, i32 22, i32 25, i32 22, i32 16, i32 23, i32 18, i32 16, i32 25, i32 26, i32 17, i32 40, i32 37, i32 38, i32 44, i32 39, i32 46, i32 41, i32 39, i32 42, i32 37, i32 33, i32 42, i32 41, i32 44, i32 34, i32 46, i32 60, i32 62, i32 61, i32 58, i32 60, i32 56, i32 60, i32 51, i32 60, i32 55, i32 60, i32 55, i32 60, i32 49, i32 48, i32 62> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 8, i32 4, i32 1, i32 13, i32 15, i32 4, i32 6, i32 12, i32 0, i32 10, i32 2, i32 4, i32 13, i32 0, i32 0, i32 6, i32 23, i32 29, i32 27, i32 26, i32 18, i32 31, i32 22, i32 25, i32 22, i32 16, i32 23, i32 18, i32 16, i32 25, i32 26, i32 17, i32 40, i32 37, i32 38, i32 44, i32 39, i32 46, i32 41, i32 39, i32 42, i32 37, i32 33, i32 42, i32 41, i32 44, i32 34, i32 46, i32 60, i32 62, i32 61, i32 58, i32 60, i32 56, i32 60, i32 51, i32 60, i32 55, i32 60, i32 55, i32 60, i32 49, i32 48, i32 62>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mask1(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mask1(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mask1: ; GENERIC-LABEL: test_masked_64xi8_perm_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mask1: ; SKX-LABEL: test_masked_64xi8_perm_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [8:1.00]
; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 7, i32 14, i32 15, i32 10, i32 9, i32 3, i32 1, i32 13, i32 14, i32 12, i32 11, i32 6, i32 4, i32 1, i32 6, i32 9, i32 30, i32 30, i32 22, i32 17, i32 28, i32 27, i32 16, i32 23, i32 26, i32 16, i32 30, i32 31, i32 27, i32 17, i32 17, i32 21, i32 32, i32 37, i32 32, i32 47, i32 45, i32 33, i32 46, i32 35, i32 35, i32 42, i32 47, i32 33, i32 32, i32 37, i32 32, i32 41, i32 61, i32 50, i32 49, i32 53, i32 63, i32 50, i32 63, i32 53, i32 55, i32 52, i32 62, i32 63, i32 58, i32 50, i32 63, i32 49> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 7, i32 14, i32 15, i32 10, i32 9, i32 3, i32 1, i32 13, i32 14, i32 12, i32 11, i32 6, i32 4, i32 1, i32 6, i32 9, i32 30, i32 30, i32 22, i32 17, i32 28, i32 27, i32 16, i32 23, i32 26, i32 16, i32 30, i32 31, i32 27, i32 17, i32 17, i32 21, i32 32, i32 37, i32 32, i32 47, i32 45, i32 33, i32 46, i32 35, i32 35, i32 42, i32 47, i32 33, i32 32, i32 37, i32 32, i32 41, i32 61, i32 50, i32 49, i32 53, i32 63, i32 50, i32 63, i32 53, i32 55, i32 52, i32 62, i32 63, i32 58, i32 50, i32 63, i32 49>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mask1(<64 x i8> %vec, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mask1(<64 x i8> %vec, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mask1: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mask1: ; SKX-LABEL: test_masked_z_64xi8_perm_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[7,14,15,10,9,3,1,13,14,12,11,6,4,1,6,9,30,30,22,17,28,27,16,23,26,16,30,31,27,17,17,21,32,37,32,47,45,33,46,35,35,42,47,33,32,37,32,41,61,50,49,53,63,50,63,53,55,52,62,63,58,50,63,49] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 7, i32 14, i32 15, i32 10, i32 9, i32 3, i32 1, i32 13, i32 14, i32 12, i32 11, i32 6, i32 4, i32 1, i32 6, i32 9, i32 30, i32 30, i32 22, i32 17, i32 28, i32 27, i32 16, i32 23, i32 26, i32 16, i32 30, i32 31, i32 27, i32 17, i32 17, i32 21, i32 32, i32 37, i32 32, i32 47, i32 45, i32 33, i32 46, i32 35, i32 35, i32 42, i32 47, i32 33, i32 32, i32 37, i32 32, i32 41, i32 61, i32 50, i32 49, i32 53, i32 63, i32 50, i32 63, i32 53, i32 55, i32 52, i32 62, i32 63, i32 58, i32 50, i32 63, i32 49> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 7, i32 14, i32 15, i32 10, i32 9, i32 3, i32 1, i32 13, i32 14, i32 12, i32 11, i32 6, i32 4, i32 1, i32 6, i32 9, i32 30, i32 30, i32 22, i32 17, i32 28, i32 27, i32 16, i32 23, i32 26, i32 16, i32 30, i32 31, i32 27, i32 17, i32 17, i32 21, i32 32, i32 37, i32 32, i32 47, i32 45, i32 33, i32 46, i32 35, i32 35, i32 42, i32 47, i32 33, i32 32, i32 37, i32 32, i32 41, i32 61, i32 50, i32 49, i32 53, i32 63, i32 50, i32 63, i32 53, i32 55, i32 52, i32 62, i32 63, i32 58, i32 50, i32 63, i32 49>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mask2(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mask2(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mask2: ; GENERIC-LABEL: test_masked_64xi8_perm_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mask2: ; SKX-LABEL: test_masked_64xi8_perm_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [8:1.00]
; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 9, i32 2, i32 14, i32 15, i32 12, i32 5, i32 3, i32 12, i32 4, i32 6, i32 0, i32 2, i32 0, i32 1, i32 1, i32 6, i32 24, i32 27, i32 18, i32 22, i32 26, i32 17, i32 23, i32 21, i32 31, i32 16, i32 22, i32 22, i32 27, i32 21, i32 19, i32 20, i32 39, i32 47, i32 44, i32 36, i32 40, i32 43, i32 44, i32 39, i32 38, i32 44, i32 38, i32 35, i32 39, i32 46, i32 34, i32 39, i32 58, i32 55, i32 51, i32 48, i32 59, i32 57, i32 48, i32 52, i32 60, i32 58, i32 56, i32 50, i32 59, i32 55, i32 58, i32 60> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 9, i32 2, i32 14, i32 15, i32 12, i32 5, i32 3, i32 12, i32 4, i32 6, i32 0, i32 2, i32 0, i32 1, i32 1, i32 6, i32 24, i32 27, i32 18, i32 22, i32 26, i32 17, i32 23, i32 21, i32 31, i32 16, i32 22, i32 22, i32 27, i32 21, i32 19, i32 20, i32 39, i32 47, i32 44, i32 36, i32 40, i32 43, i32 44, i32 39, i32 38, i32 44, i32 38, i32 35, i32 39, i32 46, i32 34, i32 39, i32 58, i32 55, i32 51, i32 48, i32 59, i32 57, i32 48, i32 52, i32 60, i32 58, i32 56, i32 50, i32 59, i32 55, i32 58, i32 60>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mask2(<64 x i8> %vec, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mask2(<64 x i8> %vec, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mask2: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mask2: ; SKX-LABEL: test_masked_z_64xi8_perm_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[9,2,14,15,12,5,3,12,4,6,0,2,0,1,1,6,24,27,18,22,26,17,23,21,31,16,22,22,27,21,19,20,39,47,44,36,40,43,44,39,38,44,38,35,39,46,34,39,58,55,51,48,59,57,48,52,60,58,56,50,59,55,58,60] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 9, i32 2, i32 14, i32 15, i32 12, i32 5, i32 3, i32 12, i32 4, i32 6, i32 0, i32 2, i32 0, i32 1, i32 1, i32 6, i32 24, i32 27, i32 18, i32 22, i32 26, i32 17, i32 23, i32 21, i32 31, i32 16, i32 22, i32 22, i32 27, i32 21, i32 19, i32 20, i32 39, i32 47, i32 44, i32 36, i32 40, i32 43, i32 44, i32 39, i32 38, i32 44, i32 38, i32 35, i32 39, i32 46, i32 34, i32 39, i32 58, i32 55, i32 51, i32 48, i32 59, i32 57, i32 48, i32 52, i32 60, i32 58, i32 56, i32 50, i32 59, i32 55, i32 58, i32 60> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 9, i32 2, i32 14, i32 15, i32 12, i32 5, i32 3, i32 12, i32 4, i32 6, i32 0, i32 2, i32 0, i32 1, i32 1, i32 6, i32 24, i32 27, i32 18, i32 22, i32 26, i32 17, i32 23, i32 21, i32 31, i32 16, i32 22, i32 22, i32 27, i32 21, i32 19, i32 20, i32 39, i32 47, i32 44, i32 36, i32 40, i32 43, i32 44, i32 39, i32 38, i32 44, i32 38, i32 35, i32 39, i32 46, i32 34, i32 39, i32 58, i32 55, i32 51, i32 48, i32 59, i32 57, i32 48, i32 52, i32 60, i32 58, i32 56, i32 50, i32 59, i32 55, i32 58, i32 60>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_64xi8_perm_mask3(<64 x i8> %vec) { define <64 x i8> @test_64xi8_perm_mask3(<64 x i8> %vec) {
; GENERIC-LABEL: test_64xi8_perm_mask3: ; GENERIC-LABEL: test_64xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_64xi8_perm_mask3: ; SKX-LABEL: test_64xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 3, i32 12, i32 4, i32 15, i32 1, i32 14, i32 0, i32 4, i32 8, i32 9, i32 6, i32 1, i32 4, i32 4, i32 12, i32 14, i32 25, i32 16, i32 28, i32 20, i32 21, i32 24, i32 19, i32 30, i32 18, i32 22, i32 20, i32 24, i32 25, i32 26, i32 24, i32 22, i32 42, i32 38, i32 44, i32 44, i32 36, i32 37, i32 42, i32 34, i32 43, i32 38, i32 41, i32 34, i32 42, i32 37, i32 39, i32 38, i32 55, i32 59, i32 53, i32 58, i32 48, i32 52, i32 59, i32 48, i32 57, i32 48, i32 55, i32 62, i32 48, i32 56, i32 49, i32 61> %res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 3, i32 12, i32 4, i32 15, i32 1, i32 14, i32 0, i32 4, i32 8, i32 9, i32 6, i32 1, i32 4, i32 4, i32 12, i32 14, i32 25, i32 16, i32 28, i32 20, i32 21, i32 24, i32 19, i32 30, i32 18, i32 22, i32 20, i32 24, i32 25, i32 26, i32 24, i32 22, i32 42, i32 38, i32 44, i32 44, i32 36, i32 37, i32 42, i32 34, i32 43, i32 38, i32 41, i32 34, i32 42, i32 37, i32 39, i32 38, i32 55, i32 59, i32 53, i32 58, i32 48, i32 52, i32 59, i32 48, i32 57, i32 48, i32 55, i32 62, i32 48, i32 56, i32 49, i32 61>
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mask3(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mask3(<64 x i8> %vec, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mask3: ; GENERIC-LABEL: test_masked_64xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [6:0.50]
; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50] ; GENERIC-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mask3: ; SKX-LABEL: test_masked_64xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm2, %zmm2, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm1 {%k1} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [8:1.00]
; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33] ; SKX-NEXT: vmovdqa64 %zmm1, %zmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 3, i32 12, i32 4, i32 15, i32 1, i32 14, i32 0, i32 4, i32 8, i32 9, i32 6, i32 1, i32 4, i32 4, i32 12, i32 14, i32 25, i32 16, i32 28, i32 20, i32 21, i32 24, i32 19, i32 30, i32 18, i32 22, i32 20, i32 24, i32 25, i32 26, i32 24, i32 22, i32 42, i32 38, i32 44, i32 44, i32 36, i32 37, i32 42, i32 34, i32 43, i32 38, i32 41, i32 34, i32 42, i32 37, i32 39, i32 38, i32 55, i32 59, i32 53, i32 58, i32 48, i32 52, i32 59, i32 48, i32 57, i32 48, i32 55, i32 62, i32 48, i32 56, i32 49, i32 61> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 3, i32 12, i32 4, i32 15, i32 1, i32 14, i32 0, i32 4, i32 8, i32 9, i32 6, i32 1, i32 4, i32 4, i32 12, i32 14, i32 25, i32 16, i32 28, i32 20, i32 21, i32 24, i32 19, i32 30, i32 18, i32 22, i32 20, i32 24, i32 25, i32 26, i32 24, i32 22, i32 42, i32 38, i32 44, i32 44, i32 36, i32 37, i32 42, i32 34, i32 43, i32 38, i32 41, i32 34, i32 42, i32 37, i32 39, i32 38, i32 55, i32 59, i32 53, i32 58, i32 48, i32 52, i32 59, i32 48, i32 57, i32 48, i32 55, i32 62, i32 48, i32 56, i32 49, i32 61>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mask3(<64 x i8> %vec, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mask3(<64 x i8> %vec, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mask3: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mask3: ; SKX-LABEL: test_masked_z_64xi8_perm_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm0[3,12,4,15,1,14,0,4,8,9,6,1,4,4,12,14,25,16,28,20,21,24,19,30,18,22,20,24,25,26,24,22,42,38,44,44,36,37,42,34,43,38,41,34,42,37,39,38,55,59,53,58,48,52,59,48,57,48,55,62,48,56,49,61] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 3, i32 12, i32 4, i32 15, i32 1, i32 14, i32 0, i32 4, i32 8, i32 9, i32 6, i32 1, i32 4, i32 4, i32 12, i32 14, i32 25, i32 16, i32 28, i32 20, i32 21, i32 24, i32 19, i32 30, i32 18, i32 22, i32 20, i32 24, i32 25, i32 26, i32 24, i32 22, i32 42, i32 38, i32 44, i32 44, i32 36, i32 37, i32 42, i32 34, i32 43, i32 38, i32 41, i32 34, i32 42, i32 37, i32 39, i32 38, i32 55, i32 59, i32 53, i32 58, i32 48, i32 52, i32 59, i32 48, i32 57, i32 48, i32 55, i32 62, i32 48, i32 56, i32 49, i32 61> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 3, i32 12, i32 4, i32 15, i32 1, i32 14, i32 0, i32 4, i32 8, i32 9, i32 6, i32 1, i32 4, i32 4, i32 12, i32 14, i32 25, i32 16, i32 28, i32 20, i32 21, i32 24, i32 19, i32 30, i32 18, i32 22, i32 20, i32 24, i32 25, i32 26, i32 24, i32 22, i32 42, i32 38, i32 44, i32 44, i32 36, i32 37, i32 42, i32 34, i32 43, i32 38, i32 41, i32 34, i32 42, i32 37, i32 39, i32 38, i32 55, i32 59, i32 53, i32 58, i32 48, i32 52, i32 59, i32 48, i32 57, i32 48, i32 55, i32 62, i32 48, i32 56, i32 49, i32 61>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_64xi8_perm_mem_mask0(<64 x i8>* %vp) { define <64 x i8> @test_64xi8_perm_mem_mask0(<64 x i8>* %vp) {
; GENERIC-LABEL: test_64xi8_perm_mem_mask0: ; GENERIC-LABEL: test_64xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [6:0.50]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_64xi8_perm_mem_mask0: ; SKX-LABEL: test_64xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [8:0.50]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 0, i32 9, i32 15, i32 13, i32 11, i32 11, i32 3, i32 12, i32 4, i32 1, i32 7, i32 5, i32 2, i32 6, i32 14, i32 6, i32 23, i32 27, i32 24, i32 18, i32 30, i32 23, i32 28, i32 22, i32 28, i32 22, i32 19, i32 19, i32 31, i32 25, i32 16, i32 22, i32 35, i32 33, i32 34, i32 32, i32 42, i32 34, i32 41, i32 41, i32 43, i32 40, i32 36, i32 46, i32 37, i32 39, i32 42, i32 40, i32 63, i32 63, i32 62, i32 62, i32 57, i32 55, i32 59, i32 51, i32 52, i32 48, i32 50, i32 48, i32 58, i32 50, i32 60, i32 58> %res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 0, i32 9, i32 15, i32 13, i32 11, i32 11, i32 3, i32 12, i32 4, i32 1, i32 7, i32 5, i32 2, i32 6, i32 14, i32 6, i32 23, i32 27, i32 24, i32 18, i32 30, i32 23, i32 28, i32 22, i32 28, i32 22, i32 19, i32 19, i32 31, i32 25, i32 16, i32 22, i32 35, i32 33, i32 34, i32 32, i32 42, i32 34, i32 41, i32 41, i32 43, i32 40, i32 36, i32 46, i32 37, i32 39, i32 42, i32 40, i32 63, i32 63, i32 62, i32 62, i32 57, i32 55, i32 59, i32 51, i32 52, i32 48, i32 50, i32 48, i32 58, i32 50, i32 60, i32 58>
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mem_mask0(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mem_mask0(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask0: ; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mem_mask0: ; SKX-LABEL: test_masked_64xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 0, i32 9, i32 15, i32 13, i32 11, i32 11, i32 3, i32 12, i32 4, i32 1, i32 7, i32 5, i32 2, i32 6, i32 14, i32 6, i32 23, i32 27, i32 24, i32 18, i32 30, i32 23, i32 28, i32 22, i32 28, i32 22, i32 19, i32 19, i32 31, i32 25, i32 16, i32 22, i32 35, i32 33, i32 34, i32 32, i32 42, i32 34, i32 41, i32 41, i32 43, i32 40, i32 36, i32 46, i32 37, i32 39, i32 42, i32 40, i32 63, i32 63, i32 62, i32 62, i32 57, i32 55, i32 59, i32 51, i32 52, i32 48, i32 50, i32 48, i32 58, i32 50, i32 60, i32 58> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 0, i32 9, i32 15, i32 13, i32 11, i32 11, i32 3, i32 12, i32 4, i32 1, i32 7, i32 5, i32 2, i32 6, i32 14, i32 6, i32 23, i32 27, i32 24, i32 18, i32 30, i32 23, i32 28, i32 22, i32 28, i32 22, i32 19, i32 19, i32 31, i32 25, i32 16, i32 22, i32 35, i32 33, i32 34, i32 32, i32 42, i32 34, i32 41, i32 41, i32 43, i32 40, i32 36, i32 46, i32 37, i32 39, i32 42, i32 40, i32 63, i32 63, i32 62, i32 62, i32 57, i32 55, i32 59, i32 51, i32 52, i32 48, i32 50, i32 48, i32 58, i32 50, i32 60, i32 58>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mem_mask0(<64 x i8>* %vp, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mem_mask0(<64 x i8>* %vp, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask0: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask0:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask0: ; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask0:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[0,9,15,13,11,11,3,12,4,1,7,5,2,6,14,6,23,27,24,18,30,23,28,22,28,22,19,19,31,25,16,22,35,33,34,32,42,34,41,41,43,40,36,46,37,39,42,40,63,63,62,62,57,55,59,51,52,48,50,48,58,50,60,58] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 0, i32 9, i32 15, i32 13, i32 11, i32 11, i32 3, i32 12, i32 4, i32 1, i32 7, i32 5, i32 2, i32 6, i32 14, i32 6, i32 23, i32 27, i32 24, i32 18, i32 30, i32 23, i32 28, i32 22, i32 28, i32 22, i32 19, i32 19, i32 31, i32 25, i32 16, i32 22, i32 35, i32 33, i32 34, i32 32, i32 42, i32 34, i32 41, i32 41, i32 43, i32 40, i32 36, i32 46, i32 37, i32 39, i32 42, i32 40, i32 63, i32 63, i32 62, i32 62, i32 57, i32 55, i32 59, i32 51, i32 52, i32 48, i32 50, i32 48, i32 58, i32 50, i32 60, i32 58> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 0, i32 9, i32 15, i32 13, i32 11, i32 11, i32 3, i32 12, i32 4, i32 1, i32 7, i32 5, i32 2, i32 6, i32 14, i32 6, i32 23, i32 27, i32 24, i32 18, i32 30, i32 23, i32 28, i32 22, i32 28, i32 22, i32 19, i32 19, i32 31, i32 25, i32 16, i32 22, i32 35, i32 33, i32 34, i32 32, i32 42, i32 34, i32 41, i32 41, i32 43, i32 40, i32 36, i32 46, i32 37, i32 39, i32 42, i32 40, i32 63, i32 63, i32 62, i32 62, i32 57, i32 55, i32 59, i32 51, i32 52, i32 48, i32 50, i32 48, i32 58, i32 50, i32 60, i32 58>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mem_mask1(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mem_mask1(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask1: ; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mem_mask1: ; SKX-LABEL: test_masked_64xi8_perm_mem_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 15, i32 6, i32 14, i32 7, i32 5, i32 1, i32 14, i32 12, i32 5, i32 7, i32 5, i32 0, i32 0, i32 5, i32 3, i32 8, i32 19, i32 19, i32 26, i32 27, i32 20, i32 29, i32 20, i32 21, i32 27, i32 16, i32 30, i32 17, i32 23, i32 27, i32 16, i32 28, i32 47, i32 39, i32 33, i32 33, i32 33, i32 44, i32 38, i32 46, i32 39, i32 33, i32 38, i32 44, i32 45, i32 32, i32 34, i32 39, i32 50, i32 61, i32 62, i32 53, i32 54, i32 56, i32 52, i32 56, i32 51, i32 52, i32 55, i32 57, i32 56, i32 52, i32 51, i32 49> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 15, i32 6, i32 14, i32 7, i32 5, i32 1, i32 14, i32 12, i32 5, i32 7, i32 5, i32 0, i32 0, i32 5, i32 3, i32 8, i32 19, i32 19, i32 26, i32 27, i32 20, i32 29, i32 20, i32 21, i32 27, i32 16, i32 30, i32 17, i32 23, i32 27, i32 16, i32 28, i32 47, i32 39, i32 33, i32 33, i32 33, i32 44, i32 38, i32 46, i32 39, i32 33, i32 38, i32 44, i32 45, i32 32, i32 34, i32 39, i32 50, i32 61, i32 62, i32 53, i32 54, i32 56, i32 52, i32 56, i32 51, i32 52, i32 55, i32 57, i32 56, i32 52, i32 51, i32 49>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mem_mask1(<64 x i8>* %vp, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mem_mask1(<64 x i8>* %vp, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask1: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask1:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask1: ; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask1:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[15,6,14,7,5,1,14,12,5,7,5,0,0,5,3,8,19,19,26,27,20,29,20,21,27,16,30,17,23,27,16,28,47,39,33,33,33,44,38,46,39,33,38,44,45,32,34,39,50,61,62,53,54,56,52,56,51,52,55,57,56,52,51,49] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 15, i32 6, i32 14, i32 7, i32 5, i32 1, i32 14, i32 12, i32 5, i32 7, i32 5, i32 0, i32 0, i32 5, i32 3, i32 8, i32 19, i32 19, i32 26, i32 27, i32 20, i32 29, i32 20, i32 21, i32 27, i32 16, i32 30, i32 17, i32 23, i32 27, i32 16, i32 28, i32 47, i32 39, i32 33, i32 33, i32 33, i32 44, i32 38, i32 46, i32 39, i32 33, i32 38, i32 44, i32 45, i32 32, i32 34, i32 39, i32 50, i32 61, i32 62, i32 53, i32 54, i32 56, i32 52, i32 56, i32 51, i32 52, i32 55, i32 57, i32 56, i32 52, i32 51, i32 49> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 15, i32 6, i32 14, i32 7, i32 5, i32 1, i32 14, i32 12, i32 5, i32 7, i32 5, i32 0, i32 0, i32 5, i32 3, i32 8, i32 19, i32 19, i32 26, i32 27, i32 20, i32 29, i32 20, i32 21, i32 27, i32 16, i32 30, i32 17, i32 23, i32 27, i32 16, i32 28, i32 47, i32 39, i32 33, i32 33, i32 33, i32 44, i32 38, i32 46, i32 39, i32 33, i32 38, i32 44, i32 45, i32 32, i32 34, i32 39, i32 50, i32 61, i32 62, i32 53, i32 54, i32 56, i32 52, i32 56, i32 51, i32 52, i32 55, i32 57, i32 56, i32 52, i32 51, i32 49>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mem_mask2(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mem_mask2(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask2: ; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mem_mask2: ; SKX-LABEL: test_masked_64xi8_perm_mem_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 12, i32 1, i32 11, i32 3, i32 4, i32 11, i32 10, i32 11, i32 8, i32 13, i32 1, i32 10, i32 1, i32 11, i32 5, i32 10, i32 27, i32 26, i32 19, i32 29, i32 19, i32 24, i32 26, i32 19, i32 26, i32 20, i32 18, i32 28, i32 24, i32 21, i32 25, i32 16, i32 34, i32 38, i32 47, i32 40, i32 33, i32 44, i32 44, i32 44, i32 41, i32 43, i32 35, i32 43, i32 45, i32 44, i32 37, i32 41, i32 58, i32 62, i32 49, i32 61, i32 56, i32 53, i32 55, i32 48, i32 51, i32 58, i32 58, i32 55, i32 63, i32 55, i32 53, i32 61> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 12, i32 1, i32 11, i32 3, i32 4, i32 11, i32 10, i32 11, i32 8, i32 13, i32 1, i32 10, i32 1, i32 11, i32 5, i32 10, i32 27, i32 26, i32 19, i32 29, i32 19, i32 24, i32 26, i32 19, i32 26, i32 20, i32 18, i32 28, i32 24, i32 21, i32 25, i32 16, i32 34, i32 38, i32 47, i32 40, i32 33, i32 44, i32 44, i32 44, i32 41, i32 43, i32 35, i32 43, i32 45, i32 44, i32 37, i32 41, i32 58, i32 62, i32 49, i32 61, i32 56, i32 53, i32 55, i32 48, i32 51, i32 58, i32 58, i32 55, i32 63, i32 55, i32 53, i32 61>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mem_mask2(<64 x i8>* %vp, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mem_mask2(<64 x i8>* %vp, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask2: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask2:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask2: ; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask2:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[12,1,11,3,4,11,10,11,8,13,1,10,1,11,5,10,27,26,19,29,19,24,26,19,26,20,18,28,24,21,25,16,34,38,47,40,33,44,44,44,41,43,35,43,45,44,37,41,58,62,49,61,56,53,55,48,51,58,58,55,63,55,53,61] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 12, i32 1, i32 11, i32 3, i32 4, i32 11, i32 10, i32 11, i32 8, i32 13, i32 1, i32 10, i32 1, i32 11, i32 5, i32 10, i32 27, i32 26, i32 19, i32 29, i32 19, i32 24, i32 26, i32 19, i32 26, i32 20, i32 18, i32 28, i32 24, i32 21, i32 25, i32 16, i32 34, i32 38, i32 47, i32 40, i32 33, i32 44, i32 44, i32 44, i32 41, i32 43, i32 35, i32 43, i32 45, i32 44, i32 37, i32 41, i32 58, i32 62, i32 49, i32 61, i32 56, i32 53, i32 55, i32 48, i32 51, i32 58, i32 58, i32 55, i32 63, i32 55, i32 53, i32 61> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 12, i32 1, i32 11, i32 3, i32 4, i32 11, i32 10, i32 11, i32 8, i32 13, i32 1, i32 10, i32 1, i32 11, i32 5, i32 10, i32 27, i32 26, i32 19, i32 29, i32 19, i32 24, i32 26, i32 19, i32 26, i32 20, i32 18, i32 28, i32 24, i32 21, i32 25, i32 16, i32 34, i32 38, i32 47, i32 40, i32 33, i32 44, i32 44, i32 44, i32 41, i32 43, i32 35, i32 43, i32 45, i32 44, i32 37, i32 41, i32 58, i32 62, i32 49, i32 61, i32 56, i32 53, i32 55, i32 48, i32 51, i32 58, i32 58, i32 55, i32 63, i32 55, i32 53, i32 61>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> zeroinitializer
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_64xi8_perm_mem_mask3(<64 x i8>* %vp) { define <64 x i8> @test_64xi8_perm_mem_mask3(<64 x i8>* %vp) {
; GENERIC-LABEL: test_64xi8_perm_mem_mask3: ; GENERIC-LABEL: test_64xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [6:0.50]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_64xi8_perm_mem_mask3: ; SKX-LABEL: test_64xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm0 # sched: [8:0.50]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 4, i32 9, i32 11, i32 13, i32 12, i32 6, i32 0, i32 0, i32 11, i32 15, i32 5, i32 7, i32 11, i32 10, i32 4, i32 10, i32 20, i32 21, i32 24, i32 27, i32 18, i32 16, i32 26, i32 16, i32 16, i32 19, i32 26, i32 17, i32 16, i32 31, i32 22, i32 30, i32 35, i32 38, i32 37, i32 34, i32 37, i32 47, i32 43, i32 38, i32 38, i32 36, i32 40, i32 43, i32 42, i32 39, i32 32, i32 46, i32 54, i32 54, i32 48, i32 50, i32 61, i32 56, i32 59, i32 50, i32 53, i32 61, i32 61, i32 51, i32 48, i32 60, i32 50, i32 60> %res = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 4, i32 9, i32 11, i32 13, i32 12, i32 6, i32 0, i32 0, i32 11, i32 15, i32 5, i32 7, i32 11, i32 10, i32 4, i32 10, i32 20, i32 21, i32 24, i32 27, i32 18, i32 16, i32 26, i32 16, i32 16, i32 19, i32 26, i32 17, i32 16, i32 31, i32 22, i32 30, i32 35, i32 38, i32 37, i32 34, i32 37, i32 47, i32 43, i32 38, i32 38, i32 36, i32 40, i32 43, i32 42, i32 39, i32 32, i32 46, i32 54, i32 54, i32 48, i32 50, i32 61, i32 56, i32 59, i32 50, i32 53, i32 61, i32 61, i32 51, i32 48, i32 60, i32 50, i32 60>
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_64xi8_perm_mem_mask3(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) { define <64 x i8> @test_masked_64xi8_perm_mem_mask3(<64 x i8>* %vp, <64 x i8> %vec2, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask3: ; GENERIC-LABEL: test_masked_64xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_64xi8_perm_mem_mask3: ; SKX-LABEL: test_masked_64xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm2 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm1, %zmm1, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} = zmm2[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
%vec = load <64 x i8>, <64 x i8>* %vp %vec = load <64 x i8>, <64 x i8>* %vp
%shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 4, i32 9, i32 11, i32 13, i32 12, i32 6, i32 0, i32 0, i32 11, i32 15, i32 5, i32 7, i32 11, i32 10, i32 4, i32 10, i32 20, i32 21, i32 24, i32 27, i32 18, i32 16, i32 26, i32 16, i32 16, i32 19, i32 26, i32 17, i32 16, i32 31, i32 22, i32 30, i32 35, i32 38, i32 37, i32 34, i32 37, i32 47, i32 43, i32 38, i32 38, i32 36, i32 40, i32 43, i32 42, i32 39, i32 32, i32 46, i32 54, i32 54, i32 48, i32 50, i32 61, i32 56, i32 59, i32 50, i32 53, i32 61, i32 61, i32 51, i32 48, i32 60, i32 50, i32 60> %shuf = shufflevector <64 x i8> %vec, <64 x i8> undef, <64 x i32> <i32 4, i32 9, i32 11, i32 13, i32 12, i32 6, i32 0, i32 0, i32 11, i32 15, i32 5, i32 7, i32 11, i32 10, i32 4, i32 10, i32 20, i32 21, i32 24, i32 27, i32 18, i32 16, i32 26, i32 16, i32 16, i32 19, i32 26, i32 17, i32 16, i32 31, i32 22, i32 30, i32 35, i32 38, i32 37, i32 34, i32 37, i32 47, i32 43, i32 38, i32 38, i32 36, i32 40, i32 43, i32 42, i32 39, i32 32, i32 46, i32 54, i32 54, i32 48, i32 50, i32 61, i32 56, i32 59, i32 50, i32 53, i32 61, i32 61, i32 51, i32 48, i32 60, i32 50, i32 60>
%cmp = icmp eq <64 x i8> %mask, zeroinitializer %cmp = icmp eq <64 x i8> %mask, zeroinitializer
%res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2 %res = select <64 x i1> %cmp, <64 x i8> %shuf, <64 x i8> %vec2
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @test_masked_z_64xi8_perm_mem_mask3(<64 x i8>* %vp, <64 x i8> %mask) { define <64 x i8> @test_masked_z_64xi8_perm_mem_mask3(<64 x i8>* %vp, <64 x i8> %mask) {
; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask3: ; GENERIC-LABEL: test_masked_z_64xi8_perm_mem_mask3:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50] ; GENERIC-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [6:0.50]
; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00] ; GENERIC-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [1:1.00]
; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [6:1.00] ; GENERIC-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask3: ; SKX-LABEL: test_masked_z_64xi8_perm_mem_mask3:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50] ; SKX-NEXT: vmovdqa64 (%rdi), %zmm1 # sched: [8:0.50]
; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00] ; SKX-NEXT: vptestnmb %zmm0, %zmm0, %k1 # sched: [3:1.00]
; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [8:1.00] ; SKX-NEXT: vpshufb {{.*#+}} zmm0 {%k1} {z} = zmm1[4,9,11,13,12,6,0,0,11,15,5,7,11,10,4,10,20,21,24,27,18,16,26,16,16,19,26,17,16,31,22,30,35,38,37,34,37,47,43,38,38,36,40,43,42,39,32,46,54,54,48,50,61,56,59,50,53,61,61,51,48,60,50,60] sched: [8:1.00]
; SKX-NEXT: retq # sched: [7:1.00] ; SKX-NEXT: retq # sched: [7:1.00]
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llvm/trunk/test/CodeGen/X86/xop-schedule.ll

Show First 20 Lines • Show All 837 Lines • ▼ Show 20 Lines; BDVER-NEXT: retq
call void asm sideeffect "vpmadcswd $2, $1, $0, $0 \0a\09 vpmadcswd $2, $3, $0, $0", "x,x,x,*m"(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, <2 x i64> *%a3) call void asm sideeffect "vpmadcswd $2, $1, $0, $0 \0a\09 vpmadcswd $2, $3, $0, $0", "x,x,x,*m"(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, <2 x i64> *%a3)
ret void ret void
} }
define void @test_vpperm(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, <2 x i64> *%a3) { define void @test_vpperm(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, <2 x i64> *%a3) {
; GENERIC-LABEL: test_vpperm: ; GENERIC-LABEL: test_vpperm:
; GENERIC: # %bb.0: ; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP ; GENERIC-NEXT: #APP
; GENERIC-NEXT: vpperm %xmm2, %xmm1, %xmm0, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: vpperm %xmm2, %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: vpperm (%rdi), %xmm1, %xmm0, %xmm0 # sched: [6:1.00] ; GENERIC-NEXT: vpperm (%rdi), %xmm1, %xmm0, %xmm0 # sched: [6:0.50]
; GENERIC-NEXT: vpperm %xmm2, (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; GENERIC-NEXT: vpperm %xmm2, (%rdi), %xmm0, %xmm0 # sched: [6:0.50]
; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; BDVER-LABEL: test_vpperm: ; BDVER-LABEL: test_vpperm:
; BDVER: # %bb.0: ; BDVER: # %bb.0:
; BDVER-NEXT: #APP ; BDVER-NEXT: #APP
; BDVER-NEXT: vpperm %xmm2, %xmm1, %xmm0, %xmm0 ; BDVER-NEXT: vpperm %xmm2, %xmm1, %xmm0, %xmm0
; BDVER-NEXT: vpperm (%rdi), %xmm1, %xmm0, %xmm0 ; BDVER-NEXT: vpperm (%rdi), %xmm1, %xmm0, %xmm0
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