[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision

[lei]

Summary

Legalize and emit code for:

• xscvsdqp
• xscvudqp

[nemanjai]

I think overall, we want to cover all the ways we can get the input integer:

• Extending load from a smaller type (only unsigned forms for byte and halfword, both signed and unsigned for word)
• Extracting from a vector (with sign extensions as needed)
• Smaller types in registers
• An fp to int conversion
• A bitcast

I don't mind that being split up into multiple patches, but I think we can at least start with a test case for each of the cases with FIXME's for what we're going to cover in upcoming patches.

lib/Target/PowerPC/PPCInstrVSX.td

3121

I just realized that we should also add patterns for converting an extracted vector value to f128 because it will currently do mfvsrd -> mtvsrd -> xscv[us]dqp which is obviously redundant.
We will also need patterns for extending loads from byte, halfword and word.

test/CodeGen/PowerPC/f128-conv.ll

3

Please add test cases that convert from smaller integer types as well (byte, halfword and word).

22

Please also add a version of the test where the integer value is passed as a parameter by pointer (for both the signed and unsigned conversions).

[lei]

lib/Target/PowerPC/PPCInstrVSX.td

3121

Will post patterns for extending these in a separate patch.

test/CodeGen/PowerPC/f128-conv.ll

3

will be done in a separate patch

22

okay

[lei]

Additional test cases added: [u|s]dwConv2qp_03()

[lei]

Only legalize (un)signed int to FP conv if converting to f128

[nemanjai]

LGTM. Feel free to address the nit comments on the commit.

lib/Target/PowerPC/PPCISelLowering.cpp

9415

Nit: complete sentences - don't forget the punctuation. Also, no need to be this generic here. Something like // Conversions to f128 are legal. should communicate this more clearly.

test/CodeGen/PowerPC/f128-conv.ll

18

This isn't guaranteed to use the same register for input/output. Perhaps something like:
; CHECK: xscvsdqp [[CONV:[0-9]+]], [[REG]]
would be more appropriate (and of course, use CONV below).
This applies to all the tests below.

103

Please add a test case that will actually use the X-Form load. Perhaps something like:

void testXForm(__float128 *sink, signed char *a) {
  *sink = *((long long *) (a + 3));
}

lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasP9Vector()) {
         addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
         setOperationAction(ISD::FADD, MVT::f128, Legal);
         setOperationAction(ISD::FSUB, MVT::f128, Legal);
         setOperationAction(ISD::FDIV, MVT::f128, Legal);
         setOperationAction(ISD::FMUL, MVT::f128, Legal);
         setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
         setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
         setOperationAction(ISD::FMA, MVT::f128, Legal);
+        setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
+        setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
       }
 
     }
 
     if (Subtarget.hasP9Altivec()) {
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
     }
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::STORE:              return LowerSTORE(Op, DAG);
   case ISD::TRUNCATE:           return LowerTRUNCATE(Op, DAG);
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
   case ISD::FP_TO_UINT:
   case ISD::FP_TO_SINT:         return LowerFP_TO_INT(Op, DAG,
                                                       SDLoc(Op));
   case ISD::UINT_TO_FP:
   case ISD::SINT_TO_FP:         return LowerINT_TO_FP(Op, DAG);
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
 
   // Lower 64-bit shifts.
   case ISD::SHL_PARTS:          return LowerSHL_PARTS(Op, DAG);
   case ISD::SRL_PARTS:          return LowerSRL_PARTS(Op, DAG);
   case ISD::SRA_PARTS:          return LowerSRA_PARTS(Op, DAG);
 
   // Vector-related lowering.
   case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
   def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
   def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz", []>;
 
   // Convert (Un)Signed DWord -> QP
   def XSCVSDQP  : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
+  def : Pat<(f128 (sint_to_fp i64:$src)),
+            (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+
   def XSCVUDQP  : X_VT5_XO5_VB5_TyVB<63,  2, 836, "xscvudqp", vfrc, []>;
+  def : Pat<(f128 (uint_to_fp i64:$src)),
+            (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
 
   let UseVSXReg = 1 in {
   //===--------------------------------------------------------------------===//
   // Round to Floating-Point Integer Instructions
 
   // (Round &) Convert DP <-> HP
   // Note! xscvdphp's src and dest register both use the left 64 bits, so we use
   // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits,
let isPseudo = 1 in {
     def DFSTOREf64 : Pseudo<(outs), (ins vsfrc:$XT, memrix:$dst),
                             "#DFSTOREf64",
                             [(store f64:$XT, ixaddr:$dst)]>;
   }
   def : Pat<(f64 (extloadf32 ixaddr:$src)),
             (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>;
   def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
             (f32 (DFLOADf32 ixaddr:$src))>;
+
+  // Convert (Un)Signed DWord in memory -> QP
+  def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))),
+            (f128 (XSCVSDQP (LXSDX xaddr:$src)))>;
+  def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))),
+            (f128 (XSCVSDQP (LXSD ixaddr:$src)))>;
+  def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))),
+            (f128 (XSCVUDQP (LXSDX xaddr:$src)))>;
+  def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))),
+            (f128 (XSCVUDQP (LXSD ixaddr:$src)))>;
+
 } // end HasP9Vector, AddedComplexity
 
 let Predicates = [HasP9Vector] in {
   let isPseudo = 1 in {
     let mayStore = 1 in {
       def SPILLTOVSR_STX : Pseudo<(outs), (ins spilltovsrrc:$XT, memrr:$dst),
                                 "#SPILLTOVSR_STX", []>;
       def SPILLTOVSR_ST : Pseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),

test/CodeGen/PowerPC/f128-conv.ll

+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
+@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
+
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp(fp128* nocapture %a, i64 %b) {
+entry:
+  %conv = sitofp i64 %b to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+
+; CHECK-LABEL: sdwConv2qp
+; CHECK: mtvsrd [[REG:[0-9]+]], 4
+; CHECK-NEXT: xscvsdqp [[REG]], [[REG]]
+; CHECK-NEXT: stxv [[REG]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp_02(fp128* nocapture %a) {
+entry:
+  %0 = load i64, i64* getelementptr inbounds 
+                        ([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8
+  %conv = sitofp i64 %0 to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+
+; CHECK-LABEL: sdwConv2qp_02
+; CHECK: addis [[REG:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld [[REG]], .LC0@toc@l([[REG]])
+; CHECK: lxsd [[REG0:[0-9]+]], 16([[REG]])
+; CHECK-NEXT: xscvsdqp [[REG0]], [[REG0]]
+; CHECK-NEXT: stxv [[REG0]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwConv2qp(fp128* nocapture %a, i64 %b) {
+entry:
+  %conv = uitofp i64 %b to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+
+; CHECK-LABEL: udwConv2qp
+; CHECK: mtvsrd [[REG:[0-9]+]], 4
+; CHECK-NEXT: xscvudqp [[REG]], [[REG]]
+; CHECK-NEXT: stxv [[REG]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwConv2qp_02(fp128* nocapture %a) {
+entry:
+  %0 = load i64, i64* getelementptr inbounds
+                        ([5 x i64], [5 x i64]* @umem, i64 0, i64 4), align 8
+  %conv = uitofp i64 %0 to fp128
+  store fp128 %conv, fp128* %a, align 16
+  ret void
+
+; CHECK-LABEL: udwConv2qp_02
+; CHECK: addis [[REG:[0-9]+]], 2, .LC1@toc@ha
+; CHECK: ld [[REG]], .LC1@toc@l([[REG]])
+; CHECK: lxsd [[REG0:[0-9]+]], 32([[REG]])
+; CHECK-NEXT: xscvudqp [[REG0]], [[REG0]]
+; CHECK-NEXT: stxv [[REG0]], 0(3)
+; CHECK-NEXT: blr
+}
+