[ARM] Support float literals under XO

[christof]

Summary

Follow up patch of r328313 to support the UseVMOVSR constraint. Removed some unneeded instructions from the test and removed some stray comments.

[efriedma]

LGTM

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

if (LHS.getValueType() == MVT::i32) {
     SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
     return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
   }
 
   ARMCC::CondCodes CondCode, CondCode2;
   bool InvalidOnQNaN;
   FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
 
-  // Try to generate VMAXNM/VMINNM on ARMv8. Except if we compare to a zero.
-  // This ensures we use CMPFPw0 instead of CMPFP in such case.
+  // Normalize the fp compare. If RHS is zero we keep it there so we match
+  // CMPFPw0 instead of CMPFP.
   if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
     (TrueVal.getValueType() == MVT::f32 || TrueVal.getValueType() == MVT::f64)) {
     bool swpCmpOps = false;
     bool swpVselOps = false;
     checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
 
     if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
         CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {

llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
              (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
 
 
 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
 def : Pat<(f32 (bitconvert GPR:$a)),
           (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
         Requires<[HasNEON, DontUseVMOVSR]>;
+def : Pat<(arm_vmovsr GPR:$a),
+          (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
+        Requires<[HasNEON, DontUseVMOVSR]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
 // bit_convert
 let Predicates = [IsLE] in {
   def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

def VMOVSR : AVConv4I<0b11100000, 0b1010,
 
   let Inst{6-5}   = 0b00;
   let Inst{3-0}   = 0b0000;
 
   // Some single precision VFP instructions may be executed on both NEON and VFP
   // pipelines.
   let D = VFPNeonDomain;
 }
-def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>;
+def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>;
 
 let hasSideEffects = 0 in {
 def VMOVRRD  : AVConv3I<0b11000101, 0b1011,
                         (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
                         IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
                  [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
                Sched<[WriteFPMOV]> {
   // Instruction operands.

llvm/trunk/test/CodeGen/ARM/fcmp-xo.ll

-; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 %s -o - | FileCheck --check-prefixes=CHECK,VMOVSR %s
+; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp %s -o - | FileCheck --check-prefixes=CHECK,NEON %s
 
-; This function used to run into a code selection error on fp-armv8 due to
-; different ordering of the constant arguments of fcmp. Fixed by extending the
-; code selection to handle the missing case.
-define arm_aapcs_vfpcc void @foo0() local_unnamed_addr {
-  br i1 undef, label %.end, label %1
-
-  %2 = fcmp nsz olt float undef, 0.000000e+00
-  %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
-  %4 = fadd nsz float undef, %3
-  %5 = fptosi float %4 to i32
-  %6 = ashr i32 %5, 4
-  %7 = icmp slt i32 %6, 0
-  br i1 %7, label %8, label %.end
-
-  tail call arm_aapcs_vfpcc void @bar()
-  br label %.end
-
-.end:
-  ret void
+define arm_aapcs_vfpcc float @foo0() local_unnamed_addr {
+  %1 = fcmp nsz olt float undef, 0.000000e+00
+  %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
+  ret float %2
 }
 ; CHECK-LABEL: foo0
 ; CHECK: vcmpe.f32 {{s[0-9]+}}, #0
 
 
-define arm_aapcs_vfpcc void @float1() local_unnamed_addr {
+define arm_aapcs_vfpcc float @float1() local_unnamed_addr {
   br i1 undef, label %.end, label %1
 
   %2 = fcmp nsz olt float undef, 1.000000e+00
   %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
-  %4 = fadd nsz float undef, %3
-  %5 = fptosi float %4 to i32
-  %6 = ashr i32 %5, 4
-  %7 = icmp slt i32 %6, 0
-  br i1 %7, label %8, label %.end
-
-  tail call arm_aapcs_vfpcc void @bar()
   br label %.end
 
 .end:
-  ret void
+  %4 = phi float [ undef, %0 ], [ %3, %1]
+  ret float %4
 }
 ; CHECK-LABEL: float1
 ; CHECK: vmov.f32 [[FPREG:s[0-9]+]], #1.000000e+00
 ; CHECK: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
 
-define arm_aapcs_vfpcc void @float128() local_unnamed_addr {
-  br i1 undef, label %.end, label %1
-
-  %2 = fcmp nsz olt float undef, 128.000000e+00
-  %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
-  %4 = fadd nsz float undef, %3
-  %5 = fptosi float %4 to i32
-  %6 = ashr i32 %5, 4
-  %7 = icmp slt i32 %6, 0
-  br i1 %7, label %8, label %.end
-
-  tail call arm_aapcs_vfpcc void @bar()
-  br label %.end
-
-.end:
-  ret void
+define arm_aapcs_vfpcc float @float128() local_unnamed_addr {
+  %1 = fcmp nsz olt float undef, 128.000000e+00
+  %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
+  ret float %2
 }
 ; CHECK-LABEL: float128
 ; CHECK: mov.w [[REG:r[0-9]+]], #1124073472
-; CHECK: vmov [[FPREG:s[0-9]+]], [[REG]]
-; CHECK: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
+; VMOVSR: vmov [[FPREG:s[0-9]+]], [[REG]]
+; VMOVSR: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
+; NEON: vmov d2, [[REG]], [[REG]]
+; NEON: vcmpe.f32 s4, {{s[0-9]+}}
 
 
-define arm_aapcs_vfpcc void @double1() local_unnamed_addr {
-  br i1 undef, label %.end, label %1
-
-  %2 = fcmp nsz olt double undef, 1.000000e+00
-  %3 = select i1 %2, double -5.000000e-01, double 5.000000e-01
-  %4 = fadd nsz double undef, %3
-  %5 = fptosi double %4 to i32
-  %6 = ashr i32 %5, 4
-  %7 = icmp slt i32 %6, 0
-  br i1 %7, label %8, label %.end
-
-  tail call arm_aapcs_vfpcc void @bar()
-  br label %.end
-
-.end:
-  ret void
+define arm_aapcs_vfpcc double @double1() local_unnamed_addr {
+  %1 = fcmp nsz olt double undef, 1.000000e+00
+  %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
+  ret double %2
 }
 ; CHECK-LABEL: double1
 ; CHECK: vmov.f64 [[FPREG:d[0-9]+]], #1.000000e+00
 ; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
 
-define arm_aapcs_vfpcc void @double128() local_unnamed_addr {
-  br i1 undef, label %.end, label %1
-
-  %2 = fcmp nsz olt double undef, 128.000000e+00
-  %3 = select i1 %2, double -5.000000e-01, double 5.000000e-01
-  %4 = fadd nsz double undef, %3
-  %5 = fptosi double %4 to i32
-  %6 = ashr i32 %5, 4
-  %7 = icmp slt i32 %6, 0
-  br i1 %7, label %8, label %.end
-
-  tail call arm_aapcs_vfpcc void @bar()
-  br label %.end
-
-.end:
-  ret void
+define arm_aapcs_vfpcc double @double128() local_unnamed_addr {
+  %1 = fcmp nsz olt double undef, 128.000000e+00
+  %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
+  ret double %2
 }
 ; CHECK-LABEL: double128
-; CHECK: movs [[REGL:r[0-9]+]], #0
 ; CHECK: movs [[REGH:r[0-9]+]], #0
 ; CHECK: movt [[REGH]], #16480
+; CHECK: movs [[REGL:r[0-9]+]], #0
 ; CHECK: vmov [[FPREG:d[0-9]+]], [[REGL]], [[REGH]]
 ; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
 
-
-declare arm_aapcs_vfpcc void @bar() local_unnamed_addr
-