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[AMDGPU] Inline asm - added i16, half and i128 types support
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Authored by dfukalov on Mar 27 2018, 3:30 AM.

Details

Summary

AMDGPU inline assembler support i16, half and i128 typed variables in constraints, but they were reported as error.
Needed to fix https://github.com/RadeonOpenCompute/ROCm/issues/341,
e.g. to be able to load with global_load_dwordx4 to a 128bit integer variable

Diff Detail

Repository
rL LLVM

Event Timeline

dfukalov created this revision.Mar 27 2018, 3:30 AM
arsenm added inline comments.Mar 29 2018, 11:10 AM
lib/Target/AMDGPU/SIISelLowering.cpp
7698

Capitalize

7700–7701

Conditions backwards

test/CodeGen/AMDGPU/inlineasm-16.ll
40

Should also test packed types here?

dfukalov updated this revision to Diff 140402.Mar 30 2018, 3:51 AM
dfukalov marked an inline comment as done.

diff updated as requested

dfukalov marked 2 inline comments as done.Mar 30 2018, 3:52 AM
dfukalov added inline comments.
test/CodeGen/AMDGPU/inlineasm-16.ll
40

they are already tested in inlineasm-packed.ll

arsenm accepted this revision.Jun 8 2018, 1:14 AM

LGTM

This revision is now accepted and ready to land.Jun 8 2018, 1:14 AM
This revision was automatically updated to reflect the committed changes.