AMDGPU: Fix FP restore from being reordered with stack ops

[arsenm]

Summary

In a function, s5 is used as the frame base SGPR. Before it was
possible if there were stack operations immediately after
the call to be moved before the FP restore copy after the call.

I'm not 100% satisfied with the solution of adding an implicit
use to the ADJCALLSTACK* pseudo, but I'm not sure what would
be better.

[rampitec]

LGTM

[arsenm]

r328650

lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPU::SI_BR_UNDEF: {
     Br->getOperand(1).setIsUndef(true); // read undef SCC
     MI.eraseFromParent();
     return BB;
   }
   case AMDGPU::ADJCALLSTACKUP:
   case AMDGPU::ADJCALLSTACKDOWN: {
     const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
     MachineInstrBuilder MIB(*MF, &MI);
+
+    // Add an implicit use of the frame offset reg to prevent the restore copy
+    // inserted after the call from being reorderd after stack operations in the
+    // the caller's frame.
     MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
-        .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
+        .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
+        .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
     return BB;
   }
   case AMDGPU::SI_CALL_ISEL:
   case AMDGPU::SI_TCRETURN_ISEL: {
     const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
     const DebugLoc &DL = MI.getDebugLoc();
     unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
 

test/CodeGen/AMDGPU/call-preserved-registers.ll

 ; GCN: v_writelane_b32 v32, s34, 1
 ; GCN: v_writelane_b32 v32, s35, 2
 ; GCN: v_writelane_b32 v32, s36, 3
 ; GCN: v_writelane_b32 v32, s37, 4
 
 ; GCN: s_mov_b32 s33, s5
 ; GCN-NEXT: s_swappc_b64
 ; GCN-NEXT: s_mov_b32 s5, s33
+; GCN-NEXT: s_mov_b32 s33, s5
 ; GCN-NEXT: ;;#ASMSTART
 ; GCN-NEXT: ;;#ASMEND
-; GCN-NEXT: s_mov_b32 s33, s5
 ; GCN-NEXT: s_swappc_b64
 ; GCN-NEXT: s_mov_b32 s5, s33
 ; GCN: v_readlane_b32 s37, v32, 4
 ; GCN: v_readlane_b32 s36, v32, 3
 ; GCN: v_readlane_b32 s35, v32, 2
 ; GCN: v_readlane_b32 s34, v32, 1
 ; GCN: v_readlane_b32 s33, v32, 0
 ; GCN: s_setpc_b64