[llvm-mca] Move the logic that computes the register file usage to the BackendStatistics view.

[andreadb]

Summary

With this patch, the "instruction dispatched" event now provides information related to the number of microarchitectural registers used by the instructio in each register file. Similarly, the "instruction retired" event is able to tell how may registers are freed in each register file.

Currently, the BackendStatistics view is the only consumer of register usage/pressure information. BackendStatistics uses that info to print out a few general statistics (i.e. max number of mappings used; total mapping created).
Before this patch, the BackendStatistics was forced to query the Backend to obtain the register pressure information.

This helps removes that dependency. Now views are completely independent from the Backend.
As a consequence, it should be easier to address PR36663 and further modularize the pipeline.

Added a couple of test cases in the BtVer2 specific directory.

[RKSimon]

tools/llvm-mca/BackendStatistics.cpp

28

const auto for casts - we already know the type

40

const auto for casts - we already know the type

[andreadb]

Patch updated.

Addressed review comments.

[RKSimon]

LGTM - thanks

[andreadb]

Thanks.
Committed revision 328129.

test/tools/llvm-mca/X86/BtVer2/register-files-1.s

+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=5 -verbose -timeline < %s | FileCheck %s
+
+vaddps %xmm0, %xmm0, %xmm0
+vmulps %xmm0, %xmm0, %xmm0
+
+# CHECK: Iterations:     5
+# CHECK-NEXT: Instructions:   10
+
+# CHECK:      Dynamic Dispatch Stall Cycles:
+# CHECK-NEXT: RAT     - Register unavailable:                      0
+
+# CHECK:      Register File statistics.
+# CHECK-NEXT: Register File #0
+# CHECK-NEXT:   Total number of mappings created: 10
+# CHECK-NEXT:   Max number of mappings used:      10
+
+# CHECK: Timeline view:
+# CHECK-NEXT:                 0123456789        
+# CHECK-NEXT: Index 0123456789          01234567
+# CHECK:      [0,0] DeeeER    .    .    .    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1] D===eeER  .    .    .    . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [1,0] .D====eeeER    .    .    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1] .D=======eeER  .    .    . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [2,0] . D========eeeER    .    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1] . D===========eeER  .    . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [3,0] .  D============eeeER    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [3,1] .  D===============eeER  . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [4,0] .   D================eeeER .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [4,1] .   D===================eeER  vmulps  %xmm0, %xmm0, %xmm0

test/tools/llvm-mca/X86/BtVer2/register-files-2.s

+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -register-file-size=5 -iterations=5 -verbose -timeline < %s | FileCheck %s
+
+vaddps %xmm0, %xmm0, %xmm0
+vmulps %xmm0, %xmm0, %xmm0
+
+# CHECK: Iterations:     5
+# CHECK-NEXT: Instructions:   10
+
+# CHECK:      Dynamic Dispatch Stall Cycles:
+# CHECK-NEXT: RAT     - Register unavailable:                      13
+
+# CHECK:      Register File statistics.
+# CHECK-NEXT: Register File #0
+# CHECK-NEXT:   Total number of mappings created: 10
+# CHECK-NEXT:   Max number of mappings used:      5
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                 0123456789        
+# CHECK-NEXT: Index 0123456789          01234567
+# CHECK:      [0,0] DeeeER    .    .    .    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1] D===eeER  .    .    .    . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [1,0] .D====eeeER    .    .    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1] .D=======eeER  .    .    . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [2,0] . D========eeeER    .    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1] .    D========eeER  .    . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [3,0] .    . D========eeeER    . .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [3,1] .    .    D========eeER  . .  vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [4,0] .    .    . D========eeeER .  vaddps  %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [4,1] .    .    .    D========eeER  vmulps  %xmm0, %xmm0, %xmm0

tools/llvm-mca/Backend.h

public:
 
   const Instruction &getInstruction(unsigned Index) const {
     const auto It = Instructions.find(Index);
     assert(It != Instructions.end() && "no running instructions with index");
     assert(It->second);
     return *It->second;
   }
   void eraseInstruction(unsigned Index) { Instructions.erase(Index); }
-  unsigned getTotalRegisterMappingsCreated() const {
-    return DU->getTotalRegisterMappingsCreated();
-  }
-  unsigned getMaxUsedRegisterMappings() const {
-    return DU->getMaxUsedRegisterMappings();
-  }
 
   void addEventListener(HWEventListener *Listener);
   void notifyCycleBegin(unsigned Cycle);
   void notifyInstructionEvent(const HWInstructionEvent &Event);
   void notifyStallEvent(const HWStallEvent &Event);
   void notifyResourceAvailable(const ResourceRef &RR);
   void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
 
 } // namespace mca
 
 #endif

tools/llvm-mca/BackendStatistics.h

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/raw_ostream.h"
 #include <map>
 
 namespace mca {
 
 class BackendStatistics : public View {
-  // TODO: remove the dependency from Backend.
-  const Backend &B;
   const llvm::MCSubtargetInfo &STI;
 
   using Histogram = std::map<unsigned, unsigned>;
   Histogram DispatchGroupSizePerCycle;
   Histogram RetiredPerCycle;
   Histogram IssuedPerCycle;
 
   unsigned NumDispatched;
void updateHistograms() {
     DispatchGroupSizePerCycle[NumDispatched]++;
     IssuedPerCycle[NumIssued]++;
     RetiredPerCycle[NumRetired]++;
     NumDispatched = 0;
     NumIssued = 0;
     NumRetired = 0;
   }
 
+  // Used to track the number of physical registers used in a register file.
+  struct RegisterFileUsage {
+    unsigned TotalMappings;
+    unsigned MaxUsedMappings;
+    unsigned CurrentlyUsedMappings;
+  };
+
+  // There is one entry for each register file implemented by the processor.
+  llvm::SmallVector<RegisterFileUsage, 4> RegisterFiles;
+
   void printRetireUnitStatistics(llvm::raw_ostream &OS) const;
   void printDispatchUnitStatistics(llvm::raw_ostream &OS) const;
   void printSchedulerStatistics(llvm::raw_ostream &OS) const;
 
   void printDispatchStalls(llvm::raw_ostream &OS) const;
-  void printRATStatistics(llvm::raw_ostream &OS, unsigned Mappings,
-                          unsigned MaxUsedMappings) const;
+  void printRATStatistics(llvm::raw_ostream &OS) const;
   void printRCUStatistics(llvm::raw_ostream &OS, const Histogram &Histogram,
                           unsigned Cycles) const;
   void printDispatchUnitUsage(llvm::raw_ostream &OS, const Histogram &Stats,
                               unsigned Cycles) const;
   void printIssuePerCycle(const Histogram &IssuePerCycle,
                           unsigned TotalCycles) const;
   void printSchedulerUsage(llvm::raw_ostream &OS,
                            const llvm::MCSchedModel &SM) const;
 
 public:
-  BackendStatistics(const Backend &backend, const llvm::MCSubtargetInfo &sti)
-      : B(backend), STI(sti), NumDispatched(0), NumIssued(0), NumRetired(0),
-        NumCycles(0), HWStalls(HWStallEvent::LastGenericEvent) {}
+  BackendStatistics(const llvm::MCSubtargetInfo &sti)
+      : STI(sti), NumDispatched(0), NumIssued(0), NumRetired(0),
+        NumCycles(0), HWStalls(HWStallEvent::LastGenericEvent),
+        // TODO: The view currently assumes a single register file. This will
+        // change in future.
+        RegisterFiles(1) {}
 
   void onInstructionEvent(const HWInstructionEvent &Event) override;
 
   void onCycleBegin(unsigned Cycle) override { NumCycles++; }
 
   void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
 
   void onStallEvent(const HWStallEvent &Event) override {
     if (Event.Type < HWStallEvent::LastGenericEvent)
       HWStalls[Event.Type]++;
   }
 
   // Increases the number of used scheduler queue slots of every buffered
   // resource in the Buffers set.
   void onReservedBuffers(llvm::ArrayRef<unsigned> Buffers) override;
 
   // Decreases by one the number of used scheduler queue slots of every
   // buffered resource in the Buffers set.
   void onReleasedBuffers(llvm::ArrayRef<unsigned> Buffers) override;
 
   void printView(llvm::raw_ostream &OS) const override {
     printDispatchStalls(OS);
-    printRATStatistics(OS, B.getTotalRegisterMappingsCreated(),
-                       B.getMaxUsedRegisterMappings());
+    printRATStatistics(OS);
     printDispatchUnitStatistics(OS);
     printSchedulerStatistics(OS);
     printRetireUnitStatistics(OS);
-
     printSchedulerUsage(OS, STI.getSchedModel());
   }
 };
 } // namespace mca
 
 #endif

tools/llvm-mca/BackendStatistics.cpp

 #include "llvm/Support/Format.h"
 
 using namespace llvm;
 
 namespace mca {
 
 void BackendStatistics::onInstructionEvent(const HWInstructionEvent &Event) {
   switch (Event.Type) {
-  case HWInstructionEvent::Retired:
+  default:
+    break;
+  case HWInstructionEvent::Retired: {
+    const auto &RE = static_cast<const HWInstructionRetiredEvent &>(Event);
+    for (unsigned I = 0, E = RegisterFiles.size(); I < E; ++I)
+      RegisterFiles[I].CurrentlyUsedMappings -= RE.FreedPhysRegs[I];
+
     ++NumRetired;
     break;
+  }
   case HWInstructionEvent::Issued:
     ++NumIssued;
     break;
-  case HWInstructionEvent::Dispatched:
+  case HWInstructionEvent::Dispatched: {
+    const auto &DE = static_cast<const HWInstructionDispatchedEvent &>(Event);
+    for (unsigned I = 0, E = RegisterFiles.size(); I < E; ++I) {
+      RegisterFileUsage &RFU = RegisterFiles[I];
+      unsigned NumUsedPhysRegs = DE.UsedPhysRegs[I];
+      RFU.CurrentlyUsedMappings += NumUsedPhysRegs;
+      RFU.TotalMappings += NumUsedPhysRegs;
+      RFU.MaxUsedMappings =
+          std::max(RFU.MaxUsedMappings, RFU.CurrentlyUsedMappings);
+    }
+
     ++NumDispatched;
-    break;
-  default:
-    break;
+  }
   }
 }
 
 void BackendStatistics::onReservedBuffers(ArrayRef<unsigned> Buffers) {
   for (const unsigned Buffer : Buffers) {
     if (BufferedResources.find(Buffer) != BufferedResources.end()) {
       BufferUsage &BU = BufferedResources[Buffer];
       BU.SlotsInUse++;
TempStream << " " << Entry.first << ",          " << Entry.second << "  ("
                << format("%.1f", ((double)Entry.second / NumCycles) * 100)
                << "%)\n";
   }
 
   TempStream.flush();
   OS << Buffer;
 }
 
-void BackendStatistics::printRATStatistics(raw_ostream &OS,
-                                           unsigned TotalMappings,
-                                           unsigned MaxUsedMappings) const {
+void BackendStatistics::printRATStatistics(raw_ostream &OS) const {
   std::string Buffer;
   raw_string_ostream TempStream(Buffer);
-  TempStream << "\n\nRegister Alias Table:";
-  TempStream << "\nTotal number of mappings created: " << TotalMappings;
-  TempStream << "\nMax number of mappings used:      " << MaxUsedMappings
-             << '\n';
+
+  TempStream << "\n\nRegister File statistics.";
+  for (unsigned I = 0, E = RegisterFiles.size(); I < E; ++I) {
+    const RegisterFileUsage &RFU = RegisterFiles[I];
+    TempStream << "\nRegister File #" << I;
+    TempStream << "\n  Total number of mappings created: " << RFU.TotalMappings;
+    TempStream << "\n  Max number of mappings used:      "
+               << RFU.MaxUsedMappings;
+  }
+
   TempStream.flush();
   OS << Buffer;
 }
 
 void BackendStatistics::printDispatchStalls(raw_ostream &OS) const {
   std::string Buffer;
   raw_string_ostream TempStream(Buffer);
   TempStream << "\n\nDynamic Dispatch Stall Cycles:\n";

tools/llvm-mca/Dispatch.h

class RegisterFile {
   // allocated during the execution.
   struct RegisterMappingTracker {
     // Total number of register mappings that are available for register
     // renaming. A value of zero for this field means: this register file has
     // an unbounded number of registers.
     const unsigned TotalMappings;
     // Number of mappings that are currently in use.
     unsigned NumUsedMappings;
-    // Maximum number of register mappings used.
-    unsigned MaxUsedMappings;
-    // Total number of mappings allocated during the entire execution.
-    unsigned TotalMappingsCreated;
 
     RegisterMappingTracker(unsigned NumMappings)
-        : TotalMappings(NumMappings), NumUsedMappings(0), MaxUsedMappings(0),
-          TotalMappingsCreated(0) {}
+        : TotalMappings(NumMappings), NumUsedMappings(0) {}
   };
 
   // This is where information related to the various register files is kept.
   // This set always contains at least one register file at index #0. That
   // register file "sees" all the physical registers declared by the target, and
   // (by default) it allows an unbound number of mappings.
   // Users can limit the number of mappings that can be created by register file
   // #0 through the command line flag `-register-file-size`.
class RegisterFile {
   // The list of register classes is then converted by the tablegen backend into
   // a list of register class indices. That list, along with the number of
   // available mappings, is then used to create a new RegisterMappingTracker.
   void addRegisterFile(llvm::ArrayRef<unsigned> RegisterClasses,
                        unsigned NumTemps);
 
   // Allocates a new register mapping in every register file specified by the
   // register file mask. This method is called from addRegisterMapping.
-  void createNewMappings(unsigned RegisterFileMask);
+  void createNewMappings(unsigned RegisterFileMask,
+                         llvm::MutableArrayRef<unsigned> UsedPhysRegs);
 
   // Removes a previously allocated mapping from each register file in the
   // RegisterFileMask set. This method is called from invalidateRegisterMapping.
-  void removeMappings(unsigned RegisterFileMask);
+  void removeMappings(unsigned RegisterFileMask,
+                      llvm::MutableArrayRef<unsigned> FreedPhysRegs);
 
 public:
   RegisterFile(const llvm::MCRegisterInfo &mri, unsigned TempRegs = 0)
       : MRI(mri), RegisterMappings(MRI.getNumRegs(), {nullptr, 0U}) {
     addRegisterFile({}, TempRegs);
     // TODO: teach the scheduling models how to specify multiple register files.
   }
 
   // Creates a new register mapping for RegID.
   // This reserves a microarchitectural register in every register file that
   // contains RegID.
-  void addRegisterMapping(WriteState &WS);
+  void addRegisterMapping(WriteState &WS,
+                          llvm::MutableArrayRef<unsigned> UsedPhysRegs);
 
   // Invalidates register mappings associated to the input WriteState object.
   // This releases previously allocated mappings for the physical register
   // associated to the WriteState.
-  void invalidateRegisterMapping(const WriteState &WS);
+  void invalidateRegisterMapping(const WriteState &WS,
+                                 llvm::MutableArrayRef<unsigned> FreedPhysRegs);
 
   // Checks if there are enough microarchitectural registers in the register
   // files.  Returns a "response mask" where each bit is the response from a
   // RegisterMappingTracker.
   // For example: if all register files are available, then the response mask
   // is a bitmask of all zeroes. If Instead register file #1 is not available,
   // then the response mask is 0b10.
   unsigned isAvailable(llvm::ArrayRef<unsigned> Regs) const;
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Writes,
                      unsigned RegID) const;
   void updateOnRead(ReadState &RS, unsigned RegID);
-  unsigned getMaxUsedRegisterMappings(unsigned RegisterFileIndex) const {
-    assert(RegisterFileIndex < getNumRegisterFiles() &&
-           "Invalid register file index!");
-    return RegisterFiles[RegisterFileIndex].MaxUsedMappings;
-  }
-  unsigned getTotalRegisterMappingsCreated(unsigned RegisterFileIndex) const {
-    assert(RegisterFileIndex < getNumRegisterFiles() &&
-           "Invalid register file index!");
-    return RegisterFiles[RegisterFileIndex].TotalMappingsCreated;
-  }
+
   unsigned getNumRegisterFiles() const { return RegisterFiles.size(); }
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 /// \brief tracks which instructions are in-flight (i.e. dispatched but not
class DispatchUnit {
   std::unique_ptr<RetireControlUnit> RCU;
   Backend *Owner;
 
   bool checkRAT(unsigned Index, const Instruction &Desc);
   bool checkRCU(unsigned Index, const InstrDesc &Desc);
   bool checkScheduler(unsigned Index, const InstrDesc &Desc);
 
   void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
-  void notifyInstructionDispatched(unsigned IID);
+  void notifyInstructionDispatched(unsigned IID, llvm::ArrayRef<unsigned> UsedPhysRegs);
 
 public:
   DispatchUnit(Backend *B, const llvm::MCRegisterInfo &MRI,
                unsigned MicroOpBufferSize, unsigned RegisterFileSize,
                unsigned MaxRetirePerCycle, unsigned MaxDispatchWidth,
                Scheduler *Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
         CarryOver(0U), SC(Sched),
public:
 
   unsigned dispatch(unsigned IID, Instruction *NewInst,
                     const llvm::MCSubtargetInfo &STI);
 
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
                      unsigned RegID) const {
     return RAT->collectWrites(Vec, RegID);
   }
-  unsigned getMaxUsedRegisterMappings(unsigned RegFileIndex = 0) const {
-    return RAT->getMaxUsedRegisterMappings(RegFileIndex);
-  }
-  unsigned getTotalRegisterMappingsCreated(unsigned RegFileIndex = 0) const {
-    return RAT->getTotalRegisterMappingsCreated(RegFileIndex);
-  }
 
   void cycleEvent(unsigned Cycle) {
     RCU->cycleEvent();
     AvailableEntries =
         CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
     CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
   }
 

tools/llvm-mca/Dispatch.cpp

if (RegisterClasses.empty()) {
     for (const unsigned RegClassIndex : RegisterClasses) {
       const MCRegisterClass &RC = MRI.getRegClass(RegClassIndex);
       for (const MCPhysReg Reg : RC)
         RegisterMappings[Reg].second |= 1U << RegisterFileIndex;
     }
   }
 }
 
-void RegisterFile::createNewMappings(unsigned RegisterFileMask) {
+void RegisterFile::createNewMappings(unsigned RegisterFileMask,
+                                     MutableArrayRef<unsigned> UsedPhysRegs) {
   assert(RegisterFileMask && "RegisterFileMask cannot be zero!");
   // Notify each register file that contains RegID.
   do {
     unsigned NextRegisterFile = llvm::PowerOf2Floor(RegisterFileMask);
     unsigned RegisterFileIndex = llvm::countTrailingZeros(NextRegisterFile);
     RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex];
     RMT.NumUsedMappings++;
-    RMT.MaxUsedMappings = std::max(RMT.MaxUsedMappings, RMT.NumUsedMappings);
-    RMT.TotalMappingsCreated++;
+    UsedPhysRegs[RegisterFileIndex]++;
     RegisterFileMask ^= NextRegisterFile;
   } while (RegisterFileMask);
 }
 
-void RegisterFile::removeMappings(unsigned RegisterFileMask) {
+void RegisterFile::removeMappings(unsigned RegisterFileMask,
+                                  MutableArrayRef<unsigned> FreedPhysRegs) {
   assert(RegisterFileMask && "RegisterFileMask cannot be zero!");
   // Notify each register file that contains RegID.
   do {
     unsigned NextRegisterFile = llvm::PowerOf2Floor(RegisterFileMask);
     unsigned RegisterFileIndex = llvm::countTrailingZeros(NextRegisterFile);
     RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex];
     assert(RMT.NumUsedMappings);
     RMT.NumUsedMappings--;
+    FreedPhysRegs[RegisterFileIndex]++;
     RegisterFileMask ^= NextRegisterFile;
   } while (RegisterFileMask);
 }
 
-void RegisterFile::addRegisterMapping(WriteState &WS) {
+void RegisterFile::addRegisterMapping(WriteState &WS,
+                                      MutableArrayRef<unsigned> UsedPhysRegs) {
   unsigned RegID = WS.getRegisterID();
   assert(RegID && "Adding an invalid register definition?");
 
   RegisterMapping &Mapping = RegisterMappings[RegID];
   Mapping.first = &WS;
   for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I)
     RegisterMappings[*I].first = &WS;
 
-  createNewMappings(Mapping.second);
+  createNewMappings(Mapping.second, UsedPhysRegs);
+
   // If this is a partial update, then we are done.
   if (!WS.fullyUpdatesSuperRegs())
     return;
 
   for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I)
     RegisterMappings[*I].first = &WS;
 }
 
-void RegisterFile::invalidateRegisterMapping(const WriteState &WS) {
+void RegisterFile::invalidateRegisterMapping(
+    const WriteState &WS, MutableArrayRef<unsigned> FreedPhysRegs) {
   unsigned RegID = WS.getRegisterID();
   bool ShouldInvalidateSuperRegs = WS.fullyUpdatesSuperRegs();
 
   assert(RegID != 0 && "Invalidating an already invalid register?");
   assert(WS.getCyclesLeft() != -512 &&
          "Invalidating a write of unknown cycles!");
   assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!");
   RegisterMapping &Mapping = RegisterMappings[RegID];
   if (!Mapping.first)
     return;
 
-  removeMappings(Mapping.second);
+  removeMappings(Mapping.second, FreedPhysRegs);
 
   if (Mapping.first == &WS)
     Mapping.first = nullptr;
 
   for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I)
     if (RegisterMappings[*I].first == &WS)
       RegisterMappings[*I].first = nullptr;
 
for (unsigned I = 0, E = MRI.getNumRegs(); I < E; ++I) {
     else
       dbgs() << "(null)\n";
   }
 
   for (unsigned I = 0, E = getNumRegisterFiles(); I < E; ++I) {
     dbgs() << "Register File #" << I;
     const RegisterMappingTracker &RMT = RegisterFiles[I];
     dbgs() << "\n  TotalMappings:        " << RMT.TotalMappings
-           << "\n  TotalMappingsCreated: " << RMT.TotalMappingsCreated
-           << "\n  MaxUsedMappings:      " << RMT.MaxUsedMappings
            << "\n  NumUsedMappings:      " << RMT.NumUsedMappings << '\n';
   }
 }
 #endif
 
 // Reserves a number of slots, and returns a new token.
 unsigned RetireControlUnit::reserveSlot(unsigned Index, unsigned NumMicroOps) {
   assert(isAvailable(NumMicroOps));
   unsigned NormalizedQuantity =
       std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
   // Zero latency instructions may have zero mOps. Artificially bump this
   // value to 1. Although zero latency instructions don't consume scheduler
   // resources, they still consume one slot in the retire queue.
   NormalizedQuantity = std::max(NormalizedQuantity, 1U);
   unsigned TokenID = NextAvailableSlotIdx;
   Queue[NextAvailableSlotIdx] = {Index, NormalizedQuantity, false};
   NextAvailableSlotIdx += NormalizedQuantity;
   NextAvailableSlotIdx %= Queue.size();
   AvailableSlots -= NormalizedQuantity;
   return TokenID;
 }
 
-void DispatchUnit::notifyInstructionDispatched(unsigned Index) {
+void DispatchUnit::notifyInstructionDispatched(
+    unsigned Index, ArrayRef<unsigned> UsedRegs) {
   DEBUG(dbgs() << "[E] Instruction Dispatched: " << Index << '\n');
-  Owner->notifyInstructionEvent(
-      HWInstructionEvent(HWInstructionEvent::Dispatched, Index));
+  Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(Index, UsedRegs));
 }
 
 void DispatchUnit::notifyInstructionRetired(unsigned Index) {
   DEBUG(dbgs() << "[E] Instruction Retired: " << Index << '\n');
-  Owner->notifyInstructionEvent(
-      HWInstructionEvent(HWInstructionEvent::Retired, Index));
-
   const Instruction &IS = Owner->getInstruction(Index);
+  SmallVector<unsigned, 4> FreedRegs(RAT->getNumRegisterFiles());
   for (const std::unique_ptr<WriteState> &WS : IS.getDefs())
-    RAT->invalidateRegisterMapping(*WS.get());
+    RAT->invalidateRegisterMapping(*WS.get(), FreedRegs);
 
+  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(Index, FreedRegs));
   Owner->eraseInstruction(Index);
 }
 
 void RetireControlUnit::cycleEvent() {
   if (isEmpty())
     return;
 
   unsigned NumRetired = 0;
if (NumMicroOps > DispatchWidth) {
     AvailableEntries -= NumMicroOps;
   }
 
   // Update RAW dependencies.
   for (std::unique_ptr<ReadState> &RS : NewInst->getUses())
     updateRAWDependencies(*RS, STI);
 
   // Allocate new mappings.
+  SmallVector<unsigned, 4> RegisterFiles(RAT->getNumRegisterFiles());
   for (std::unique_ptr<WriteState> &WS : NewInst->getDefs())
-    RAT->addRegisterMapping(*WS);
+    RAT->addRegisterMapping(*WS, RegisterFiles);
 
   // Set the cycles left before the write-back stage.
   const InstrDesc &D = NewInst->getDesc();
   NewInst->setCyclesLeft(D.MaxLatency);
 
   // Reserve slots in the RCU.
   unsigned RCUTokenID = RCU->reserveSlot(IID, NumMicroOps);
   NewInst->setRCUTokenID(RCUTokenID);
-  notifyInstructionDispatched(IID);
+  notifyInstructionDispatched(IID, RegisterFiles);
 
   SC->scheduleInstruction(IID, *NewInst);
   return RCUTokenID;
 }
 
 #ifndef NDEBUG
 void DispatchUnit::dump() const {
   RAT->dump();
   RCU->dump();
 }
 #endif
 
 } // namespace mca

tools/llvm-mca/HWEventListener.h

public:
   HWInstructionIssuedEvent(
       unsigned Index, llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UR)
       : HWInstructionEvent(HWInstructionEvent::Issued, Index),
         UsedResources(UR) {}
 
   llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UsedResources;
 };
 
+class HWInstructionDispatchedEvent : public HWInstructionEvent {
+public:
+  HWInstructionDispatchedEvent(unsigned Index, llvm::ArrayRef<unsigned> Regs)
+      : HWInstructionEvent(HWInstructionEvent::Dispatched, Index),
+        UsedPhysRegs(Regs) {}
+  // Number of physical register allocated for this instruction. There is one
+  // entry per register file.
+  llvm::ArrayRef<unsigned> UsedPhysRegs;
+};
+
+class HWInstructionRetiredEvent : public HWInstructionEvent {
+public:
+  HWInstructionRetiredEvent(unsigned Index, llvm::ArrayRef<unsigned> Regs)
+      : HWInstructionEvent(HWInstructionEvent::Retired, Index),
+        FreedPhysRegs(Regs) {}
+  // Number of register writes that have been architecturally committed. There
+  // is one entry per register file.
+  llvm::ArrayRef<unsigned> FreedPhysRegs;
+};
+
 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
 // resources.
 class HWStallEvent {
 public:
   enum GenericEventType {
     Invalid = 0,
     // Generic stall events generated by the DispatchUnit.
     RegisterFileStall,

tools/llvm-mca/llvm-mca.cpp

std::unique_ptr<mca::BackendPrinter> Printer =
       llvm::make_unique<mca::BackendPrinter>(*B);
 
   std::unique_ptr<mca::SummaryView> SV =
       llvm::make_unique<mca::SummaryView>(*STI, *MCII, *S, *IP, Width);
   Printer->addView(std::move(SV));
 
   if (PrintModeVerbose) {
     std::unique_ptr<mca::BackendStatistics> BS =
-        llvm::make_unique<mca::BackendStatistics>(*B, *STI);
+        llvm::make_unique<mca::BackendStatistics>(*STI);
     Printer->addView(std::move(BS));
   }
 
   std::unique_ptr<mca::ResourcePressureView> RPV =
       llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, *S);
   Printer->addView(std::move(RPV));
 
   if (PrintTimelineView) {