AMDGPU: Don't leave dead illegal VGPR->SGPR copies

[arsenm]

Summary

Normally DCE kills these, but at -O0 these get left behind
leaving suspicious looking illegal copies.

Replace with IMPLICIT_DEF to avoid iterator issues.

[rampitec]

LGTM

[arsenm]

r327842

lib/Target/AMDGPU/SIInstrInfo.cpp

if (HasDst) {
         // copies interfere with the heuristics MachineSink uses to decide
         // whether or not to split a critical edge.  Since the pass assumes
         // that copies will end up as machine instructions and not be
         // eliminated.
         addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
         MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
         MRI.clearKillFlags(Inst.getOperand(1).getReg());
         Inst.getOperand(0).setReg(DstReg);
+
+        // Make sure we don't leave around a dead VGPR->SGPR copy. Normally
+        // these are deleted later, but at -O0 it would leave a suspicious
+        // looking illegal copy of an undef register.
+        for (unsigned I = Inst.getNumOperands() - 1; I != 0; --I)
+          Inst.RemoveOperand(I);
+        Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
         continue;
       }
 
       NewDstReg = MRI.createVirtualRegister(NewDstRC);
       MRI.replaceRegWith(DstReg, NewDstReg);
     }
 
     // Legalize the operands

test/CodeGen/AMDGPU/control-flow-fastregalloc.ll

 
 ; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
 
 ; GCN: mask branch [[ENDIF:BB[0-9]+_[0-9]+]]
 
 ; GCN: {{^}}BB{{[0-9]+}}_1: ; %if
 ; GCN: s_mov_b32 m0, -1
 ; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]
-; GCN: s_waitcnt lgkmcnt(0)
 ; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
+; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
+
 
 ; Spill val register
 ; GCN: v_add_i32_e32 [[VAL:v[0-9]+]], vcc, [[LOAD1]], [[RELOAD_LOAD0]]
 ; GCN: buffer_store_dword [[VAL]], off, s[0:3], s7 offset:[[VAL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
 
 ; VMEM: [[ENDIF]]:
+
 ; Reload and restore exec mask
-; VGPR: s_waitcnt lgkmcnt(0)
 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
 
 
 
 ; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC_LO:[0-9]+]], off, s[0:3], s7 offset:4 ; 4-byte Folded Reload
 ; VMEM: s_waitcnt vmcnt(0)
 ; VMEM: v_readfirstlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC_LO]]

test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir

 # RUN: llc -march=amdgcn -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN
 
---- |
-  define amdgpu_kernel void @phi_visit_order() { ret void }
+---
 
 name: phi_visit_order
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32_xm0 }
   - { id: 1, class: sreg_64 }
   - { id: 2, class: sreg_32_xm0 }
   - { id: 7, class: vgpr_32 }
body: |
 
   bb.2:
     SI_END_CF %1, implicit-def $exec, implicit-def $scc, implicit $exec
     %11 = S_MOV_B32 1
     %2 = S_ADD_I32 %0, %11, implicit-def $scc
     S_BRANCH %bb.1
 
 ...
+
+---
+
+# GCN-LABEL: name: dead_illegal_virtreg_copy
+# GCN: %0:vgpr_32 = COPY $vgpr0
+# GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
+# GCN: S_ENDPGM implicit %0
+
+name: dead_illegal_virtreg_copy
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    %0:vgpr_32 = COPY $vgpr0
+    %1:sreg_32_xm0 = COPY %0
+    S_ENDPGM implicit %1
+...
+
 ---
+
+# GCN-LABEL: name: dead_illegal_physreg_copy
+# GCN %2:vgpr_32 = COPY $vgpr0
+# GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
+# GCN: S_ENDPGM implicit %2
+
+name: dead_illegal_physreg_copy
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    %0:sreg_32_xm0 = COPY $vgpr0
+    %1:sreg_32_xm0 = COPY %0
+    S_ENDPGM implicit %1
+...