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[Power9]Legalize and emit code for quad-precision add/div/mul/sub
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Authored by lei on Mar 14 2018, 10:43 PM.

Details

Summary

This is the first patch of several to come to add support for quad-precision floating point operations.

Legalize and emit code for quad-precision floating point operations:

  • xsaddqp
  • xssubqp
  • xsdivqp
  • xsmulqp

Diff Detail

Repository
rL LLVM

Event Timeline

lei created this revision.Mar 14 2018, 10:43 PM
nemanjai accepted this revision.Mar 16 2018, 5:24 PM

LGTM. Please add the requested test case on the commit - no need for an additional review.

lib/Target/PowerPC/PPCInstrVSX.td
2898 ↗(On Diff #138492)

Can you please add an additional test case for this. We want to make sure no future patches break it. Something along these lines should suffice:

define void @test(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
entry:
  %add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4
  %0 = bitcast i8* %add.ptr to fp128*
  %1 = load fp128, fp128* %0, align 16
  %2 = bitcast fp128* %PtrF to i8*
  %add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8
  %3 = bitcast i8* %add.ptr1 to fp128*
  store fp128 %1, fp128* %3, align 16
  ret void
}

We need to make sure we emit LXVX and STXVX here rather than their D-Form analogs.

This revision is now accepted and ready to land.Mar 16 2018, 5:24 PM
This revision was automatically updated to reflect the committed changes.