[CodeGenPrepare] Respect endianness in splitMergedValStore.

[jonpa]

Summary

splitMergedValStore will split a store into two if target prefers this, or if -force-split-store is passed.

There is currently no check for endianness when this is done, which results in wrong code. This patch adds handling for this along with a test case.

[efriedma]

LGTM

[jonpa]

r327375.

lib/CodeGen/CodeGenPrepare.cpp

static bool splitMergedValStore(StoreInst &SI, const DataLayout &DL,
 
   // If LValue/HValue is a bitcast in another BB, create a new one in current
   // BB so it may be merged with the splitted stores by dag combiner.
   if (LBC && LBC->getParent() != SI.getParent())
     LValue = Builder.CreateBitCast(LBC->getOperand(0), LBC->getType());
   if (HBC && HBC->getParent() != SI.getParent())
     HValue = Builder.CreateBitCast(HBC->getOperand(0), HBC->getType());
 
+  bool IsLE = SI.getModule()->getDataLayout().isLittleEndian();
   auto CreateSplitStore = [&](Value *V, bool Upper) {
     V = Builder.CreateZExtOrBitCast(V, SplitStoreType);
     Value *Addr = Builder.CreateBitCast(
         SI.getOperand(1),
         SplitStoreType->getPointerTo(SI.getPointerAddressSpace()));
-    if (Upper)
+    if ((IsLE && Upper) || (!IsLE && !Upper))
       Addr = Builder.CreateGEP(
           SplitStoreType, Addr,
           ConstantInt::get(Type::getInt32Ty(SI.getContext()), 1));
     Builder.CreateAlignedStore(
         V, Addr, Upper ? SI.getAlignment() / 2 : SI.getAlignment());
   };
 
   CreateSplitStore(LValue, false);

test/CodeGen/SystemZ/codegenprepare-splitstore.ll

+; Test that CodeGenPrepare respects endianness when splitting a store.
+;
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -force-split-store < %s  | FileCheck %s
+
+define void @fun(i16* %Src, i16* %Dst) {
+; CHECK-LABEL: # %bb.0:
+; CHECK:       lh   %r0, 0(%r2)
+; CHECK-NEXT:  stc  %r0, 1(%r3)
+; CHECK-NEXT:  srl  %r0, 8
+; CHECK-NEXT:  stc  %r0, 0(%r3)
+; CHECK-NEXT:  br   %r14
+  %1 = load i16, i16* %Src
+  %2 = trunc i16 %1 to i8
+  %3 = lshr i16 %1, 8
+  %4 = trunc i16 %3 to i8
+  %5 = zext i8 %2 to i16
+  %6 = zext i8 %4 to i16
+  %7 = shl nuw i16 %6, 8
+  %8 = or i16 %7, %5
+  store i16 %8, i16* %Dst
+  ret void
+}