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[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
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Authored by aivchenk on Mar 12 2018, 10:09 AM.

Details

Summary
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for                                                                                  
shift instructions : shift gpr, shift imm, shift 1.                                                                                  
Currently GlobalIsel TableGen generate patterns for                                                                                  
shift imm and shift 1, but with shiftCount i8.                                                                                       
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments                                                                                   
has the same type, so for now only shift i8 can use                                                                                  
auto generated TableGen patterns.                                                                                                    
                                                                                                                                     
The support of G_SHL/G_ASHR enables tryCombineSExt                                                                                   
from LegalizationArtifactCombiner.h to hit, which                                                                                    
results in different legalization for the following tests:                                                                           
    LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll                                                                                     
    LLVM :: CodeGen/X86/GlobalISel/gep.ll                                                                                            
    LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir                                                                           
                                                                                                                                     
-; X64-NEXT:    movsbl %dil, %eax                                                                                                    
+; X64-NEXT:    movl $24, %ecx                                                                                                       
+; X64-NEXT:    # kill: def $cl killed $ecx                                                                                          
+; X64-NEXT:    shll %cl, %edi                                                                                                       
+; X64-NEXT:    movl $24, %ecx                                                                                                       
+; X64-NEXT:    # kill: def $cl killed $ecx                                                                                          
+; X64-NEXT:    sarl %cl, %edi                                                                                                       
+; X64-NEXT:    movl %edi, %eax                                                                                                      
                                                                                                                                     
..which is not optimal and should be addressed later.

Rework of the patch by Igor Breger:
https://reviews.llvm.org/D38219

Diff Detail

Repository
rL LLVM

Event Timeline

aivchenk created this revision.Mar 12 2018, 10:09 AM
igorb added a comment.Mar 13 2018, 2:09 AM

Hi,
Could you please add more context in this patch also (svn diff --diff-cmd=diff -x -U999999)
Thanks

Right, sorry about that. One sec

aivchenk updated this revision to Diff 138140.Mar 13 2018, 2:14 AM

added context

igorb accepted this revision.Mar 14 2018, 3:57 AM

LGTM

This revision is now accepted and ready to land.Mar 14 2018, 3:57 AM
This revision was automatically updated to reflect the committed changes.