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Differential D44332

AMDGPU: Fix crash when constant folding with physreg operand
ClosedPublic

Authored by arsenm on Mar 9 2018, 2:59 PM.

Details

Reviewers
rampitec

Diff Detail

Event Timeline

arsenm created this revision.Mar 9 2018, 2:59 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptMar 9 2018, 2:59 PM
rampitec accepted this revision.Mar 9 2018, 3:03 PM

LGTM

This revision is now accepted and ready to land.Mar 9 2018, 3:03 PM
arsenm closed this revision.Mar 10 2018, 8:08 AM

r327209

Revision Contents

PathSize
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
27 lines

Diff 137848

lib/Target/AMDGPU/SIFoldOperands.cpp

Show First 20 Lines • Show All 465 Lines • ▼ Show 20 Linesstatic void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
MI.setDesc(NewDesc); MI.setDesc(NewDesc);
stripExtraCopyOperands(MI); stripExtraCopyOperands(MI);
} }
static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI, static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
MachineOperand &Op) { MachineOperand &Op) {
if (Op.isReg()) { if (Op.isReg()) {
// If this has a subregister, it obviously is a register source. // If this has a subregister, it obviously is a register source.
if (Op.getSubReg() != AMDGPU::NoSubRegister) if (Op.getSubReg() != AMDGPU::NoSubRegister ||
!TargetRegisterInfo::isVirtualRegister(Op.getReg()))
return &Op; return &Op;
MachineInstr *Def = MRI.getVRegDef(Op.getReg()); MachineInstr *Def = MRI.getVRegDef(Op.getReg());
if (Def && Def->isMoveImmediate()) { if (Def && Def->isMoveImmediate()) {
MachineOperand &ImmSrc = Def->getOperand(1); MachineOperand &ImmSrc = Def->getOperand(1);
if (ImmSrc.isImm()) if (ImmSrc.isImm())
return &ImmSrc; return &ImmSrc;
} }
▲ Show 20 Lines • Show All 505 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir

Show First 20 Lines • Show All 798 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec %0 = V_MOV_B32_e32 0, implicit $exec
%2 = V_XOR_B32_e64 killed %0, undef %1, implicit $exec %2 = V_XOR_B32_e64 killed %0, undef %1, implicit $exec
FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM S_ENDPGM
... ...
---
# Make sure there is no crash if one of the operands is a physical register
# GCN-LABEL: name: constant_fold_physreg_op{{$}}
# GCN: %3:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
name: constant_fold_physreg_op
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.3
liveins: $vgpr0, $sgpr4_sgpr5
%19:sreg_64 = IMPLICIT_DEF
%0:sreg_64 = SI_IF killed %19, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
%6:sreg_64 = S_MOV_B64 0
%7:sreg_64 = S_AND_B64 $exec, killed %6, implicit-def dead $scc
$vcc = COPY %7
bb.3:
liveins: $vcc
SI_END_CF %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM implicit $vcc
...