[AArch64] Fix UB about shift amount exceeds data bit-width

[weimingz]

Summary

Fixes an UB caught by sanitizer. The shift amount might be larger than 32 so the operand should be 1ULL.
In this patch, we replace the original expression with existing API with uint64_t type.

[rengolin]

Nice! LGTM, thanks!

llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
   uint64_t AndImm = 0;
   if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
     return false;
 
   const SDNode *Op0 = N->getOperand(0).getNode();
 
   // Because of simplify-demanded-bits in DAGCombine, the mask may have been
   // simplified. Try to undo that
-  AndImm |= (1 << NumberOfIgnoredLowBits) - 1;
+  AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);
 
   // The immediate is a mask of the low bits iff imm & (imm+1) == 0
   if (AndImm & (AndImm + 1))
     return false;
 
   bool ClampMSB = false;
   uint64_t SrlImm = 0;
   // Handle the SRL + ANY_EXTEND case.