[X86] Describe wbnoinvd instruction

[GBuella]

Summary

Similar to the wbinvd instruction, except this
one does not invalidate caches. Ring 0 only.
The encoding matches a wbinvd instruction with
an F3 prefix.

[craig.topper]

Can you add a disassembler test as well?

lib/Support/Host.cpp

1222

Can you line up the '=' in the clzero line above? This way it's consistent with the HasExtLeaf1 and HasLeaf7 code where everything is nicely lined up.

lib/Target/X86/X86.td

751

Isn't this instruction only on icelake server? Not icelake desktop/mobile. We may need to separate a icelake server like we do skylake and skylake-avx512.

[GBuella]

Removed wbinvd related code.
Added Ice Lake Server architecture.
Added disassembly tests.

[craig.topper]

LGTM other than that one comment.

include/llvm/IR/IntrinsicsX86.td

6426

This comment is misleading. WBNOINVD writes back the entire cache hierarchy not just a cache line.

[GBuella]

Fixed the comment on "cache line write back"

[GBuella]

Rebased the patch.
Added x86-16 tests.

[craig.topper]

lib/Target/X86/X86InstrSystem.td

488

Do you know if 0xf3 0x0f 0x09 behaves as wbinvd on older processors. Or was 0xf3 0x0f 0x09 a #UD fault on previous CPUs? Wondering whether WBINVD should have TB or PS. I'm guess since wbinvd is super old the prefixes have always been ignored, but I'm not sure.

[GBuella]

lib/Target/X86/X86InstrSystem.td

488

Well, the ISA says about the REP prefix:
"Use these prefixes only with string and I/O instructions (MOVS, CMPS, SCAS, LODS, STOS, INS, and OUTS). Use of repeat prefixes and/or undefined opcodes with other Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable behavior."

So, one should not use the 0xf3 prefix with winvd.

On the other hand, this still doesn't tell us whether it would be #UD on older CPUs, or ignored.

Since the disassembler I think doesn't use flags like -mwbnoinvd, I guess we can modify wbinvd's description to mention PS.

[GBuella]

Disallow 0xf3 prefix with wbinvd.

[craig.topper]

Based on the discussion here https://patchwork.kernel.org/patch/10175159/ I think 0xf3 + wbinvd was previously equivalent to wbinvd so I think TB was correct.

[GBuella]

In D43816#1064590, @craig.topper wrote:

Based on the discussion here https://patchwork.kernel.org/patch/10175159/ I think 0xf3 + wbinvd was previously equivalent to wbinvd so I think TB was correct.

Right, but the disassembler is still going to recognize it as wbnoinvd.

[craig.topper]

Changing it from TB to PS will affect the behavior of 0xf2 0x0f 0x09 and 0x66 0x0f 0x09. Which I think we still want to disassemble to just wbinvd.

[GBuella]

In D43816#1064625, @craig.topper wrote:

Changing it from TB to PS will affect the behavior of 0xf2 0x0f 0x09 and 0x66 0x0f 0x09. Which I think we still want to disassemble to just wbinvd.

True. I reverted it to TB.

[craig.topper]

LGTM

include/llvm/IR/IntrinsicsX86.td

   def int_x86_clzero : GCCBuiltin<"__builtin_ia32_clzero">,
       Intrinsic<[], [llvm_ptr_ty], []>;
 }
+
+//===----------------------------------------------------------------------===//
+// Cache line write back intrinsics
+
+// Write back no-invalidate
+let TargetPrefix = "x86" in {
+  def int_x86_wbnoinvd : GCCBuiltin<"__builtin_ia32_wbnoinvd">,
+      Intrinsic<[], [], []>;
+}

lib/Support/Host.cpp

   Features["tbm"]    = HasExtLeaf1 && ((ECX >> 21) & 1);
   Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
 
+  // Miscellaneous memory related features, detected by
+  // using the 0x80000008 leaf of the CPUID instruction
   bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
                      !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
-  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
+  Features["clzero"]   = HasExtLeaf8 && ((EBX >> 0) & 1);
+  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
 
   bool HasLeaf7 =
       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);

lib/Target/X86/X86.td

                                       "Flush A Cache Line Optimized">;
 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
                                       "Cache Line Write Back">;
+def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
+                                      "Write Back No Invalidate">;
 def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
                                     "Support RDPID instructions">;
 // On some processors, instructions that implicitly take two memory operands are

 def ProcIntelCNL  : SubtargetFeature<"cannonlake", "X86ProcFamily",
                     "IntelCannonlake", "Intel Cannonlake processors">;
 def ProcIntelICL  : SubtargetFeature<"icelake", "X86ProcFamily",
-                    "IntelIcelake", "Intel Icelake processors">;
+                    "IntelIcelake", "Intel Icelake Client processors">;
+def ProcIntelICX  : SubtargetFeature<"icelakex", "X86ProcFamily",
+                    "IntelIcelakeServer", "Intel Icelake Server processors">;
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, GenericModel, Features>;

 ]>;
 def : IcelakeProc<"icelake">;
 
+class IcelakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
+                                           ICLFeatures.Value, [
+  ProcIntelICX,
+  FeatureHasFastGather,
+  FeatureWBNOINVD
+]>;
+def : IcelakeServerProc<"icelakex">;
+
 // AMD CPUs.
 
 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;

lib/Target/X86/X86InstrInfo.td

 def HasIBT       : Predicate<"Subtarget->hasIBT()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
+def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
 def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,

lib/Target/X86/X86InstrSystem.td

 let SchedRW = [WriteSystem] in {
 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
+
+// wbnoinvd is like wbinvd, except without invalidation
+// XS refers to the extra F3 prefix -- which originally used refer to repetition
+def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
+                 [(int_x86_wbnoinvd)], IIC_INVD>, XS,
+                 Requires<[HasWBNOINVD]>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//

lib/Target/X86/X86Subtarget.h

     IntelSKX,
     IntelCannonlake,
     IntelIcelake,
+    IntelIcelakeServer,
   };
 
 protected:

   /// Processor supports Cache Line Write Back instruction
   bool HasCLWB;
 
+  /// Processor supports Write Back No Invalidate instruction
+  bool HasWBNOINVD;
+
   /// Processor support RDPID instruction
   bool HasRDPID;
 

   bool hasIBT() const { return HasIBT; }
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
   bool hasCLWB() const { return HasCLWB; }
+  bool hasWBNOINVD() const { return HasWBNOINVD; }
   bool hasRDPID() const { return HasRDPID; }
   bool useRetpoline() const { return UseRetpoline; }
   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }

lib/Target/X86/X86Subtarget.cpp

   HasSGX = false;
   HasCLFLUSHOPT = false;
   HasCLWB = false;
+  HasWBNOINVD = false;
   HasRDPID = false;
   UseRetpoline = false;
   UseRetpolineExternalThunk = false;

test/CodeGen/X86/cpus.ll

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelakex 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=atom 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

test/CodeGen/X86/wbnoinvd-intrinsic.ll

+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+wbnoinvd | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+wbnoinvd | FileCheck %s
+
+define void @wbnoinvd() nounwind {
+; CHECK-LABEL: wbnoinvd:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    wbnoinvd
+; CHECK-NEXT:    ret{{.}}
+  tail call void @llvm.x86.wbnoinvd()
+  ret void
+}
+declare void @llvm.x86.wbnoinvd() nounwind

test/MC/Disassembler/X86/x86-32.txt

 
 # CHECK: ptwritel %eax
 0xf3 0x0f 0xae 0xe0
+
+# CHECK: wbnoinvd
+0xf3 0x0f 0x09

test/MC/Disassembler/X86/x86-64.txt

 
 # CHECK: ptwriteq %rax
 0xf3 0x48 0x0f 0xae 0xe0
+
+# CHECK: wbnoinvd
+0xf3 0x0f 0x09

test/MC/X86/x86-32-coverage.s

 // CHECK:  encoding: [0x0f,0x09]
           wbinvd
 
+// CHECK: wbnoinvd
+// CHECK:  encoding: [0xf3,0x0f,0x09]
+          wbnoinvd
+
 // CHECK: cpuid
 // CHECK:  encoding: [0x0f,0xa2]
           cpuid

test/MC/X86/x86-64.s

 // CHECK:  encoding: [0xf3,0x48,0x0f,0xae,0xe0]
 ptwriteq %rax
 
+// CHECK: wbnoinvd
+// CHECK:  encoding: [0xf3,0x0f,0x09]
+          wbnoinvd
+
 //  __asm __volatile(
 //    "pushf        \n\t"
 //    "popf       \n\t"