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[X86][SSE] Reduce FADD/FSUB/FMUL costs on later targets (PR36280)
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Authored by RKSimon on Feb 24 2018, 10:03 AM.

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Summary

Agner's tables indicate that for SSE42+ targets (Core2 and later) we can reduce the FADD/FSUB/FMUL costs down to 1, which should fix the Himeno benchmark.

Note: the AVX512 FDIV costs look rather dodgy, but this isn't part of this patch.

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rL LLVM

Event Timeline

RKSimon created this revision.Feb 24 2018, 10:03 AM
fhahn added a subscriber: fhahn.Feb 24 2018, 10:06 AM
This revision is now accepted and ready to land.Feb 26 2018, 11:19 AM
This revision was automatically updated to reflect the committed changes.