[PowerPC] Disable shrink-wrapping when PC address is acquired through the link register

[nemanjai]

Summary

When we need to acquire the address of the next instruction through the link register, this will always be added to the entry block. Of course, since we're clobbering the link register, we need to make sure we save it first. However, the fact that we need to do this is only apparent at PEI time (i.e. after shrink-wrapping).

This patch simply disables shrink-wrapping on functions that need to do this - there's no sense at looking at anything further in this function since we are positive that we won't be able to shrink-wrap the function.

This fixes PR33547.

[hfinkel]

LGTM

llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp

if (CR2Spilled || CR3Spilled || CR4Spilled) {
     restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
                MBB, I, CSI, CSIIndex);
   }
 
   return true;
 }
 
 bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
+  if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())
+    return false;
   return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
           MF.getSubtarget<PPCSubtarget>().isPPC64());
 }

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
         }
       } else {
         GlobalBaseReg =
           RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass);
         BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
         BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
       }
     } else {
+      // We must ensure that this sequence is dominated by the prologue.
+      // FIXME: This is a bit of a big hammer since we don't get the benefits
+      // of shrink-wrapping whenever we emit this instruction. Considering
+      // this is used in any function where we emit a jump table, this may be
+      // a significant limitation. We should consider inserting this in the
+      // block where it is used and then commoning this sequence up if it
+      // appears in multiple places.
+      // Note: on ISA 3.0 cores, we can use lnia (addpcis) insteand of
+      // MovePCtoLR8.
+      MF->getInfo<PPCFunctionInfo>()->setShrinkWrapDisabled(true);
       GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
     }
   }
   return CurDAG->getRegister(GlobalBaseReg,
                              PPCLowering->getPointerTy(CurDAG->getDataLayout()))
       .getNode();

llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h

class PPCFunctionInfo : public MachineFunctionInfo {
   /// Frame index where the old PIC base pointer is stored.
   int PICBasePointerSaveIndex = 0;
 
   /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
   /// function.  This is only valid after the initial scan of the function by
   /// PEI.
   bool MustSaveLR;
 
+  /// Do we have to disable shrink-wrapping? This has to be set if we emit any
+  /// instructions that clobber LR in the entry block because discovering this
+  /// in PEI is too late (happens after shrink-wrapping);
+  bool ShrinkWrapDisabled = false;
+
   /// Does this function have any stack spills.
   bool HasSpills = false;
 
   /// Does this function spill using instructions with only r+r (not r+i)
   /// forms.
   bool HasNonRISpills = false;
 
   /// SpillsCR - Indicates whether CR is spilled in the current function.
public:
   /// MustSaveLR - This is set when the prolog/epilog inserter does its initial
   /// scan of the function. It is true if the LR/LR8 register is ever explicitly
   /// defined/clobbered in the machine function (e.g. by calls and movpctolr,
   /// which is used in PIC generation), or if the LR stack slot is explicitly
   /// referenced by builtin_return_address.
   void setMustSaveLR(bool U) { MustSaveLR = U; }
   bool mustSaveLR() const    { return MustSaveLR; }
 
+  /// We certainly don't want to shrink wrap functions if we've emitted a
+  /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely
+  /// has to go into the entry block.
+  void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; }
+  bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; }
+
   void setHasSpills()      { HasSpills = true; }
   bool hasSpills() const   { return HasSpills; }
 
   void setHasNonRISpills()    { HasNonRISpills = true; }
   bool hasNonRISpills() const { return HasNonRISpills; }
 
   void setSpillsCR()       { SpillsCR = true; }
   bool isCRSpilled() const { return SpillsCR; }

llvm/trunk/test/CodeGen/PowerPC/pr33547.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 -code-model=large < %s | FileCheck %s
+%struct.STATICS1 = type <{ [128 x i8] }>
+
+@.STATICS1 = internal global %struct.STATICS1 <{ [128 x i8] c"\09\00\00\00\03\00\00\00\05\00\00\00\04\00\00\00\0A\00\00\00\0A\00\00\00\0B\00\00\00\0A\08\AF/\B8\B6\87\04 \A1\07\00\08\9D\00\00\09\00\00\00\05\00\00\00\03\00\00\00\03\00\00\00\05\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" }>, align 16
+@.C302_MAIN_ = internal constant i32 4
+
+; Function Attrs: noinline norecurse nounwind
+define void @main() {
+L.entry:
+  tail call void @testFunc(i64* bitcast (i8* getelementptr inbounds (%struct.STATICS1, %struct.STATICS1* @.STATICS1, i64 0, i32 0, i64 124) to i64*), i64* bitcast (i32* @.C302_MAIN_ to i64*))
+  ret void
+}
+
+; Function Attrs: noinline norecurse nounwind readonly
+define signext i32 @ifunc_(i64* nocapture readonly %i) {
+; CHECK-LABEL: ifunc_:
+; CHECK:       # %bb.0: # %L.entry
+; CHECK-NEXT:    lwa 3, 0(3)
+; CHECK-NEXT:    blr
+L.entry:
+  %0 = bitcast i64* %i to i32*
+  %1 = load i32, i32* %0, align 4
+  ret i32 %1
+}
+
+; Function Attrs: noinline norecurse nounwind
+define void @testFunc(i64* nocapture %r, i64* nocapture readonly %k) {
+; CHECK-LABEL: testFunc
+; CHECK: mflr 0
+; CHECK: std 0, 16(1)
+; CHECK: bl .[[BRANCHNEXT:[L0-9\$a-z]+]]
+; CHECK-NEXT: [[BRANCHNEXT]]
+L.entry:
+  %0 = bitcast i64* %k to i32*
+  %1 = load i32, i32* %0, align 4
+  switch i32 %1, label %L.LB3_307 [
+    i32 1, label %L.LB3_307.sink.split
+    i32 3, label %L.LB3_307.sink.split
+    i32 4, label %L.LB3_321.split
+    i32 5, label %L.LB3_307.sink.split
+    i32 6, label %infloop.preheader
+    i32 2, label %infloop11.preheader
+  ]
+
+infloop11.preheader:                              ; preds = %L.entry
+  br label %infloop11
+
+infloop.preheader:                                ; preds = %L.entry
+  br label %infloop
+
+L.LB3_321.split:                                  ; preds = %L.entry
+  br label %L.LB3_307.sink.split
+
+L.LB3_307.sink.split:                             ; preds = %L.LB3_321.split, %L.entry, %L.entry, %L.entry
+  %.sink = phi i32 [ 5, %L.LB3_321.split ], [ -3, %L.entry ], [ -3, %L.entry ], [ -3, %L.entry ]
+  %2 = bitcast i64* %r to i32*
+  store i32 %.sink, i32* %2, align 4
+  br label %L.LB3_307
+
+L.LB3_307:                                        ; preds = %L.LB3_307.sink.split, %L.entry
+  ret void
+
+infloop:                                          ; preds = %infloop.preheader, %infloop
+  br label %infloop
+
+infloop11:                                        ; preds = %infloop11.preheader, %infloop11
+  br label %infloop11
+}