[X86][3DNOW] Teach decoder about AMD 3DNow! instrs

[rafauler]

Summary

This patch makes the decoder understand old AMD 3DNow!
instructions that have never been properly supported in the X86
disassembler, despite being supported in other subsystems. Hopefully
this should make the X86 decoder more complete with respect to binaries
containing legacy code.

[craig.topper]

LGTM. Thanks a lot for doing this. Its good to see it finally supported.

[rafauler]

np, thanks for reviewing this!

[craig.topper]

test/MC/Disassembler/X86/amd3dnow.txt

29

Is this all the 3dnow instructions? I think some may be missing.

[rafauler]

test/MC/Disassembler/X86/amd3dnow.txt

29

There are some that are definitely missing, I'll try to add them all here, since there aren't too many in the entire 3dnow encoding space.

[craig.topper]

I found this bug in the database for 3dnow support being missing. https://bugs.llvm.org/show_bug.cgi?id=21168 We should be able to close it after this I hope.

[rafauler]

Add a more complete LIT file that tests all opcodes

[craig.topper]

Thank you for adding the additional tests. LGTM

lib/Target/X86/Disassembler/X86DisassemblerDecoder.h

enum VEXPrefixCode {
   VEX_PREFIX_F2 = 0x3
 };
 
 enum VectorExtensionType {
   TYPE_NO_VEX_XOP   = 0x0,
   TYPE_VEX_2B       = 0x1,
   TYPE_VEX_3B       = 0x2,
   TYPE_EVEX         = 0x3,
-  TYPE_XOP          = 0x4
+  TYPE_XOP          = 0x4,
+  TYPE_3DNOW        = 0x5
 };
 
 /// \brief Type for the byte reader that the consumer must provide to
 /// the decoder. Reads a single byte from the instruction's address space.
 /// \param arg     A baton that the consumer can associate with any internal
 ///                state that it needs.
 /// \param byte    A pointer to a single byte in memory that should be set to
 ///                contain the value at address.

lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

if (insn->vectorExtensionType == TYPE_XOP) {
         insn->hasOpSize = true;
         break;
       }
 
       dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
                 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
                 insn->vectorExtensionPrefix[2]);
     }
+  } else if (byte == 0x0f) {
+    uint8_t byte1;
+
+    // Check for AMD 3DNow without a REX prefix
+    if (consumeByte(insn, &byte1)) {
+      unconsumeByte(insn);
+    } else {
+      if (byte1 != 0x0f) {
+        unconsumeByte(insn);
+        unconsumeByte(insn);
+      } else {
+        dbgprintf(insn, "Found AMD 3DNow prefix 0f0f");
+        insn->vectorExtensionType = TYPE_3DNOW;
+      }
+    }
   } else if (isREX(insn, byte)) {
     if (lookAtByte(insn, &nextByte))
       return -1;
     insn->rexPrefix = byte;
     dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
+
+    // Check for AMD 3DNow with a REX prefix
+    if (nextByte == 0x0f) {
+      consumeByte(insn, &nextByte);
+      uint8_t byte1;
+
+      if (consumeByte(insn, &byte1)) {
+        unconsumeByte(insn);
+      } else {
+        if (byte1 != 0x0f) {
+          unconsumeByte(insn);
+          unconsumeByte(insn);
+        } else {
+          dbgprintf(insn, "Found AMD 3DNow prefix 0f0f");
+          insn->vectorExtensionType = TYPE_3DNOW;
+        }
+      }
+    }
   } else
     unconsumeByte(insn);
 
   if (insn->mode == MODE_16BIT) {
     insn->registerSize = (insn->hasOpSize ? 4 : 2);
     insn->addressSize = (insn->hasAdSize ? 4 : 2);
     insn->displacementSize = (insn->hasAdSize ? 4 : 2);
     insn->immediateSize = (insn->hasOpSize ? 4 : 2);
if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
       insn->displacementSize = (insn->hasOpSize ? 2 : 4);
       insn->immediateSize = (insn->hasOpSize ? 2 : 4);
     }
   }
 
   return 0;
 }
 
+static int readModRM(struct InternalInstruction* insn);
+
 /*
  * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
  *   extended or escape opcodes).
  *
  * @param insn  - The instruction whose opcode is to be read.
  * @return      - 0 if the opcode could be read successfully; nonzero otherwise.
  */
 static int readOpcode(struct InternalInstruction* insn) {
case XOP_MAP_SELECT_8:
       return consumeByte(insn, &insn->opcode);
     case XOP_MAP_SELECT_9:
       insn->opcodeType = XOP9_MAP;
       return consumeByte(insn, &insn->opcode);
     case XOP_MAP_SELECT_A:
       insn->opcodeType = XOPA_MAP;
       return consumeByte(insn, &insn->opcode);
     }
+  } else if (insn->vectorExtensionType == TYPE_3DNOW) {
+    // Consume operands before the opcode to comply with the 3DNow encoding
+    if (readModRM(insn))
+      return -1;
+    insn->opcodeType = TWOBYTE;
+    return consumeByte(insn, &insn->opcode);
   }
 
   if (consumeByte(insn, &current))
     return -1;
 
   if (current == 0x0f) {
     dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
 
static int readOpcode(struct InternalInstruction* insn) {
    * Anything we consume from here on must be unconsumed.
    */
 
   insn->opcode = current;
 
   return 0;
 }
 
-static int readModRM(struct InternalInstruction* insn);
-
 /*
  * getIDWithAttrMask - Determines the ID of an instruction, consuming
  *   the ModR/M byte as appropriate for extended and escape opcodes,
  *   and using a supplied attribute mask.
  *
  * @param instructionID - A pointer whose target is filled in with the ID of the
  *                        instruction.
  * @param insn          - The instruction whose ID is to be determined.
if (insn->vectorExtensionType == TYPE_EVEX) {
         break;
       case VEX_PREFIX_F2:
         attrMask |= ATTR_XD;
         break;
       }
 
       if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
         attrMask |= ATTR_VEXL;
+    } else if (insn->vectorExtensionType == TYPE_3DNOW) {
+      attrMask |= ATTR_3DNOW;
     } else {
       return -1;
     }
   } else if (!insn->mandatoryPrefix) {
     // If we don't have mandatory prefix we should use legacy prefixes here
     if (insn->hasOpSize && (insn->mode != MODE_16BIT))
       attrMask |= ATTR_OPSIZE;
     if (insn->hasAdSize)

lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h

#define ATTRIBUTE_BITS                  \
   ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5))   \
   ENUM_ENTRY(ATTR_VEX,    (0x1 << 6))   \
   ENUM_ENTRY(ATTR_VEXL,   (0x1 << 7))   \
   ENUM_ENTRY(ATTR_EVEX,   (0x1 << 8))   \
   ENUM_ENTRY(ATTR_EVEXL,  (0x1 << 9))   \
   ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10))  \
   ENUM_ENTRY(ATTR_EVEXK,  (0x1 << 11))  \
   ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12))  \
-  ENUM_ENTRY(ATTR_EVEXB,  (0x1 << 13))
+  ENUM_ENTRY(ATTR_EVEXB,  (0x1 << 13))  \
+  ENUM_ENTRY(ATTR_3DNOW,  (0x1 << 14))
 
 #define ENUM_ENTRY(n, v) n = v,
 enum attributeBits {
   ATTRIBUTE_BITS
   ATTR_max
 };
 #undef ENUM_ENTRY
 
#define INSTRUCTION_CONTEXTS                                                   \
   ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ,  4,  "requires EVEX_KZ, L, W and OpSize")       \
   ENUM_ENTRY(IC_EVEX_L2_KZ,          3,  "requires EVEX_KZ and the L2 prefix")       \
   ENUM_ENTRY(IC_EVEX_L2_XS_KZ,       4,  "requires EVEX_KZ and the L2 and XS prefix")\
   ENUM_ENTRY(IC_EVEX_L2_XD_KZ,       4,  "requires EVEX_KZ and the L2 and XD prefix")\
   ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ,   4,  "requires EVEX_KZ, L2, and OpSize")         \
   ENUM_ENTRY(IC_EVEX_L2_W_KZ,        3,  "requires EVEX_KZ, L2 and W")               \
   ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ,     4,  "requires EVEX_KZ, L2, W and XS prefix")    \
   ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ,     4,  "requires EVEX_KZ, L2, W and XD prefix")    \
-  ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4,  "requires EVEX_KZ, L2, W and OpSize")
+  ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4,  "requires EVEX_KZ, L2, W and OpSize")       \
+  ENUM_ENTRY(IC_3DNOW,               8,  "requires AMD 3DNow prefix 0f0f")
 
 #define ENUM_ENTRY(n, r, d) n,
 enum InstructionContext {
   INSTRUCTION_CONTEXTS
   IC_max
 };
 #undef ENUM_ENTRY
 

lib/Target/X86/X86Instr3DNow.td

class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat,
       : I<o, F, outs, ins, asm, pat, itin>, TB, Requires<[Has3DNow]> {
 }
 
 class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
                    InstrItinClass itin>
       : I3DNow<o, F, (outs VR64:$dst), ins,
           !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat, itin>,
         Has3DNow0F0FOpcode {
-  // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
-  let isAsmParserOnly = 1;
   let Constraints = "$src1 = $dst";
 }
 
 class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
                   InstrItinClass itin>
       : I3DNow<o, F, (outs VR64:$dst), ins,
           !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat, itin>,
-        Has3DNow0F0FOpcode {
-  // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
-  let isAsmParserOnly = 1;
-}
+        Has3DNow0F0FOpcode;
 
 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, OpndItins itins,
                                bit Commutable = 0, string Ver = ""> {
   let isCommutable = Commutable in
   def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
     [(set VR64:$dst, (!cast<Intrinsic>(
       !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))],
       itins.rr>, Sched<[itins.Sched]>;

test/MC/Disassembler/X86/amd3dnow.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64-unknown-linux-gnu | FileCheck %s
+
+# Reference: AMD64 Architecture Programmer's Manual Vol.3
+# Pub no. 24594 - Rev. 3.25 - Dec 2017 - pgs.468-469
+
+# CHECK: pfcmpge     %mm0, %mm1
+0x0f 0x0f 0xc8 0x90
+
+# CHECK: pfcmpgt     %mm2, %mm0
+0x0f 0x0f 0xc2 0xa0
+
+# CHECK: pfcmpeq     %mm5, %mm2
+0x0f 0x0f 0xd5 0xb0
+
+# CHECK: pfmin       %mm1, %mm0
+0x0f 0x0f 0xc1 0x94
+
+# CHECK: pfmax       (%rax), %mm0
+0x0f 0x0f 0x00 0xa4
+
+# CHECK: pfmul       %mm6, %mm0
+0x0f 0x0f 0xc6 0xb4
+
+# CHECK: pfrcp       (%rbx), %mm1
+0x0f 0x0f 0x0b 0x96
+
+# CHECK: pfrcpit1    %mm0, %mm2
+0x0f 0x0f 0xd0 0xa6
+
+# CHECK: pfrcpit2    %mm0, %mm1
+0x0f 0x0f 0xc8 0xb6
+
+# CHECK: pfrsqrt     (%eax), %mm1
+0x67 0x0f 0x0f 0x08 0x97
+
+# CHECK: pfrsqit1    (%ebx), %mm4
+0x67 0x0f 0x0f 0x23 0xa7
+
+# CHECK: pmulhrw     %mm3, %mm0
+0x0f 0x0f 0xc3 0xb7
+
+# CHECK: pi2fw       %mm1, %mm3
+0x0f 0x0f 0xd9 0x0c
+
+# CHECK: pf2iw       %mm2, %mm4
+0x0f 0x0f 0xe2 0x1c
+
+# CHECK: pi2fd       %mm3, %mm1
+0x0f 0x0f 0xcb 0x0d
+
+# CHECK: pf2id       (%rdi,%r8), %mm1
+0x42 0x0f 0x0f 0x0c 0x07 0x1d
+
+# CHECK: pfnacc      16(%eax,%ebx,4), %mm0
+0x67 0x0f 0x0f 0x44 0x98 0x10 0x8a
+
+# CHECK: pfsub       %mm1, %mm0
+0x0f 0x0f 0xc1 0x9a
+
+# CHECK: pfsubr      %mm2, %mm1
+0x0f 0x0f 0xca 0xaa
+
+# CHECK: pswapd      %mm1, %mm3
+0x0f 0x0f 0xd9 0xbb
+
+# CHECK: pfpnacc     %mm0, %mm2
+0x0f 0x0f 0xd0 0x8e
+
+# CHECK: pfadd       %mm4, %mm3
+0x0f 0x0f 0xdc 0x9e
+
+# CHECK: pfacc       %mm1, %mm2
+0x0f 0x0f 0xd1 0xae
+
+# CHECK: pavgusb     %mm1, %mm3
+0x0f 0x0f 0xd9 0xbf

utils/TableGen/X86DisassemblerTables.cpp

static inline bool inheritsFrom(InstructionContext child,
   case IC_EVEX_L2_W_XD_K_B:
   case IC_EVEX_L2_W_OPSIZE_K_B:
     return false;
   case IC_EVEX_L2_W_KZ_B:
   case IC_EVEX_L2_W_XS_KZ_B:
   case IC_EVEX_L2_W_XD_KZ_B:
   case IC_EVEX_L2_W_OPSIZE_KZ_B:
     return false;
+  case IC_3DNOW:
+    return false;
   default:
     errs() << "Unknown instruction class: " <<
       stringForContext((InstructionContext)parent) << "\n";
     llvm_unreachable("Unknown instruction class");
   }
 }
 
 /// outranks - Indicates whether, if an instruction has two different applicable
for (unsigned index = 0; index < NumInstructions; ++index) {
     o.indent(i * 2) << "},\n";
   }
 
   i--;
   o.indent(i * 2) << "};" << "\n";
 }
 
 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
-  const unsigned int tableSize = 16384;
+  const unsigned int tableSize = 32768;
   o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
                      "[" << tableSize << "] = {\n";
   i++;
 
   for (unsigned index = 0; index < tableSize; ++index) {
     o.indent(i * 2);
 
-    if (index & ATTR_EVEX) {
+    if (index & ATTR_3DNOW)
+      o << "IC_3DNOW";
+    else if (index & ATTR_EVEX) {
       o << "IC_EVEX";
       if (index & ATTR_EVEXL2)
         o << "_L2";
       else if (index & ATTR_EVEXL)
         o << "_L";
       if (index & ATTR_REXW)
         o << "_W";
       if (index & ATTR_OPSIZE)

utils/TableGen/X86RecognizableInstr.h

private:
   /// The hasEVEX_L2Prefix field from the record
   bool HasEVEX_L2Prefix;
   /// The hasEVEX_K field from the record
   bool HasEVEX_K;
   /// The hasEVEX_KZ field from the record
   bool HasEVEX_KZ;
   /// The hasEVEX_B field from the record
   bool HasEVEX_B;
+  /// The has3DNow0F0FOpcode field from the record
+  bool Has3DNow0F0FOpcode;
   /// Indicates that the instruction uses the L and L' fields for RC.
   bool EncodeRC;
   /// The isCodeGenOnly field from the record
   bool IsCodeGenOnly;
   /// The ForceDisassemble field from the record
   bool ForceDisassemble;
   // The CD8_Scale field from the record
   uint8_t CD8_Scale;
   // Whether the instruction has the predicate "In64BitMode"
   bool Is64Bit;
   // Whether the instruction has the predicate "In32BitMode"
   bool Is32Bit;
 
   /// The instruction name as listed in the tables
   std::string Name;
 
   /// Indicates whether the instruction should be emitted into the decode
   /// tables; regardless, it will be emitted into the instruction info table
   bool ShouldBeEmitted;
-  
   /// The operands of the instruction, as listed in the CodeGenInstruction.
   /// They are not one-to-one with operands listed in the MCInst; for example,
   /// memory operands expand to 5 operands in the MCInst
   const std::vector<CGIOperandList::OperandInfo>* Operands;
-  
   /// The description of the instruction that is emitted into the instruction
   /// info table
   InstructionSpecifier* Spec;
 
   /// insnContext - Returns the primary context in which the instruction is
   ///   valid.
   ///
   /// @return - The context in which the instruction is valid.
private:
   /// handleOperand - Converts a single operand from the LLVM table format to
   ///   the emitted table format, handling any duplicate operands it encounters
   ///   and then one non-duplicate.
   ///
   /// @param optional             - Determines whether to assert that the
   ///                               operand exists.
   /// @param operandIndex         - The index into the generated operand table.
   ///                               Incremented by this function one or more
-  ///                               times to reflect possible duplicate 
+  ///                               times to reflect possible duplicate
   ///                               operands).
   /// @param physicalOperandIndex - The index of the current operand into the
   ///                               set of non-duplicate ('physical') operands.
   ///                               Incremented by this function once.
   /// @param numPhysicalOperands  - The number of non-duplicate operands in the
   ///                               instructions.
   /// @param operandMapping       - The operand mapping, which has an entry for
   ///                               each operand that indicates whether it is a
private:
   ///   identified during operand parsing.
   ///
   /// @return - true if at this point we believe the instruction should be
   ///   emitted; false if not.  This will return false if filter() returns false
   ///   once emitInstructionSpecifier() has been called.
   bool shouldBeEmitted() const {
     return ShouldBeEmitted;
   }
-  
   /// emitInstructionSpecifier - Loads the instruction specifier for the current
   ///   instruction into a DisassemblerTables.
   ///
   void emitInstructionSpecifier();
-  
   /// emitDecodePath - Populates the proper fields in the decode tables
   ///   corresponding to the decode paths for this instruction.
   ///
   /// \param tables The DisassemblerTables to populate with the decode
   ///               decode information for the current instruction.
   void emitDecodePath(DisassemblerTables &tables) const;
 
   /// Constructor - Initializes a RecognizableInstr with the appropriate fields
public:
   ///               information.
   /// \param insn   The CodeGenInstruction to be used as a source for this
   ///               information.
   /// \param uid    The unique ID of the instruction.
   static void processInstr(DisassemblerTables &tables,
                            const CodeGenInstruction &insn,
                            InstrUID uid);
 };
-  
 } // namespace X86Disassembler
 
 } // namespace llvm
 
 #endif

utils/TableGen/X86RecognizableInstr.cpp

RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   }
 
   OpPrefix = byteFromRec(Rec, "OpPrefixBits");
   OpMap    = byteFromRec(Rec, "OpMapBits");
   Opcode   = byteFromRec(Rec, "Opcode");
   Form     = byteFromRec(Rec, "FormBits");
   Encoding = byteFromRec(Rec, "OpEncBits");
 
-  OpSize           = byteFromRec(Rec, "OpSizeBits");
-  AdSize           = byteFromRec(Rec, "AdSizeBits");
-  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
-  HasVEX_4V        = Rec->getValueAsBit("hasVEX_4V");
-  VEX_WPrefix      = byteFromRec(Rec,"VEX_WPrefix");
-  IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
-  HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
-  HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
-  HasEVEX_KZ       = Rec->getValueAsBit("hasEVEX_Z");
-  HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
-  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
-  ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
-  CD8_Scale        = byteFromRec(Rec, "CD8_Scale");
+  OpSize             = byteFromRec(Rec, "OpSizeBits");
+  AdSize             = byteFromRec(Rec, "AdSizeBits");
+  HasREX_WPrefix     = Rec->getValueAsBit("hasREX_WPrefix");
+  HasVEX_4V          = Rec->getValueAsBit("hasVEX_4V");
+  VEX_WPrefix        = byteFromRec(Rec,"VEX_WPrefix");
+  IgnoresVEX_L       = Rec->getValueAsBit("ignoresVEX_L");
+  HasEVEX_L2Prefix   = Rec->getValueAsBit("hasEVEX_L2");
+  HasEVEX_K          = Rec->getValueAsBit("hasEVEX_K");
+  HasEVEX_KZ         = Rec->getValueAsBit("hasEVEX_Z");
+  HasEVEX_B          = Rec->getValueAsBit("hasEVEX_B");
+  Has3DNow0F0FOpcode = Rec->getValueAsBit("has3DNow0F0FOpcode");
+  IsCodeGenOnly      = Rec->getValueAsBit("isCodeGenOnly");
+  ForceDisassemble   = Rec->getValueAsBit("ForceDisassemble");
+  CD8_Scale          = byteFromRec(Rec, "CD8_Scale");
 
   Name      = Rec->getName();
 
   Operands = &insn.Operands.OperandList;
 
   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
 
   EncodeRC = HasEVEX_B &&
if (Encoding == X86Local::EVEX) {
     else if (OpPrefix == X86Local::XS)
       insnContext = IC_VEX_XS;
     else if (OpPrefix == X86Local::PS)
       insnContext = IC_VEX;
     else {
       errs() << "Instruction does not use a prefix: " << Name << "\n";
       llvm_unreachable("Invalid prefix");
     }
+  } else if (Has3DNow0F0FOpcode) {
+    insnContext = IC_3DNOW;
   } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
     if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
       insnContext = IC_64BIT_REXW_OPSIZE;
     else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
       insnContext = IC_64BIT_REXW_ADSIZE;
     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
       insnContext = IC_64BIT_XD_OPSIZE;
     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)