[X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to v2i64/v2f64

[RKSimon]

Summary

Minor refactor to make it possible for LowerBUILD_VECTORAsVariablePermute to be used with a wider variety of shuffles op and types.

I'd have liked to add v4i32/v4f32 support as well but we don't see v4i32 index extractions at the moment (which is why I created D42308)

After this I intend to begin adding scaling support for PSHUFB (v8i16, v4i32, v2i64)) and VPERMPS (v4f64, v4i64).

[zvi]

LGTM

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

 //               (extract_elt V, (extract_elt I, 1)),
 //                    ...
 // ->
 // (vpermv I, V)
 //
 // TODO: Handle undefs
 // TODO: Utilize pshufb and zero mask blending to support more efficient
 // construction of vectors with constant-0 elements.
-// TODO: Use smaller-element vectors of same width, and "interpolate" the indices,
-// when no native operation available.
+// TODO: Use smaller-element vectors of same width, and "interpolate" the
+// indices, when no native operation available.
 static SDValue
 LowerBUILD_VECTORAsVariablePermute(SDValue V, SelectionDAG &DAG,
                                    const X86Subtarget &Subtarget) {
-  // Look for VPERMV and PSHUFB opportunities.
-  MVT VT = V.getSimpleValueType();
-  switch (VT.SimpleTy) {
+  // Look for VPERMV/VPERMILPV/PSHUFB opportunities.
+  auto LegalPermuteOpcode = [&Subtarget](MVT DstVT, MVT &ShuffleVT) {
+    unsigned Opcode = 0;
+    switch (DstVT.SimpleTy) {
     default:
-    return SDValue();
+      break;
     case MVT::v16i8:
-    if (!Subtarget.hasSSE3())
-      return SDValue();
+      if (Subtarget.hasSSE3())
+        Opcode = X86ISD::PSHUFB;
+      break;
+    case MVT::v2f64:
+    case MVT::v2i64:
+      if (Subtarget.hasAVX()) {
+        Opcode = X86ISD::VPERMILPV;
+        ShuffleVT = MVT::v2f64;
+      }
       break;
     case MVT::v8f32:
     case MVT::v8i32:
-    if (!Subtarget.hasAVX2())
-      return SDValue();
+      if (Subtarget.hasAVX2())
+        Opcode = X86ISD::VPERMV;
       break;
     case MVT::v4i64:
     case MVT::v4f64:
-    if (!Subtarget.hasVLX())
-      return SDValue();
+      if (Subtarget.hasVLX())
+        Opcode = X86ISD::VPERMV;
       break;
     case MVT::v16f32:
     case MVT::v8f64:
     case MVT::v16i32:
     case MVT::v8i64:
-    if (!Subtarget.hasAVX512())
-      return SDValue();
+      if (Subtarget.hasAVX512())
+        Opcode = X86ISD::VPERMV;
       break;
     case MVT::v32i16:
-    if (!Subtarget.hasBWI())
-      return SDValue();
+      if (Subtarget.hasBWI())
+        Opcode = X86ISD::VPERMV;
       break;
     case MVT::v8i16:
     case MVT::v16i16:
-    if (!Subtarget.hasVLX() || !Subtarget.hasBWI())
-      return SDValue();
+      if (Subtarget.hasVLX() && Subtarget.hasBWI())
+        Opcode = X86ISD::VPERMV;
       break;
     case MVT::v64i8:
-    if (!Subtarget.hasVBMI())
-      return SDValue();
+      if (Subtarget.hasVBMI())
+        Opcode = X86ISD::VPERMV;
       break;
     case MVT::v32i8:
-    if (!Subtarget.hasVLX() || !Subtarget.hasVBMI())
-      return SDValue();
+      if (Subtarget.hasVLX() && Subtarget.hasVBMI())
+        Opcode = X86ISD::VPERMV;
       break;
     }
+    return Opcode;
+  };
+
   SDValue SrcVec, IndicesVec;
   // Check for a match of the permute source vector and permute index elements.
   // This is done by checking that the i-th build_vector operand is of the form:
   // (extract_elt SrcVec, (extract_elt IndicesVec, i)).
   for (unsigned Idx = 0, E = V.getNumOperands(); Idx != E; ++Idx) {
     SDValue Op = V.getOperand(Idx);
     if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
       return SDValue();
for (unsigned Idx = 0, E = V.getNumOperands(); Idx != E; ++Idx) {
     else if (IndicesVec != ExtractedIndex.getOperand(0))
       return SDValue();
 
     auto *PermIdx = dyn_cast<ConstantSDNode>(ExtractedIndex.getOperand(1));
     if (!PermIdx || PermIdx->getZExtValue() != Idx)
       return SDValue();
   }
 
+  MVT VT = V.getSimpleValueType();
+  MVT ShuffleVT = VT;
+  unsigned Opcode = LegalPermuteOpcode(VT, ShuffleVT);
+  if (!Opcode)
+    return SDValue();
+  assert(VT.getScalarSizeInBits() == ShuffleVT.getScalarSizeInBits() &&
+         VT.getVectorNumElements() == ShuffleVT.getVectorNumElements() &&
+         "Illegal variable permute shuffle type");
+
   unsigned NumElts = VT.getVectorNumElements();
   if (IndicesVec.getValueType().getVectorNumElements() < NumElts)
     return SDValue();
   else if (IndicesVec.getValueType().getVectorNumElements() > NumElts) {
     IndicesVec = extractSubVector(IndicesVec, 0, DAG, SDLoc(IndicesVec),
                                   NumElts * VT.getScalarSizeInBits());
   }
 
   MVT IndicesVT = EVT(VT).changeVectorElementTypeToInteger().getSimpleVT();
   IndicesVec = DAG.getZExtOrTrunc(IndicesVec, SDLoc(IndicesVec), IndicesVT);
 
   if (SrcVec.getValueSizeInBits() > VT.getSizeInBits())
     return SDValue();
   else if (SrcVec.getValueSizeInBits() < VT.getSizeInBits()) {
     SrcVec =
         DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(SrcVec), VT, DAG.getUNDEF(VT),
                     SrcVec, DAG.getIntPtrConstant(0, SDLoc(SrcVec)));
   }
 
-  if (VT == MVT::v16i8)
-    return DAG.getNode(X86ISD::PSHUFB, SDLoc(V), VT, SrcVec, IndicesVec);
-  return DAG.getNode(X86ISD::VPERMV, SDLoc(V), VT, IndicesVec, SrcVec);
+  SrcVec = DAG.getBitcast(ShuffleVT, SrcVec);
+  SDValue Res =
+      Opcode == X86ISD::VPERMV
+          ? DAG.getNode(Opcode, SDLoc(V), ShuffleVT, IndicesVec, SrcVec)
+          : DAG.getNode(Opcode, SDLoc(V), ShuffleVT, SrcVec, IndicesVec);
+  return DAG.getBitcast(VT, Res);
 }
 
 SDValue
 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
   SDLoc dl(Op);
 
   MVT VT = Op.getSimpleValueType();
   MVT EltVT = VT.getVectorElementType();

llvm/trunk/test/CodeGen/X86/var-permute-128.ll

 ; SSSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; SSSE3-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; SSSE3-NEXT:    retq
 ;
 ; AVX-LABEL: var_shuffle_v2i64:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vmovq %xmm1, %rax
-; AVX-NEXT:    andl $1, %eax
-; AVX-NEXT:    vpextrq $1, %xmm1, %rcx
-; AVX-NEXT:    andl $1, %ecx
-; AVX-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
-; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
-; AVX-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX-NEXT:    vpermilpd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %index0 = extractelement <2 x i64> %indices, i32 0
   %index1 = extractelement <2 x i64> %indices, i32 1
   %v0 = extractelement <2 x i64> %v, i64 %index0
   %v1 = extractelement <2 x i64> %v, i64 %index1
   %ret0 = insertelement <2 x i64> undef, i64 %v0, i32 0
   %ret1 = insertelement <2 x i64> %ret0, i64 %v1, i32 1
   ret <2 x i64> %ret1

 ; SSSE3-NEXT:    andl $1, %ecx
 ; SSSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSSE3-NEXT:    movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
 ; SSSE3-NEXT:    retq
 ;
 ; AVX-LABEL: var_shuffle_v2f64:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vmovq %xmm1, %rax
-; AVX-NEXT:    andl $1, %eax
-; AVX-NEXT:    vpextrq $1, %xmm1, %rcx
-; AVX-NEXT:    andl $1, %ecx
-; AVX-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
-; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT:    vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
+; AVX-NEXT:    vpermilpd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %index0 = extractelement <2 x i64> %indices, i32 0
   %index1 = extractelement <2 x i64> %indices, i32 1
   %v0 = extractelement <2 x double> %v, i64 %index0
   %v1 = extractelement <2 x double> %v, i64 %index1
   %ret0 = insertelement <2 x double> undef, double %v0, i32 0
   %ret1 = insertelement <2 x double> %ret0, double %v1, i32 1
   ret <2 x double> %ret1