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[SelectionDAG] Convert assert to condtion
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Authored by samparker on Jan 16 2018, 3:24 AM.

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tpr
arsenm

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Summary

Follow-up to D41126, which can cause assertions for AArch64 because v1f64 and v1i64 are legal types.

Oops, sorry. LGTM.

This revision is now accepted and ready to land.Jan 17 2018, 3:19 PM

This revision was automatically updated to reflect the committed changes.

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llvm/

trunk/

lib/

CodeGen/

SelectionDAG/

5 lines

Show First 20 Lines • Show All 165 Lines • ▼ Show 20 Lines	SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
unsigned ResNo) {		unsigned ResNo) {
SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);		SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
return GetScalarizedVector(Op);		return GetScalarizedVector(Op);
}		}

SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {		SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
SDValue Op = N->getOperand(0);		SDValue Op = N->getOperand(0);
if (Op.getValueType().isVector()		if (Op.getValueType().isVector()
&& Op.getValueType().getVectorNumElements() == 1) {		&& Op.getValueType().getVectorNumElements() == 1
assert(!isSimpleLegalType(Op.getValueType()));		&& !isSimpleLegalType(Op.getValueType()))
Op = GetScalarizedVector(Op);		Op = GetScalarizedVector(Op);
}
EVT NewVT = N->getValueType(0).getVectorElementType();		EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BITCAST, SDLoc(N),		return DAG.getNode(ISD::BITCAST, SDLoc(N),
NewVT, Op);		NewVT, Op);
}		}

SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {		SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
EVT EltVT = N->getValueType(0).getVectorElementType();		EVT EltVT = N->getValueType(0).getVectorElementType();
SDValue InOp = N->getOperand(0);		SDValue InOp = N->getOperand(0);
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