[InstSimplify] Missed optimization in math expression: (x+x)/x == 2

[Quolyk]

Summary

Motivation: https://bugs.llvm.org/show_bug.cgi?id=35709. I'm not sure how do I need to handle NSWSHL, NUWSHL, SHL

[majnemer]

lib/Analysis/InstructionSimplify.cpp

997

I believe this needs to be m_NUWShl.

test/Transforms/InstSimplify/div.ll

147–154

This seems wrong as per https://www.rise4fun.com/Alive/Gslf

ERROR: Mismatch in values of i32 %div

Example:
%x i32 = 0x800FE842 (2148526146, -2146441150)
%add i32 = 0x001FD084 (2084996)
Source value: 0x00000000 (0)
Target value: 0x00000002 (2)

[grandinj]

lib/Analysis/InstructionSimplify.cpp

997

Is that not trivially extendable to

(X << C) / X -> C

for any

C <= bitwidth(X)

?

[Quolyk]

lib/Analysis/InstructionSimplify.cpp

997

I think that would be pow(2, C), not just C

[Quolyk]

Abandoning, as it was fixed in D42032

lib/Analysis/InstructionSimplify.cpp

if ((IsSigned && Mul->hasNoSignedWrap()) ||
         (!IsSigned && Mul->hasNoUnsignedWrap()))
       return X;
     // If X has the form X = A / Y then X * Y cannot overflow.
     if (BinaryOperator *Div = dyn_cast<BinaryOperator>(X))
       if (Div->getOpcode() == Opcode && Div->getOperand(1) == Y)
         return X;
   }
 
+  // (X << 1) / X -> 2
+  if ((IsSigned && match(Op0, m_NSWShl(m_Specific(Op1), m_One()))) ||
+      (!IsSigned && match(Op0, m_Shl(m_Specific(Op1), m_One())))) {
+    return ConstantInt::get(Op0->getType(), 2);
+  }
+
   // (X rem Y) / Y -> 0
   if ((IsSigned && match(Op0, m_SRem(m_Value(), m_Specific(Op1)))) ||
       (!IsSigned && match(Op0, m_URem(m_Value(), m_Specific(Op1)))))
     return Constant::getNullValue(Op0->getType());
 
   // (X /u C1) /u C2 -> 0 if C1 * C2 overflow
   ConstantInt *C1, *C2;
   if (!IsSigned && match(Op0, m_UDiv(m_Value(X), m_ConstantInt(C1))) &&

test/Transforms/InstSimplify/div.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 ; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
 
 define <2 x i8> @sdiv_zero_elt_vec_constfold(<2 x i8> %x) {
 ; CHECK-LABEL: @sdiv_zero_elt_vec_constfold(
 ; CHECK-NEXT:    ret <2 x i8> undef
 ;

 ; CHECK-NEXT:    [[CALL:%.*]] = call i32 @external(), !range !0
 ; CHECK-NEXT:    ret i32 0
 ;
   %call = call i32 @external(), !range !0
   %urem = udiv i32 %call, 3
   ret i32 %urem
 }
 
+define i32 @sdiv_nsw_doublex_x(i32 %x) {
+; CHECK-LABEL: @sdiv_nsw_doublex_x(
+; CHECK-NEXT:    ret i32 2
+;
+  %add = shl nsw i32 %x, 1
+  %div = sdiv i32 %add, %x
+  ret i32 %div
+}
+
+define i32 @udiv_doublex_x(i32 %x) {
+; CHECK-LABEL: @udiv_doublex_x(
+; CHECK-NEXT:    ret i32 2
+;
+  %add = shl i32 %x, 1
+  %div = udiv i32 %add, %x
+  ret i32 %div
+}
+
 !0 = !{i32 0, i32 3}