[mips] Properly select abs and sqrt instructions

[smaksimovic]

Summary

• Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt
• Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants
• Restrict non-micromips abs/sqrt with NotInMicroMips predicate

[sdardis]

This looks

lib/Target/Mips/MicroMips32r6InstrInfo.td

1627

Spaces around the '='.

1655

Here too.

lib/Target/Mips/MicroMipsInstrFPU.td

96

Nit, align the "SDPatternOperator [...]" to under the 'string' in the line above, spaces around the '='.

101

FIXME: This needs to be part of the instruction mapping tables.

197

Nit: the closing '}' should be aligned with the def or class it's apart of.

lib/Target/Mips/MipsInstrFPU.td

462–464

Nit, indent this by 2 columns.

test/CodeGen/Mips/abs_sqrt.ll

1

Modify the existing file test/CodeGen/Mips/llvm-ir/sqrt.ll for the square root tests.

Add test/CodeGen/Mips/llvm-ir/abs.ll for the abs tests.

2

cpu should be mips32r2.

3–4

cpu should be mips32r3.

test/MC/Disassembler/Mips/micromips32/abs_sqrt.txt

1

This should go in test/MC/Disassembler/Mips/micromips32r3/valid.txt and the little endian disassembly in test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

test/MC/Disassembler/Mips/micromips32/abs_sqrt_fp64.txt

1

This should go in test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt and provide little endian disassembly in test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt.

The -mcpu= should be mips32r3. You should drop the explicit check prefix and use CHECK: for the check lines instead. Also keep the hex and CHECK on the same line, i.e.

0x54 0x0c 0x0a 0x3b
# MMFP64:     sqrt.s  $f0, $f12

Should be:

0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s  $f0, $f12

test/MC/Disassembler/Mips/mips32/abs_sqrt.txt

1

This file can be entirely dropped, existing disassembly tests cover it.

test/MC/Disassembler/Mips/mips32/abs_sqrt_fp64.txt

1

Rename this file to valid-fp64.txt and place copies in test/MC/Disassembler/Mips/mips32r{2, 3, 5}/

Also provide little endian disassembly files. You can drop the explicit check prefix and just use 'CHECK'. See our existing disassembly files and copy their style.

test/MC/Disassembler/Mips/mips32r6/abs_sqrt.txt

1

This file can be dropped as the existing tests cover it.

test/MC/Mips/abs_sqrt.s

1

Rather than providing this as a new test, you can modify existing tests to cover almost all the variants here.

For the mips32 case, modify or ensure that test/MC/Mips/mips{1, 2, 32, 32r2, 32r3, 32r5}/valid.s produce the non-micromips AFGR64 instruction. If you look at the 'abs.d' case in test/MC/Mips/micromips/valid.s, you'll see how it should look.

I've highlighted the additional changes for this file.

2

Provide this variant in test/MC/Mips/mips32r{2,3,5}/valid-fp64.s. The cpu should correspond to the directory it's in. Also test which instruction the assembly has determined it is with -show-inst.

3

Check which instructions are produced from test/MC/Mips/micromips/valid.s with the -show-inst option.

4

Provide this variant in test/MC/Mips/micromips/valid-fp64.s. Also the cpu should be mips32r3.

5

Check which instructions are produced from test/MC/Mips/micromips32r6/valid.s with the -show-inst option.

28

This case is already covered as you've modified test/MC/Mips/micromips/valid.s

[smaksimovic]

Addressed review comments.

I made a rather inconvenient naming change to the MMR6 version of SQRT.
The SQRT_D_MMR6, as it was originally named, came after FSQRT_D64_MM in the match table residing in MipsGenAsmMatcher.inc.
This was not the case with ABS, so it seems that the instructions are ordered by name as well, among other things.
Renamed SQRT_D_MMR6 to ASQRT_D_MMR6. I didn't find another way to force the ordering of records in the match table.

[sdardis]

This looks

lib/Target/Mips/MicroMips32r6InstrInfo.td

1627–1631

You can remove the definitions of these instructions from MicroMips32r6 as you have provided the FGR64 definitions in MicroMipsInstrFPU.td and the instructions share the same encodings.

1655–1661

I've checked this again, you can remove the definition of these instructions from MicroMips32r6InstrInfo.td, as they share the same encoding as the original microMIPS instruction and you have provided the FGR64 definitions in MicroMipsInstrFPU.td.

[smaksimovic]

Removed instructions from MicroMips32r6InstrInfo.td

[sdardis]

LGTM.

lib/Target/Mips/MicroMips32r6InstrInfo.td

class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
   InstrItinClass Itinerary = Itin;
   Format Form = FrmFR;
   list<Predicate> EncodingPredicates = [HasStdEnc];
 }
 
 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
                                                 II_ABS, fabs>;
-class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
-                                                II_ABS, fabs>;
+class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", FGR64Opnd, FGR64Opnd,
+                                                II_ABS, fabs>, FGR_64;
 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
                                                     FGR32Opnd, II_FLOOR>;
 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
                                                     FGR64Opnd, II_FLOOR>;
 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
                                                     FGR32Opnd, II_FLOOR>;
 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
                                                     AFGR64Opnd, II_FLOOR>;

 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
                                                     FGR64Opnd, II_TRUNC>;
 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
                                                     FGR32Opnd, II_TRUNC>;
 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
                                                     AFGR64Opnd, II_TRUNC>;
 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
                                                  II_SQRT_S, fsqrt>;
-class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
-                                                 II_SQRT_D, fsqrt>;
+class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", FGR64Opnd, FGR64Opnd,
+                                                 II_SQRT_D, fsqrt>, FGR_64;
 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;
 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;

 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
+let AddedComplexity=1 in {
   def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
   def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
+}
 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
+let AddedComplexity=1 in {
   def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
                     ISA_MICROMIPS32R6;
   def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
                     ISA_MICROMIPS32R6;
+}
 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMipsInstrFPU.td

def CVT_W_MM   : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
                  ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
 def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
                  ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32;
 def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd,
                                             II_ROUND>, ROUND_W_FM_MM<1, 0xec>,
                  ISA_MICROMIPS, FGR_32;
 def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
                  ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
-
-def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
-                              fsqrt>, ROUND_W_FM_MM<1, 0x28>,
-               ISA_MICROMIPS, FGR_32;
-
 def CVT_L_S_MM   : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
                    ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
                    ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
 
 }
 
+multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
+                  SDPatternOperator OpNode= null_frag> {
+  def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
+                ISA_MICROMIPS, FGR_32 {
+    string DecoderNamespace = "MicroMips";
+  }
+  def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
+                ISA_MICROMIPS, FGR_64 {
+    string DecoderNamespace = "MicroMipsFP64";
+  }
+}
+
+defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
+defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
+
 let DecoderNamespace = "MicroMips" in {
   def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
                   ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
-  def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
-                ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
 }
 
 let isCodeGenOnly = 1 in {
 def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
                 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS;
 def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
                 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;
 def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
                                   II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>,
                    ISA_MICROMIPS;
 def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
                                               FGR32Opnd, II_TRUNC>,
                    ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS;
 def CEIL_W_S_MM  : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
                    ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS;
 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
-                                fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;
+                                fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS {
+    string DecoderNamespace = "MicroMips";
+  }
 def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
                MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
                MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;
 
 let DecoderNamespace = "MicroMips" in {
   def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
                 MFC1_FM_MM<0x40>, ISA_MICROMIPS;

lib/Target/Mips/MipsInstrFPU.td

def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
                ABSS_FM<0x5, 16>;
   defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
 }
 
 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
              ABSS_FM<0x7, 16>;
 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
 
+let AdditionalPredicates = [NotInMicroMips] in {
 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
               II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
+}
 
 // The odd-numbered registers are only referenced when doing loads,
 // stores, and moves between floating-point and integer registers.
 // When defining instructions, we reference all 32-bit registers,
 // regardless of register aliasing.
 
 /// Move Control Registers From/To CPU Registers
 let AdditionalPredicates = [NotInMicroMips] in {

test/CodeGen/Mips/abs_sqrt.ll

+; RUN: llc -march=mips -mcpu=mips32                           -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips -mcpu=mips32   -mattr=+fp64            -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -march=mips -mcpu=mips32   -mattr=+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -march=mips -mcpu=mips32   -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+
+define float @sqrt_s(float %a) {
+; MIPS32:     sqrt.s  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_S
+; MIPS32FP64: sqrt.s  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_S
+; MM:         sqrt.s  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_S_MM
+; MMFP64:     sqrt.s  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_S_MM
+; MMR6:       sqrt.s  {{.*}}               # <MCInst #{{[0-9]+}} SQRT_S_MMR6
+  %ret = call float @llvm.sqrt.f32(float %a)
+  ret float %ret
+}
+
+define double @sqrt_d(double %a) {
+; MIPS32:     sqrt.d  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_D32
+; MIPS32FP64: sqrt.d  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_D64
+; MM:         sqrt.d  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_D32_MM
+; MMFP64:     sqrt.d  {{.*}}               # <MCInst #{{[0-9]+}} FSQRT_D64_MM
+; MMR6:       sqrt.d  {{.*}}               # <MCInst #{{[0-9]+}} SQRT_D_MMR6
+  %ret = call double @llvm.sqrt.f64(double %a)
+  ret double %ret
+}
+
+define float @abs_s(float %a) {
+; MIPS32:     abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S
+; MIPS32FP64: abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S
+; MM:         abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S_MM
+; MMFP64:     abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S_MM
+; MMR6:       abs.s  {{.*}}               # <MCInst #{{[0-9]+}} ABS_S_MMR6
+    %ret = call float @llvm.fabs.f32(float %a)
+    ret float %ret
+}
+
+define double @abs_d(double %a) {
+; MIPS32:     abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D32
+; MIPS32FP64: abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D64
+; MM:         abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D32_MM
+; MMFP64:     abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D64_MM
+; MMR6:       abs.d  {{.*}}               # <MCInst #{{[0-9]+}} ABS_D_MMR6
+    %ret = call double @llvm.fabs.f64(double %a)
+    ret double %ret
+}
+
+declare float @llvm.sqrt.f32(float %a)
+declare double @llvm.sqrt.f64(double %a)
+declare float @llvm.fabs.f32(float %a)
+declare double @llvm.fabs.f64(double %a)

test/MC/Disassembler/Mips/micromips32/abs_sqrt.txt

+# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32   -mattr=+micromips < %s | FileCheck %s --check-prefix=MM
+
+0x54 0x0c 0x0a 0x3b
+# MM:         sqrt.s  $f0, $f12
+
+0x54 0x0c 0x03 0x7b
+# MM:         abs.s  $f0, $f12
+
+0x54 0x0c 0x4a 0x3b
+# MM:         sqrt.d  $f0, $f12
+
+0x54 0x0c 0x23 0x7b
+# MM:         abs.d  $f0, $f12

test/MC/Disassembler/Mips/micromips32/abs_sqrt_fp64.txt

+# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32   -mattr=+micromips,+fp64 < %s | FileCheck %s --check-prefix=MMFP64
+
+0x54 0x0c 0x0a 0x3b
+# MMFP64:     sqrt.s  $f0, $f12
+
+0x54 0x0c 0x03 0x7b
+# MMFP64:     abs.s  $f0, $f12
+
+0x54 0x0c 0x4a 0x3b
+# MMFP64:     sqrt.d  $f0, $f12
+
+0x54 0x0c 0x23 0x7b
+# MMFP64:     abs.d  $f0, $f12

test/MC/Disassembler/Mips/mips32/abs_sqrt.txt

+# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 < %s | FileCheck %s --check-prefix=MIPS32
+
+0x46 0x00 0x60 0x04
+# MIPS32:     sqrt.s  $f0, $f12
+
+0x46 0x00 0x60 0x05
+# MIPS32:     abs.s  $f0, $f12
+
+0x46 0x20 0x60 0x04
+# MIPS32:     sqrt.d  $f0, $f12
+
+0x46 0x20 0x60 0x05
+# MIPS32:     abs.d  $f0, $f12

test/MC/Disassembler/Mips/mips32/abs_sqrt_fp64.txt

+# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32   -mattr=+fp64 < %s | FileCheck %s --check-prefix=MIPS32FP64
+
+0x46 0x00 0x60 0x04
+# MIPS32FP64: sqrt.s  $f0, $f12
+
+0x46 0x00 0x60 0x05
+# MIPS32FP64: abs.s  $f0, $f12
+
+0x46 0x20 0x60 0x04
+# MIPS32FP64: sqrt.d  $f0, $f12
+
+0x46 0x20 0x60 0x05
+# MIPS32FP64: abs.d  $f0, $f12

test/MC/Disassembler/Mips/mips32r6/abs_sqrt.txt

+# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s --check-prefix=MMR6
+
+0x54 0x0c 0x0a 0x3b
+# MMR6:       sqrt.s  $f0, $f12
+
+0x54 0x0c 0x03 0x7b
+# MMR6:       abs.s  $f0, $f12
+
+0x54 0x0c 0x4a 0x3b
+# MMR6:       sqrt.d  $f0, $f12
+
+0x54 0x0c 0x23 0x7b
+# MMR6:       abs.d  $f0, $f12

test/MC/Mips/abs_sqrt.s

+# RUN: llvm-mc -arch=mips -mcpu=mips32                           -show-encoding < %s | FileCheck %s --check-prefix=MIPS32
+# RUN: llvm-mc -arch=mips -mcpu=mips32   -mattr=+fp64            -show-encoding < %s | FileCheck %s --check-prefix=MIPS32FP64
+# RUN: llvm-mc -arch=mips -mcpu=mips32   -mattr=+micromips       -show-encoding < %s | FileCheck %s --check-prefix=MM
+# RUN: llvm-mc -arch=mips -mcpu=mips32   -mattr=+micromips,+fp64 -show-encoding < %s | FileCheck %s --check-prefix=MMFP64
+# RUN: llvm-mc -arch=mips -mcpu=mips32r6 -mattr=+micromips       -show-encoding < %s | FileCheck %s --check-prefix=MMR6
+
+sqrt.s  $f0, $f12
+# MIPS32:     sqrt.s  $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
+# MIPS32FP64: sqrt.s  $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
+# MM:         sqrt.s  $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
+# MMFP64:     sqrt.s  $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
+# MMR6:       sqrt.s  $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
+sqrt.d  $f0, $f12
+# MIPS32:     sqrt.d  $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
+# MIPS32FP64: sqrt.d  $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
+# MM:         sqrt.d  $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
+# MMFP64:     sqrt.d  $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
+# MMR6:       sqrt.d  $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
+abs.s $f0, $f12
+# MIPS32:     abs.s  $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
+# MIPS32FP64: abs.s  $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
+# MM:         abs.s  $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
+# MMFP64:     abs.s  $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
+# MMR6:       abs.s  $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
+abs.d  $f0, $f12
+# MIPS32:     abs.d  $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
+# MIPS32FP64: abs.d  $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
+# MM:         abs.d  $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
+# MMFP64:     abs.d  $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
+# MMR6:       abs.d  $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]

test/MC/Mips/micromips/valid.s

 break16 8                   # CHECK: break16 8          # encoding: [0x46,0x88]
 sdbbp16 14                  # CHECK: sdbbp16 14         # encoding: [0x46,0xce]
 lw $3, 32($sp)              # CHECK: lw $3, 32($sp)     # encoding: [0x48,0x68]
 sw $4, 124($sp)             # CHECK: sw $4, 124($sp)    # encoding: [0xc8,0x9f]
 lw $3, 32($gp)              # CHECK: lw $3, 32($gp)     # encoding: [0x65,0x88]
 abs.s $f0, $f2              # CHECK:  abs.s $f0, $f2    # encoding: [0x54,0x02,0x03,0x7b]
                             # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_S_MM
 abs.d $f4, $f6              # CHECK:  abs.d $f4, $f6    # encoding: [0x54,0x86,0x23,0x7b]
-                            # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_MM
+                            # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_D32_MM
 add $9, $6, $7              # CHECK: add $9, $6, $7         # encoding: [0x00,0xe6,0x49,0x10]
 addi $9, $6, 17767          # CHECK: addi $9, $6, 17767     # encoding: [0x11,0x26,0x45,0x67]
 addiu $9, $6, -15001        # CHECK: addiu $9, $6, -15001   # encoding: [0x31,0x26,0xc5,0x67]
 addi $9, $6, 17767          # CHECK: addi $9, $6, 17767     # encoding: [0x11,0x26,0x45,0x67]
 addiu $9, $6, -15001        # CHECK: addiu $9, $6, -15001   # encoding: [0x31,0x26,0xc5,0x67]
 addu $9, $6, $7             # CHECK: addu $9, $6, $7        # encoding: [0x00,0xe6,0x49,0x50]
 sub $9, $6, $7              # CHECK: sub $9, $6, $7         # encoding: [0x00,0xe6,0x49,0x90]
 subu $4, $3, $5             # CHECK: subu $4, $3, $5        # encoding: [0x00,0xa3,0x21,0xd0]