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Differential D41439

[mips] Properly select abs and sqrt instructions
ClosedPublic

Authored by smaksimovic on Dec 20 2017, 6:02 AM.

Details

Reviewers
sdardis
zoran.jovanovic
Commits
rG98749e024989: [mips] Properly select abs and sqrt instructions
rL323184: [mips] Properly select abs and sqrt instructions
Summary
  • Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt
  • Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants
  • Restrict non-micromips abs/sqrt with NotInMicroMips predicate

Diff Detail

Repository
rL LLVM

Event Timeline

smaksimovic created this revision.Dec 20 2017, 6:02 AM
Herald added a subscriber: arichardson. · View Herald TranscriptDec 20 2017, 6:02 AM
sdardis added a comment.Jan 9 2018, 1:50 AM

This looks

lib/Target/Mips/MicroMips32r6InstrInfo.td
1627 ↗(On Diff #127697)

Spaces around the '='.

1655 ↗(On Diff #127697)

Here too.

lib/Target/Mips/MicroMipsInstrFPU.td
96 ↗(On Diff #127697)

Nit, align the "SDPatternOperator [...]" to under the 'string' in the line above, spaces around the '='.

101 ↗(On Diff #127697)

FIXME: This needs to be part of the instruction mapping tables.

197 ↗(On Diff #127697)

Nit: the closing '}' should be aligned with the def or class it's apart of.

lib/Target/Mips/MipsInstrFPU.td
462–464 ↗(On Diff #127697)

Nit, indent this by 2 columns.

test/CodeGen/Mips/abs_sqrt.ll
1 ↗(On Diff #127697)

Modify the existing file test/CodeGen/Mips/llvm-ir/sqrt.ll for the square root tests.

Add test/CodeGen/Mips/llvm-ir/abs.ll for the abs tests.

2 ↗(On Diff #127697)

cpu should be mips32r2.

3–4 ↗(On Diff #127697)

cpu should be mips32r3.

test/MC/Disassembler/Mips/micromips32/abs_sqrt.txt
1 ↗(On Diff #127697)

This should go in test/MC/Disassembler/Mips/micromips32r3/valid.txt and the little endian disassembly in test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

test/MC/Disassembler/Mips/micromips32/abs_sqrt_fp64.txt
1 ↗(On Diff #127697)

This should go in test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt and provide little endian disassembly in test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt.

The -mcpu= should be mips32r3. You should drop the explicit check prefix and use CHECK: for the check lines instead. Also keep the hex and CHECK on the same line, i.e.

0x54 0x0c 0x0a 0x3b
# MMFP64:     sqrt.s  $f0, $f12

Should be:

0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s  $f0, $f12
test/MC/Disassembler/Mips/mips32/abs_sqrt.txt
1 ↗(On Diff #127697)

This file can be entirely dropped, existing disassembly tests cover it.

test/MC/Disassembler/Mips/mips32/abs_sqrt_fp64.txt
1 ↗(On Diff #127697)

Rename this file to valid-fp64.txt and place copies in test/MC/Disassembler/Mips/mips32r{2, 3, 5}/

Also provide little endian disassembly files. You can drop the explicit check prefix and just use 'CHECK'. See our existing disassembly files and copy their style.

test/MC/Disassembler/Mips/mips32r6/abs_sqrt.txt
1 ↗(On Diff #127697)

This file can be dropped as the existing tests cover it.

test/MC/Mips/abs_sqrt.s
1 ↗(On Diff #127697)

Rather than providing this as a new test, you can modify existing tests to cover almost all the variants here.

For the mips32 case, modify or ensure that test/MC/Mips/mips{1, 2, 32, 32r2, 32r3, 32r5}/valid.s produce the non-micromips AFGR64 instruction. If you look at the 'abs.d' case in test/MC/Mips/micromips/valid.s, you'll see how it should look.

I've highlighted the additional changes for this file.

2 ↗(On Diff #127697)

Provide this variant in test/MC/Mips/mips32r{2,3,5}/valid-fp64.s. The cpu should correspond to the directory it's in. Also test which instruction the assembly has determined it is with -show-inst.

3 ↗(On Diff #127697)

Check which instructions are produced from test/MC/Mips/micromips/valid.s with the -show-inst option.

4 ↗(On Diff #127697)

Provide this variant in test/MC/Mips/micromips/valid-fp64.s. Also the cpu should be mips32r3.

5 ↗(On Diff #127697)

Check which instructions are produced from test/MC/Mips/micromips32r6/valid.s with the -show-inst option.

28 ↗(On Diff #127697)

This case is already covered as you've modified test/MC/Mips/micromips/valid.s

smaksimovic updated this revision to Diff 129261.Jan 10 2018, 5:45 AM

Addressed review comments.

I made a rather inconvenient naming change to the MMR6 version of SQRT.
The SQRT_D_MMR6, as it was originally named, came after FSQRT_D64_MM in the match table residing in MipsGenAsmMatcher.inc.
This was not the case with ABS, so it seems that the instructions are ordered by name as well, among other things.
Renamed SQRT_D_MMR6 to ASQRT_D_MMR6. I didn't find another way to force the ordering of records in the match table.

sdardis added a comment.Jan 19 2018, 6:13 AM

This looks

lib/Target/Mips/MicroMips32r6InstrInfo.td
1627–1630 ↗(On Diff #129261)

You can remove the definitions of these instructions from MicroMips32r6 as you have provided the FGR64 definitions in MicroMipsInstrFPU.td and the instructions share the same encodings.

1655–1660 ↗(On Diff #129261)

I've checked this again, you can remove the definition of these instructions from MicroMips32r6InstrInfo.td, as they share the same encoding as the original microMIPS instruction and you have provided the FGR64 definitions in MicroMipsInstrFPU.td.

smaksimovic updated this revision to Diff 130614.Jan 19 2018, 7:19 AM
smaksimovic edited the summary of this revision. (Show Details)

Removed instructions from MicroMips32r6InstrInfo.td

sdardis accepted this revision.Jan 22 2018, 6:36 AM

LGTM.

This revision is now accepted and ready to land.Jan 22 2018, 6:36 AM
Closed by commit rL323184: [mips] Properly select abs and sqrt instructions (authored by smaksimovic). · Explain WhyJan 23 2018, 2:11 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
12 lines
27 lines
8 lines
test/
CodeGen/
Mips/
llvm-ir/
28 lines
29 lines
MC/
Disassembler/
Mips/
micromips32r3/
4 lines
7 lines
7 lines
4 lines
mips32/
7 lines
7 lines
mips32r2/
7 lines
7 lines
mips32r3/
7 lines
7 lines
mips32r5/
7 lines
7 lines
Mips/
micromips/
11 lines
6 lines
micromips32r6/
12 lines
mips1/
8 lines
mips2/
14 lines
mips32/
14 lines
mips32r2/
11 lines
14 lines
mips32r3/
11 lines
14 lines
mips32r5/
11 lines
14 lines

Diff 131010

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Lines
class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>; class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>; class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>; class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>; class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>; class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>; class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>; class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>; class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>; class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>; class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>; class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>; class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0, class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
▲ Show 20 Lines • Show All 845 Lines • ▼ Show 20 Linesclass ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
dag InOperandList = (ins SrcRC:$fs); dag InOperandList = (ins SrcRC:$fs);
string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
InstrItinClass Itinerary = Itin; InstrItinClass Itinerary = Itin;
Format Form = FrmFR; Format Form = FrmFR;
list<Predicate> EncodingPredicates = [HasStdEnc]; list<Predicate> EncodingPredicates = [HasStdEnc];
} }
class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
II_ABS, fabs>;
class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
II_ABS, fabs>;
class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd, class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
FGR32Opnd, II_FLOOR>; FGR32Opnd, II_FLOOR>;
class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd, class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
FGR64Opnd, II_FLOOR>; FGR64Opnd, II_FLOOR>;
class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd, class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
FGR32Opnd, II_FLOOR>; FGR32Opnd, II_FLOOR>;
class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd, class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
AFGR64Opnd, II_FLOOR>; AFGR64Opnd, II_FLOOR>;
▲ Show 20 Lines • Show All 486 Lines • ▼ Show 20 Lines
def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC, def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC, def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC, def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>; defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>; defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC, def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC, def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC, def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC, def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC, def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC, def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC, def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC, def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC, def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC, def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC, def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC, def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6; def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6; def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6; def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6; def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC, def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC, def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 225 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linesdef CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32;
def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd,
II_ROUND>, ROUND_W_FM_MM<1, 0xec>, II_ROUND>, ROUND_W_FM_MM<1, 0xec>,
ISA_MICROMIPS, FGR_32; ISA_MICROMIPS, FGR_32;
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
fsqrt>, ROUND_W_FM_MM<1, 0x28>,
ISA_MICROMIPS, FGR_32;
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
} }
multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> {
def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_32 {
string DecoderNamespace = "MicroMips";
}
// FIXME: This needs to be part of the instruction mapping tables.
def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_64 {
string DecoderNamespace = "MicroMipsFP64";
}
}
defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
} }
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; ABS_FM_MM<0, 0x1>, ISA_MICROMIPS;
def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;
def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesdef FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>,
ISA_MICROMIPS; ISA_MICROMIPS;
def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
FGR32Opnd, II_TRUNC>, FGR32Opnd, II_TRUNC>,
ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS;
def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS;
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS {
string DecoderNamespace = "MicroMips";
}
def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
MFC1_FM_MM<0x40>, ISA_MICROMIPS; MFC1_FM_MM<0x40>, ISA_MICROMIPS;
▲ Show 20 Lines • Show All 154 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 452 Lines • ▼ Show 20 Lines def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
ABSS_FM<0x5, 16>; ABSS_FM<0x5, 16>;
defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
} }
def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
ABSS_FM<0x7, 16>; ABSS_FM<0x7, 16>;
defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
let AdditionalPredicates = [NotInMicroMips] in {
def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
}
// The odd-numbered registers are only referenced when doing loads, // The odd-numbered registers are only referenced when doing loads,
// stores, and moves between floating-point and integer registers. // stores, and moves between floating-point and integer registers.
// When defining instructions, we reference all 32-bit registers, // When defining instructions, we reference all 32-bit registers,
// regardless of register aliasing. // regardless of register aliasing.
/// Move Control Registers From/To CPU Registers /// Move Control Registers From/To CPU Registers
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 444 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/abs.ll

; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define float @abs_s(float %a) {
; MIPS32: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S
; MIPS32FP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S
; MM: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
; MMFP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
; MMR6: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
%ret = call float @llvm.fabs.f32(float %a)
ret float %ret
}
define double @abs_d(double %a) {
; MIPS32: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32
; MIPS32FP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64
; MM: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32_MM
; MMFP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM
; MMR6: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM
%ret = call double @llvm.fabs.f64(double %a)
ret double %ret
}
declare float @llvm.fabs.f32(float %a)
declare double @llvm.fabs.f64(double %a)

llvm/trunk/test/CodeGen/Mips/llvm-ir/sqrt.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define float @sqrt_fn(float %value) #0 { define float @sqrt_fn(float %value) #0 {
entry: entry:
%sqrtf = tail call float @sqrtf(float %value) #0 %sqrtf = tail call float @sqrtf(float %value) #0
ret float %sqrtf ret float %sqrtf
} }
declare float @sqrtf(float) declare float @sqrtf(float)
; CHECK: sqrt.s $f0, $f12 ; CHECK: sqrt.s $f0, $f12
define float @sqrt_s(float %a) {
; MIPS32: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S
; MIPS32FP64: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S
; MM: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM
; MMFP64: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM
; MMR6: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM
%ret = call float @llvm.sqrt.f32(float %a)
ret float %ret
}
define double @sqrt_d(double %a) {
; MIPS32: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D32
; MIPS32FP64: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64
; MM: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D32_MM
; MMFP64: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64_MM
; MMR6: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64_MM
%ret = call double @llvm.sqrt.f64(double %a)
ret double %ret
}
declare float @llvm.sqrt.f32(float %a)
declare double @llvm.sqrt.f64(double %a)

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
0x46 0x9c 0x04 0x00 # CHECK: lwc1 $f2, 4($6) 0x46 0x9c 0x04 0x00 # CHECK: lwc1 $f2, 4($6)
0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10) 0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6) 0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6) 0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6 0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30 0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28 0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8 0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2 0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4 0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6 0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8 0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6 0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30 0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28 0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8 0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12

llvm/trunk/test/MC/Mips/micromips/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -show-encoding -show-inst %s \
# RUN: | FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM

llvm/trunk/test/MC/Mips/micromips/valid.s

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
break16 8 # CHECK: break16 8 # encoding: [0x46,0x88] break16 8 # CHECK: break16 8 # encoding: [0x46,0x88]
sdbbp16 14 # CHECK: sdbbp16 14 # encoding: [0x46,0xce] sdbbp16 14 # CHECK: sdbbp16 14 # encoding: [0x46,0xce]
lw $3, 32($sp) # CHECK: lw $3, 32($sp) # encoding: [0x48,0x68] lw $3, 32($sp) # CHECK: lw $3, 32($sp) # encoding: [0x48,0x68]
sw $4, 124($sp) # CHECK: sw $4, 124($sp) # encoding: [0xc8,0x9f] sw $4, 124($sp) # CHECK: sw $4, 124($sp) # encoding: [0xc8,0x9f]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
abs.s $f0, $f2 # CHECK: abs.s $f0, $f2 # encoding: [0x54,0x02,0x03,0x7b] abs.s $f0, $f2 # CHECK: abs.s $f0, $f2 # encoding: [0x54,0x02,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b] abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32_MM
add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10] add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10]
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67] addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67] addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67] addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67] addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]
addu $9, $6, $7 # CHECK: addu $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x50] addu $9, $6, $7 # CHECK: addu $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x50]
sub $9, $6, $7 # CHECK: sub $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x90] sub $9, $6, $7 # CHECK: sub $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x90]
subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0] subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0]
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llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b] cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b]
cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b] cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b]
cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b] cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b]
cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b] cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b]
cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b] cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b]
cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b] cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b] cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b] cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
abs.s $f3, $f5 # CHECK: abs.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x7b] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
abs.d $f2, $f4 # CHECK: abs.d $f2, $f4 # encoding: [0x54,0x44,0x23,0x7b] # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b] floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b]
floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b] floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b]
floor.w.s $f3, $f5 # CHECK: floor.w.s $f3, $f5 # encoding: [0x54,0x65,0x0b,0x3b] floor.w.s $f3, $f5 # CHECK: floor.w.s $f3, $f5 # encoding: [0x54,0x65,0x0b,0x3b]
floor.w.d $f2, $f4 # CHECK: floor.w.d $f2, $f4 # encoding: [0x54,0x44,0x4b,0x3b] floor.w.d $f2, $f4 # CHECK: floor.w.d $f2, $f4 # encoding: [0x54,0x44,0x4b,0x3b]
ceil.l.s $f3, $f5 # CHECK: ceil.l.s $f3, $f5 # encoding: [0x54,0x65,0x13,0x3b] ceil.l.s $f3, $f5 # CHECK: ceil.l.s $f3, $f5 # encoding: [0x54,0x65,0x13,0x3b]
ceil.l.d $f2, $f4 # CHECK: ceil.l.d $f2, $f4 # encoding: [0x54,0x44,0x53,0x3b] ceil.l.d $f2, $f4 # CHECK: ceil.l.d $f2, $f4 # encoding: [0x54,0x44,0x53,0x3b]
ceil.w.s $f3, $f5 # CHECK: ceil.w.s $f3, $f5 # encoding: [0x54,0x65,0x1b,0x3b] ceil.w.s $f3, $f5 # CHECK: ceil.w.s $f3, $f5 # encoding: [0x54,0x65,0x1b,0x3b]
ceil.w.d $f2, $f4 # CHECK: ceil.w.d $f2, $f4 # encoding: [0x54,0x44,0x5b,0x3b] ceil.w.d $f2, $f4 # CHECK: ceil.w.d $f2, $f4 # encoding: [0x54,0x44,0x5b,0x3b]
trunc.l.s $f3, $f5 # CHECK: trunc.l.s $f3, $f5 # encoding: [0x54,0x65,0x23,0x3b] trunc.l.s $f3, $f5 # CHECK: trunc.l.s $f3, $f5 # encoding: [0x54,0x65,0x23,0x3b]
trunc.l.d $f2, $f4 # CHECK: trunc.l.d $f2, $f4 # encoding: [0x54,0x44,0x63,0x3b] trunc.l.d $f2, $f4 # CHECK: trunc.l.d $f2, $f4 # encoding: [0x54,0x44,0x63,0x3b]
trunc.w.s $f3, $f5 # CHECK: trunc.w.s $f3, $f5 # encoding: [0x54,0x65,0x2b,0x3b] trunc.w.s $f3, $f5 # CHECK: trunc.w.s $f3, $f5 # encoding: [0x54,0x65,0x2b,0x3b]
trunc.w.d $f2, $f4 # CHECK: trunc.w.d $f2, $f4 # encoding: [0x54,0x44,0x6b,0x3b] trunc.w.d $f2, $f4 # CHECK: trunc.w.d $f2, $f4 # encoding: [0x54,0x44,0x6b,0x3b]
sqrt.s $f3, $f5 # CHECK: sqrt.s $f3, $f5 # encoding: [0x54,0x65,0x0a,0x3b] sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
sqrt.d $f2, $f4 # CHECK: sqrt.d $f2, $f4 # encoding: [0x54,0x44,0x4a,0x3b] # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM
rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b]
rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b]
lw $3, -260($gp) # CHECK: lw $3, -260($gp) # encoding: [0xfc,0x7c,0xfe,0xfc] lw $3, -260($gp) # CHECK: lw $3, -260($gp) # encoding: [0xfc,0x7c,0xfe,0xfc]
lw $3, -256($gp) # CHECK: lw $3, -256($gp) # encoding: [0x65,0xc0] lw $3, -256($gp) # CHECK: lw $3, -256($gp) # encoding: [0x65,0xc0]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 252($gp) # CHECK: lw $3, 252($gp) # encoding: [0x65,0xbf] lw $3, 252($gp) # CHECK: lw $3, 252($gp) # encoding: [0x65,0xbf]
lw $3, 256($gp) # CHECK: lw $3, 256($gp) # encoding: [0xfc,0x7c,0x01,0x00] lw $3, 256($gp) # CHECK: lw $3, 256($gp) # encoding: [0xfc,0x7c,0x01,0x00]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66] lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
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llvm/trunk/test/MC/Mips/mips1/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips1 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
abs.s $f9,$f16 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
addu $9,$a0,$a2 addu $9,$a0,$a2
▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips2/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips2 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
abs.s $f9,$f16 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
sqrt.s $f0,$f1 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
abs.s $f9,$f16 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
sqrt.s $f0,$f1 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
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llvm/trunk/test/MC/Mips/mips32r2/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64

llvm/trunk/test/MC/Mips/mips32r2/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r2 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
abs.s $f9,$f16 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
sqrt.s $f0,$f1 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r3/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64

llvm/trunk/test/MC/Mips/mips32r3/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r3 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
abs.s $f9,$f16 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
sqrt.s $f0,$f1 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r5/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64

llvm/trunk/test/MC/Mips/mips32r5/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r5 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
abs.s $f9,$f16 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
sqrt.s $f0,$f1 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
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