[DAG] Improve SimplifyDemandedBits ISD::AND handling through bitcasts (PR34620)

[RKSimon]

Summary

Instead of just using isConstOrConstSplat to get constant data, use computeKnownBits which can peek through bitcasts.

Additionally, if all of the demanded bits are known on RHS, try to simplify LHS.

[RKSimon]

Abandoning, D41643 looks a better solution

lib/CodeGen/SelectionDAG/TargetLowering.cpp

for (SDValue SrcOp : Op->ops()) {
       }
 
       // Known bits are the values that are shared by every element.
       // TODO: support per-element known bits.
       Known.One &= Known2.One;
       Known.Zero &= Known2.Zero;
     }
     return false;   // Don't fall through, will infinitely loop.
-  case ISD::AND:
+  case ISD::AND: {
+    KnownBits RHSKnown;
+    // Do not increment Depth here; that can cause an infinite loop.
+    TLO.DAG.computeKnownBits(Op.getOperand(1), RHSKnown, Depth);
+
     // If the RHS is a constant, check to see if the LHS would be zero without
     // using the bits from the RHS.  Below, we use knowledge about the RHS to
     // simplify the LHS, here we're using information from the LHS to simplify
     // the RHS.
-    if (ConstantSDNode *RHSC = isConstOrConstSplat(Op.getOperand(1))) {
+    if (RHSKnown.isConstant()) {
       SDValue Op0 = Op.getOperand(0);
       KnownBits LHSKnown;
       // Do not increment Depth here; that can cause an infinite loop.
       TLO.DAG.computeKnownBits(Op0, LHSKnown, Depth);
-      // If the LHS already has zeros where RHSC does, this and is dead.
-      if ((LHSKnown.Zero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
+      // If the LHS already has zeros where RHS does, this and is dead.
+      if ((LHSKnown.Zero & NewMask) == (RHSKnown.Zero & NewMask))
         return TLO.CombineTo(Op, Op0);
 
       // If any of the set bits in the RHS are known zero on the LHS, shrink
       // the constant.
       if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & NewMask, TLO))
         return true;
 
       // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
       // constant, but if this 'and' is only clearing bits that were just set by
       // the xor, then this 'and' can be eliminated by shrinking the mask of
       // the xor. For example, for a 32-bit X:
       // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
       if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
-          LHSKnown.One == ~RHSC->getAPIntValue()) {
+          LHSKnown.One == RHSKnown.Zero) {
         SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, Op.getValueType(),
                                       Op0.getOperand(0), Op.getOperand(1));
         return TLO.CombineTo(Op, Xor);
       }
     }
 
+    // If all of the demanded bits are known on RHS, try to simplify LHS.
+    if (NewMask.isSubsetOf(RHSKnown.Zero | RHSKnown.One))
+      if (SimplifyDemandedBits(Op.getOperand(0), NewMask & RHSKnown.One, Known,
+                               TLO, Depth + 1))
+        return true;
+
     if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
       return true;
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
     if (SimplifyDemandedBits(Op.getOperand(0), ~Known.Zero & NewMask,
                              Known2, TLO, Depth+1))
       return true;
     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
 
case ISD::AND: {
     if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
       return true;
 
     // Output known-1 bits are only known if set in both the LHS & RHS.
     Known.One &= Known2.One;
     // Output known-0 are known to be clear if zero in either the LHS | RHS.
     Known.Zero |= Known2.Zero;
     break;
+  }
   case ISD::OR:
     if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
       return true;
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
     if (SimplifyDemandedBits(Op.getOperand(0), ~Known.One & NewMask,
                              Known2, TLO, Depth+1))
       return true;
     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");

test/CodeGen/X86/combine-and.ll

 ;
 
 ; PR34620 - redundant PAND after vector shift of a byte vector (PSRLW)
 define <16 x i8> @PR34620(<16 x i8> %a0, <16 x i8> %a1) {
 ; CHECK-LABEL: PR34620:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    psrlw $1, %xmm0
 ; CHECK-NEXT:    pand {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    pand {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    paddb %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = lshr <16 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = add <16 x i8> %2, %a1
   ret <16 x i8> %3
 }