[Nios2] Arithmetic instructions for R1 and R2 ISA.

[belickim]

Summary

This commit enables some of the arithmetic instructions for Nios2 ISA (for both R1 and R2 revisions), implements facilities required to emit those instructions and provides LIT tests for added instructions.

[AndreiGrischenko]

lib/Target/Nios2/Nios2InstrInfo.td

78

Do you need this commented out?

test/CodeGen/Nios2/add-sub.ll

2

I think it makes sense to add test for R2 version as well, because you are introducing R2 in this patch. I know that you will not get difference in assembly among both versions, but we need to be sure in that.

[belickim]

Added R2 run to LIT tests, fixed a typo with unintended comment.

[hfinkel]

lib/Target/Nios2/Nios2ISelLowering.cpp

201

Merge init with the declaration on the previous line.

207

llvm_unreachable takes a string describing the problem.

lib/Target/Nios2/Nios2InstrInfo.cpp

53

Is this function being called without a valid destination or source register?

lib/Target/Nios2/Nios2InstrInfo.td

88

Would you really want to rematerialize division on this architecture? Only declare these as rematerializable if they're cheaper than a spill/restore.

[belickim]

Thanks for the review Hal. When I was addressing the things that you pointed out I found that entire analyzeReturn method is already implemented in LLVM, which allowed me to remove some code.

[hfinkel]

test/CodeGen/Nios2/add-sub.ll

7

Aren't all of the registers here fixed by the ABI? If so, check for them explicitly instead of matching any register.

[belickim]

Thanks for another comment Hal, I've updated the test accordingly.

[hfinkel]

Are you planning to soon introduce an asm parser and disassembler so that you can test the encodings? I recommend doing this early do that you can test those along the way.

lib/Target/Nios2/Nios2InstrInfo.cpp

53

We generally write this as:

BuildMI(MBB, I, DL, get(opc), DestReg)
  .addReg(Nios2::ZERO);
  .addReg(SrcReg, getKillRegState(KillSrc));

[AndreiGrischenko]

Are you planning to soon introduce an asm parser and disassembler so that you can test the encodings? I recommend doing this early do that you can test those along the way.

Yes, we plan to support asm parser in disassembler, but I would not say these were nearby plans. Currently we can just generate assembler and then use GCC as with Nios2 support to generate object-files. But I'm OK with your recommendation, I think we can focus on that before continue committing new instructions.

[belickim]

I've fixed the coding style issue in Nios2InstrInfo::copyPhysReg.

[hfinkel]

LGTM

lib/Target/Nios2/Nios2InstrInfo.cpp

50

You can now drop the MachineInstrBuilder MIB = part too.

[belickim]

Thank you Hal, I removed the unused variable.

lib/Target/Nios2/Nios2ISelLowering.cpp

 #include "Nios2GenCallingConv.inc"
 
 SDValue
 Nios2TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                  bool IsVarArg,
                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
                                  const SmallVectorImpl<SDValue> &OutVals,
                                  const SDLoc &DL, SelectionDAG &DAG) const {
+  // CCValAssign - represent the assignment of
+  // the return value to a location
+  SmallVector<CCValAssign, 16> RVLocs;
+  MachineFunction &MF = DAG.getMachineFunction();
+
+  // CCState - Info about the registers and stack slot.
+  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
+  // Analyze return values.
+  CCInfo.CheckReturn(Outs, RetCC_Nios2EABI);
 
+  SDValue Flag;
   SmallVector<SDValue, 4> RetOps(1, Chain);
 
+  // Copy the result values into the output registers.
+  for (unsigned i = 0; i != RVLocs.size(); ++i) {
+    SDValue Val = OutVals[i];
+    CCValAssign &VA = RVLocs[i];
+    assert(VA.isRegLoc() && "Can only return in registers!");
+
+    if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
+      Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
+
+    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
+
+    // Guarantee that all emitted copies are stuck together with flags.
+    Flag = Chain.getValue(1);
+    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
+  }
+
+  if (Flag.getNode())
+    RetOps.push_back(Flag);
+
   return DAG.getNode(Nios2ISD::Ret, DL, MVT::Other, RetOps);
 }
 
 // addLiveIn - This helper function adds the specified physical register to the
 // MachineFunction as a live in value.  It also creates a corresponding
 // virtual register for it.
 static unsigned addLiveIn(MachineFunction &MF, unsigned PReg,
                           const TargetRegisterClass *RC) {
const char *Nios2TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case Nios2ISD::Hi:
     return "Nios2ISD::Hi";
   case Nios2ISD::Lo:
     return "Nios2ISD::Lo";
   case Nios2ISD::Ret:
     return "Nios2ISD::Ret";
   }
   return nullptr;
 }

lib/Target/Nios2/Nios2InstrFormats.td

 
 // Format specifies the encoding used by the instruction.  This is part of the
 // ad-hoc solution used to emit machine instruction encodings by our machine
 // code emitter.
 class Format<bits<6> val> {
   bits<6> Value = val;
 }
 
-def Pseudo : Format<0>;
-def FrmI : Format<1>;
-def FrmR : Format<2>;
-def FrmJ : Format<3>;
-def FrmOther : Format<4>; // Instruction w/ a custom format
+def Pseudo     : Format<0>;
+// Nios2 R1 instr formats:
+def FrmI       : Format<1>;
+def FrmR       : Format<2>;
+def FrmJ       : Format<3>;
+def FrmOther   : Format<4>;  // Instruction w/ a custom format
+// Nios2 R2 instr 32-bit formats:
+def FrmL26     : Format<5>;  // corresponds to J format in R1
+def FrmF2I16   : Format<6>;  // corresponds to I format in R1
+def FrmF2X4I12 : Format<7>;
+def FrmF1X4I12 : Format<8>;
+def FrmF1X4L17 : Format<9>;
+def FrmF3X6L5  : Format<10>; // corresponds to R format in R1
+def FrmF2X6L10 : Format<11>;
+def FrmF3X6    : Format<12>; // corresponds to R format in R1
+def FrmF3X8    : Format<13>; // corresponds to custom format in R1
+// Nios2 R2 instr 16-bit formats:
+def FrmI10     : Format<14>;
+def FrmT1I7    : Format<15>; 
+def FrmT2I4    : Format<16>;
+def FrmT1X1I6  : Format<17>;
+def FrmX1I7    : Format<18>;
+def FrmL5I4X1  : Format<19>;
+def FrmT2X1L3  : Format<20>;
+def FrmT2X1I3  : Format<21>;
+def FrmT3X1    : Format<22>;
+def FrmT2X3    : Format<23>;
+def FrmF1X1    : Format<24>;
+def FrmX2L5    : Format<25>;
+def FrmF1I5    : Format<26>;
+def FrmF2      : Format<27>;
+
+//===----------------------------------------------------------------------===//
+// Instruction Predicates:
+//===----------------------------------------------------------------------===//
 
-def isNios2r1  : Predicate<"Subtarget->isNios2r1()">;
-def isNios2r2  : Predicate<"Subtarget->isNios2r2()">;
+def isNios2r1 : Predicate<"Subtarget->isNios2r1()">;
+def isNios2r2 : Predicate<"Subtarget->isNios2r2()">;
 
 class PredicateControl {
   // Predicates related to specific target CPU features
   list<Predicate> FeaturePredicates = [];
   // Predicates for the instruction group membership in given ISA
   list<Predicate> InstrPredicates = [];
   
   list<Predicate> Predicates = !listconcat(FeaturePredicates, InstrPredicates);
class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
          InstrItinClass itin>:
       Nios2R1Inst32<outs, ins, asmstr, pattern, itin, FrmJ> {
   bits<26> addr;
   let Opcode = op;
   let Inst{31-6} = addr;
 }
 
 //===----------------------------------------------------------------------===//
+// Format F3X6 (R2) instruction : <|opx|RSV|C|B|A|opcode|>
+//===----------------------------------------------------------------------===//
+
+class F3X6<bits<6> opx, dag outs, dag ins, string asmstr, list<dag> pattern,
+           InstrItinClass itin>:
+      Nios2R2Inst32<outs, ins, asmstr, pattern, itin, FrmF3X6> {
+  bits<5> rC;
+  bits<5> rB;
+  bits<5> rA;
+  bits<5> rsv = 0;
+
+  let Opcode = 0x20; /* opcode is always 0x20 (OPX group) for F3X6 instr. */
+
+  let Inst{31-26} = opx; /* opx stands for opcode extension */
+  let Inst{25-21} = rsv;
+  let Inst{20-16} = rC;
+  let Inst{15-11} = rB;
+  let Inst{10-6}  = rA;
+}
+
+//===----------------------------------------------------------------------===//
 // Multiclasses for common instructions of both R1 and R2:
 //===----------------------------------------------------------------------===//
 
 // Multiclass for instructions that have R format in R1 and F3X6 format in R2
 // and their opx values differ between R1 and R2
 multiclass CommonInstr_R_F3X6_opx<bits<6> opxR1, bits<6> opxR2, dag outs,
                                   dag ins, string asmstr, list<dag> pattern,
                                   InstrItinClass itin> {
   def NAME#_R1 : FR<opxR1, outs, ins, asmstr, pattern, itin>;
+  def NAME#_R2 : F3X6<opxR2, outs, ins, asmstr, pattern, itin>;
 }
 
 // Multiclass for instructions that have R format in R1 and F3X6 format in R2
 // and their opx values are the same in R1 and R2
 multiclass CommonInstr_R_F3X6<bits<6> opx, dag outs, dag ins, string asmstr,
                               list<dag> pattern, InstrItinClass itin> :
   CommonInstr_R_F3X6_opx<opx, opx, outs, ins, asmstr, pattern, itin>;
 

lib/Target/Nios2/Nios2InstrInfo.h

public:
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
   const Nios2RegisterInfo &getRegisterInfo() const { return RI; };
 
   bool expandPostRAPseudo(MachineInstr &MI) const override;
+
+  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
+                   bool KillSrc) const override;
 };
 } // namespace llvm
 
 #endif

lib/Target/Nios2/Nios2InstrInfo.cpp

bool Nios2InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   case Nios2::RetRA:
     BuildMI(MBB, MI, MI.getDebugLoc(), get(Nios2::RET_R1)).addReg(Nios2::RA);
     break;
   }
 
   MBB.erase(MI);
   return true;
 }
+
+void Nios2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+                                 MachineBasicBlock::iterator I,
+                                 const DebugLoc &DL, unsigned DestReg,
+                                 unsigned SrcReg, bool KillSrc) const {
+  unsigned opc = Subtarget.hasNios2r2() ? Nios2::ADD_R2 : Nios2::ADD_R1;
+  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(opc));
+  MIB.addReg(DestReg, RegState::Define);
+  MIB.addReg(Nios2::ZERO);
+  MIB.addReg(SrcReg, getKillRegState(KillSrc));
+}

lib/Target/Nios2/Nios2InstrInfo.td

 def simm16     : Operand<i32> {
   let DecoderMethod= "DecodeSimm16";
 }
 
 // Node immediate fits as 16-bit sign extended on target immediate.
 // e.g. addi, andi
 def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
 
+// Custom return SDNode
+def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
+    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+
 //===----------------------------------------------------------------------===//
 // Instructions specific format
 //===----------------------------------------------------------------------===//
 
 // Arithmetic and logical instructions with 2 registers and 16-bit immediate
 // value.
 multiclass ArithLogicRegImm16<bits<6> op, string mnemonic, SDNode opNode,
                               Operand immOp, PatLeaf immType>:
            CommonInstr_I_F2I16<op, (outs CPURegs:$rB),
                          (ins CPURegs:$rA, immOp:$imm),
                                !strconcat(mnemonic, "\t$rB, $rA, $imm"),
                                [(set CPURegs:$rB,
                (opNode CPURegs:$rA, immType:$imm))],
                                IIAlu>;
 
+// Arithmetic and logical instructions with 3 register operands.
+// Defines R1 and R2 instruction at the same time.
+multiclass ArithLogicReg<bits<6> opx, string mnemonic,
+                         SDNode opNode>:
+  CommonInstr_R_F3X6<opx, (outs CPURegs:$rC),
+                     (ins CPURegs:$rA, CPURegs:$rB),
+                     !strconcat(mnemonic, "\t$rC, $rA, $rB"),
+                     [(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
+                     IIAlu>;
+
 multiclass Return<bits<6> opx, dag outs, dag ins, string mnemonic> {
   let rB = 0, rC = 0,
       isReturn = 1,
       isCodeGenOnly = 1,
       hasCtrlDep = 1,
       hasExtraSrcRegAllocReq = 1 in {
     defm NAME# : CommonInstr_R_F3X6<opx, outs, ins, mnemonic, [], IIBranch>;
   }
 }
 
-// Custom return SDNode
-def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
-    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-
 //===----------------------------------------------------------------------===//
 // Nios2 Instructions
 //===----------------------------------------------------------------------===//
 
+/// Arithmetic instructions operating on registers.
+let isCommutable = 1 ,
+    isReMaterializable = 1 in {
+  defm ADD    : ArithLogicReg<0x31, "add",    add>;
+  defm AND    : ArithLogicReg<0x0e, "and",    and>;
+  defm OR     : ArithLogicReg<0x16, "or",     or>;
+  defm XOR    : ArithLogicReg<0x1e, "xor",    xor>;
+  defm MUL    : ArithLogicReg<0x27, "mul",    mul>;
+}
+
+let isReMaterializable = 1 in {
+  defm SUB    : ArithLogicReg<0x39, "sub",    sub>;
+}
+
+defm DIVU : ArithLogicReg<0x24, "divu",   udiv>;
+defm DIV  : ArithLogicReg<0x25, "div",    sdiv>;
+
+defm SLL : ArithLogicReg<0x13, "sll",  shl>;
+defm SRL : ArithLogicReg<0x1b, "srl",  srl>;
+defm SRA : ArithLogicReg<0x3b, "sra",  sra>;
+
 /// Arithmetic Instructions (ALU Immediate)
 defm ADDI  : ArithLogicRegImm16<0x04, "addi",  add, simm16, immSExt16>;
 
 // Returns:
 defm RET  : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
 
 //===----------------------------------------------------------------------===//
 // Pseudo instructions
 //===----------------------------------------------------------------------===//
 
 // Return RA.
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
 def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;

test/CodeGen/Nios2/add-sub.ll

+; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
+; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
+
+define i32 @add_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: add_reg:
+; CHECK:   add {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = add i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @sub_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: sub_reg:
+; CHECK:   sub {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = sub i32 %a, %b
+  ret i32 %c
+}
+

test/CodeGen/Nios2/mul-div.ll

+; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
+; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
+
+define i32 @mul_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: mul_reg:
+; CHECK:   mul {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = mul i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @div_signed(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: div_signed:
+; CHECK:   div {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = sdiv i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @div_unsigned(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: div_unsigned:
+; CHECK:   divu {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = udiv i32 %a, %b
+  ret i32 %c
+}
+

test/CodeGen/Nios2/shift-rotate.ll

+; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
+; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
+
+define i32 @sll_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: sll_reg:
+; CHECK:   sll {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = shl i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @srl_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: srl_reg:
+; CHECK:   srl {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = lshr i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @sra_reg(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: sra_reg:
+; CHECK:   sra {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+  %c = ashr i32 %a, %b
+  ret i32 %c
+}