[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output

[thegameg]

Summary

Work towards the unification of MIR and debug output by printing %const.0 + 8 instead of <cp#0+8> and %const.0 - 8 instead of <cp#-8>.

Only debug syntax is affected.

[MatzeB]

LGTM, bonus points for extending the MIRLangRef.rst

[thegameg]

I went ahead and committed also:

• r320566: [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug info
• r320565: [CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug info

which are pretty similar.

docs/MIRLangRef.rst

 
 .. code-block:: text
 
     %1 = COPY %0:sub_8bit
 
 The names of the subregister indices are target specific, and are typically
 defined in the target's ``*RegisterInfo.td`` file.
 
+Constant Pool Indices
+^^^^^^^^^^^^^^^^^^^^^
+
+A constant pool index (CPI) operand is printed using its index in the
+function's ``MachineConstantPool`` and an offset.
+
+For example, a CPI with the index 1 and offset 8:
+
+.. code-block:: text
+
+    %1:gr64 = MOV64ri %const.1 + 8
+
+For a CPI with the index 0 and offset -12:
+
+.. code-block:: text
+
+    %1:gr64 = MOV64ri %const.0 - 12
+
+A constant pool entry is bound to a LLVM IR ``Constant`` or a target-specific
+``MachineConstantPoolValue``. When serializing all the function's constants the
+following format is used:
+
+.. code-block:: text
+
+    constants:
+      - id:               <index>
+        value:            <value>
+        alignment:        <alignment>
+        isTargetSpecific: <target-specific>
+
+where ``<index>`` is a 32-bit unsigned integer, ``<value>`` is a `LLVM IR Constant
+<https://www.llvm.org/docs/LangRef.html#constants>`_, alignment is a 32-bit
+unsigned integer, and ``<target-specific>`` is either true or false.
+
+Example:
+
+.. code-block:: text
+
+    constants:
+      - id:               0
+        value:            'double 3.250000e+00'
+        alignment:        8
+      - id:               1
+        value:            'g-(LPC0+8)'
+        alignment:        4
+        isTargetSpecific: true
+
 Global Value Operands
 ^^^^^^^^^^^^^^^^^^^^^
 
 The global value machine operands reference the global values from the
 :ref:`embedded LLVM IR module <embedded-module>`.
 The example below shows an instance of the X86 ``MOV64rm`` instruction that has
 a global value operand named ``G``:
 

 .. TODO: Describe the syntax for the bundled instructions.
 .. TODO: Describe the syntax for virtual register YAML definitions.
 .. TODO: Describe the machine function's YAML flag attributes.
 .. TODO: Describe the syntax for the external symbol and register
    mask machine operands.
 .. TODO: Describe the frame information YAML mapping.
 .. TODO: Describe the syntax of the stack object machine operands and their
    YAML definitions.
-.. TODO: Describe the syntax of the constant pool machine operands and their
-   YAML definitions.
 .. TODO: Describe the syntax of the jump table machine operands and their
    YAML definitions.
 .. TODO: Describe the syntax of the block address machine operands.
 .. TODO: Describe the syntax of the CFI index machine operands.
 .. TODO: Describe the syntax of the metadata machine operands, and the
    instructions debug location attribute.
 .. TODO: Describe the syntax of the target index machine operands.
 .. TODO: Describe the syntax of the register live out machine operands.
 .. TODO: Describe the syntax of the machine memory operands.

lib/CodeGen/MIRPrinter.cpp

void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   case MachineOperand::MO_Immediate:
     if (MI.isOperandSubregIdx(OpIdx)) {
       MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
       break;
     }
     LLVM_FALLTHROUGH;
   case MachineOperand::MO_Register:
   case MachineOperand::MO_CImmediate:
-  case MachineOperand::MO_MachineBasicBlock: {
+  case MachineOperand::MO_MachineBasicBlock:
+  case MachineOperand::MO_ConstantPoolIndex: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
     Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies,
              TiedOperandIdx, TRI, TII);
     break;
   }
   case MachineOperand::MO_FPImmediate:
     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
   case MachineOperand::MO_FrameIndex:
     printStackObjectReference(Op.getIndex());
     break;
-  case MachineOperand::MO_ConstantPoolIndex:
-    OS << "%const." << Op.getIndex();
-    printOffset(Op.getOffset());
-    break;
   case MachineOperand::MO_TargetIndex:
     OS << "target-index(";
     if (const auto *Name =
             getTargetIndexName(*Op.getParent()->getMF(), Op.getIndex()))
       OS << Name;
     else
       OS << "<unknown>";
     OS << ')';

lib/CodeGen/MachineOperand.cpp

static void tryToGetTargetInfo(const MachineOperand &MO,
                                const TargetRegisterInfo *&TRI,
                                const TargetIntrinsicInfo *&IntrinsicInfo) {
   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
     TRI = MF->getSubtarget().getRegisterInfo();
     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
   }
 }
 
+static void printOffset(raw_ostream &OS, int64_t Offset) {
+  if (Offset == 0)
+    return;
+  if (Offset < 0) {
+    OS << " - " << -Offset;
+    return;
+  }
+  OS << " + " << Offset;
+}
+
 void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
                                     const TargetRegisterInfo *TRI) {
   OS << "%subreg.";
   if (TRI)
     OS << TRI->getSubRegIndexName(Index);
   else
     OS << Index;
 }
case MachineOperand::MO_FPImmediate:
     break;
   case MachineOperand::MO_MachineBasicBlock:
     OS << printMBBReference(*getMBB());
     break;
   case MachineOperand::MO_FrameIndex:
     OS << "<fi#" << getIndex() << '>';
     break;
   case MachineOperand::MO_ConstantPoolIndex:
-    OS << "<cp#" << getIndex();
-    if (getOffset())
-      OS << "+" << getOffset();
-    OS << '>';
+    OS << "%const." << getIndex();
+    printOffset(OS, getOffset());
     break;
   case MachineOperand::MO_TargetIndex:
     OS << "<ti#" << getIndex();
     if (getOffset())
       OS << "+" << getOffset();
     OS << '>';
     break;
   case MachineOperand::MO_JumpTableIndex:

test/CodeGen/ARM/subreg-remat.ll

 ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
 target triple = "thumbv7-apple-ios"
 ; <rdar://problem/10032939>
 ;
 ; The vector %v2 is built like this:
 ;
 ;   %6:ssub_1 = ...
-;   %6:ssub_0 = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
+;   %6:ssub_0 = VLDRS %const.0, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
 ;
 ; When %6 spills, the VLDRS constant pool load cannot be rematerialized
 ; since it implicitly reads the ssub_1 sub-register.
 ;
 ; CHECK: f1
 ; CHECK: vmov    d0, r0, r0
 ; CHECK: vldr s1, LCPI
 ; The vector must be spilled:
define void @f1(float %x, <2 x float>* %p) {
   store <2 x float> %v2, <2 x float>* %p, align 8
   ret void
 }
 
 ; On the other hand, when the partial redef doesn't read the full register
 ; because the bits are undef, we should rematerialize.  The vector is now built
 ; like this:
 ;
-;   %2:ssub_0 = VLDRS <cp#0>, 0, pred:14, pred:%noreg, implicit-def %2; mem:LD4[ConstantPool]
+;   %2:ssub_0 = VLDRS %const.0, 0, pred:14, pred:%noreg, implicit-def %2; mem:LD4[ConstantPool]
 ;
 ; The extra <imp-def> operand indicates that the instruction fully defines the
 ; virtual register.  It doesn't read the old value.
 ;
 ; CHECK: f2
 ; CHECK: vldr s0, LCPI
 ; The vector must not be spilled:
 ; CHECK-NOT: vstr

test/CodeGen/X86/2010-05-12-FastAllocKills.ll

 ; RUN: llc -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs < %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin"
 
 ; This test causes a virtual FP register to be redefined while it is live:
 ;%bb.5: derived from LLVM BB %bb10
 ;    Predecessors according to CFG: %bb.4 %bb.5
 ; %reg1024 = MOV_Fp8080 %reg1034
-; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
+; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
 ; %reg1034 = MOV_Fp8080 %reg1025
 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
 ; JMP_4 <%bb.5>
 ;    Successors according to CFG: %bb.5
 ;
 ; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
 ;%bb.5: derived from LLVM BB %bb10
 ;    Predecessors according to CFG: %bb.4 %bb.5
 ; %fp0 = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
 ; %fp1 = MOV_Fp8080 killed %fp0
-; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
+; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
 ; %fp0 = MOV_Fp8080 %fp2
 ; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
 ; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
 ; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
 ; JMP_4 <%bb.5>
 ;    Successors according to CFG: %bb.5
 

unittests/CodeGen/MachineOperandTest.cpp

TEST(MachineOperandTest, PrintSubRegIndex) {
   // TRI and IntrinsicInfo we can print the operand as a subreg index.
   std::string str;
   raw_string_ostream OS(str);
   ModuleSlotTracker DummyMST(nullptr);
   MachineOperand::printSubregIdx(OS, MO.getImm(), nullptr);
   ASSERT_TRUE(OS.str() == "%subreg.3");
 }
 
+TEST(MachineOperandTest, PrintCPI) {
+  // Create a MachineOperand with a constant pool index and print it.
+  MachineOperand MO = MachineOperand::CreateCPI(0, 8);
+
+  // Checking some preconditions on the newly created
+  // MachineOperand.
+  ASSERT_TRUE(MO.isCPI());
+  ASSERT_TRUE(MO.getIndex() == 0);
+  ASSERT_TRUE(MO.getOffset() == 8);
+
+  // Print a MachineOperand containing a constant pool index and a positive
+  // offset.
+  std::string str;
+  {
+    raw_string_ostream OS(str);
+    MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+    ASSERT_TRUE(OS.str() == "%const.0 + 8");
+  }
+
+  str.clear();
+
+  MO.setOffset(-12);
+
+  // Print a MachineOperand containing a constant pool index and a negative
+  // offset.
+  {
+    raw_string_ostream OS(str);
+    MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+    ASSERT_TRUE(OS.str() == "%const.0 - 12");
+  }
+}
+
 } // end namespace