[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output

[thegameg]

Summary

Work towards the unification of MIR and debug output by printing %stack.0 instead of <fi#0>, and %fixed-stack.0 instead of <fi#-4> (supposing there are 4 fixed stack objects).

Only debug syntax is affected.

[MatzeB]

LGTM

include/llvm/CodeGen/MachineOperand.h

230–232

Make FrameIndex unsigned, to make it clear that we don't have the same negative/positive encoding scheme here that MachineFrameInfo uses?

include/llvm/CodeGen/MachineOperand.h

public:
   /// The MachineOperand copy constructor also copies ParentMI, expecting the
   /// original to be deleted. If a MachineOperand is ever stored outside a
   /// MachineInstr, the parent pointer must be cleared.
   ///
   /// Never call clearParent() on an operand in a MachineInstr.
   ///
   void clearParent() { ParentMI = nullptr; }
 
+  /// Print a stack object reference.
+  static void printStackObjectReference(raw_ostream &OS, int FrameIndex,
+                                        bool IsFixed, StringRef Name);
+
   /// Print the MachineOperand to \p os.
   /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
   /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
   /// function will try to pick it up from the parent.
   void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
 
   /// More complex way of printing a MachineOperand.

lib/CodeGen/MIRPrinter.cpp

void MIPrinter::printIRValueReference(const Value &V) {
   printIRSlotNumber(OS, MST.getLocalSlot(&V));
 }
 
 void MIPrinter::printStackObjectReference(int FrameIndex) {
   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
   assert(ObjectInfo != StackObjectOperandMapping.end() &&
          "Invalid frame index");
   const FrameIndexOperand &Operand = ObjectInfo->second;
-  if (Operand.IsFixed) {
-    OS << "%fixed-stack." << Operand.ID;
-    return;
-  }
-  OS << "%stack." << Operand.ID;
-  if (!Operand.Name.empty())
-    OS << '.' << Operand.Name;
+  MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
+                                            Operand.Name);
 }
 
 void MIPrinter::printOffset(int64_t Offset) {
   if (Offset == 0)
     return;
   if (Offset < 0) {
     OS << " - " << -Offset;
     return;

lib/CodeGen/MachineOperand.cpp

 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file Methods common to all machine operands.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Analysis/Loads.h"
 #include "llvm/CodeGen/MIRPrinter.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/ModuleSlotTracker.h"
 #include "llvm/Target/TargetIntrinsicInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
static void tryToGetTargetInfo(const MachineOperand &MO,
                                const TargetRegisterInfo *&TRI,
                                const TargetIntrinsicInfo *&IntrinsicInfo) {
   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
     TRI = MF->getSubtarget().getRegisterInfo();
     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
   }
 }
 
+void MachineOperand::printStackObjectReference(raw_ostream &OS, int FrameIndex,
+                                               bool IsFixed, StringRef Name) {
+  if (IsFixed) {
+    OS << "%fixed-stack." << FrameIndex;
+    return;
+  }
+
+  OS << "%stack." << FrameIndex;
+  if (!Name.empty())
+    OS << '.' << Name;
+}
+
 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
   ModuleSlotTracker DummyMST(nullptr);
   print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
         /*ShouldPrintRegisterTies=*/true,
         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
 }
if (getFPImm()->getType()->isFloatTy()) {
                                  /*Upper=*/true);
     } else {
       OS << getFPImm()->getValueAPF().convertToDouble();
     }
     break;
   case MachineOperand::MO_MachineBasicBlock:
     OS << printMBBReference(*getMBB());
     break;
-  case MachineOperand::MO_FrameIndex:
-    OS << "<fi#" << getIndex() << '>';
+  case MachineOperand::MO_FrameIndex: {
+    int FrameIndex = getIndex();
+    bool IsFixed = false;
+    StringRef Name;
+    if (const MachineFunction *MF = getMFIfAvailable(*this)) {
+      const MachineFrameInfo &MFI = MF->getFrameInfo();
+      IsFixed = MFI.isFixedObjectIndex(FrameIndex);
+      if (const AllocaInst *Alloca = MFI.getObjectAllocation(FrameIndex))
+        if (Alloca->hasName())
+          Name = Alloca->getName();
+      if (IsFixed)
+        FrameIndex -= MFI.getObjectIndexBegin();
+    }
+    printStackObjectReference(OS, FrameIndex, IsFixed, Name);
     break;
+  }
   case MachineOperand::MO_ConstantPoolIndex:
     OS << "<cp#" << getIndex();
     if (getOffset())
       OS << "+" << getOffset();
     OS << '>';
     break;
   case MachineOperand::MO_TargetIndex:
     OS << "<ti#" << getIndex();

lib/Target/AArch64/AArch64InstrInfo.cpp

MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
   // Handle the case where a copy is being spilled or filled but the source
   // and destination register class don't match.  For example:
   //
   //   %0 = COPY %xzr; GPR64common:%0
   //
   // In this case we can still safely fold away the COPY and generate the
   // following spill code:
   //
-  //   STRXui %xzr, <fi#0>
+  //   STRXui %xzr, %stack.0
   //
   // This also eliminates spilled cross register class COPYs (e.g. between x and
   // d regs) of the same size.  For example:
   //
   //   %0 = COPY %1; GPR64:%0, FPR64:%1
   //
   // will be filled as
   //
if (MI.isCopy() && Ops.size() == 1 &&
 
     // Handle cases like spilling def of:
     //
     //   %0:sub_32<def,read-undef> = COPY %wzr; GPR64common:%0
     //
     // where the physical register source can be widened and stored to the full
     // virtual reg destination stack slot, in this case producing:
     //
-    //   STRXui %xzr, <fi#0>
+    //   STRXui %xzr, %stack.0
     //
     if (IsSpill && DstMO.isUndef() &&
         TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
       assert(SrcMO.getSubReg() == 0 &&
              "Unexpected subreg on physical register");
       const TargetRegisterClass *SpillRC;
       unsigned SpillSubreg;
       switch (DstMO.getSubReg()) {
if (MI.isCopy() && Ops.size() == 1 &&
 
     // Handle cases like filling use of:
     //
     //   %0:sub_32<def,read-undef> = COPY %1; GPR64:%0, GPR32:%1
     //
     // where we can load the full virtual reg source stack slot, into the subreg
     // destination, in this case producing:
     //
-    //   LDRWui %0:sub_32<def,read-undef>, <fi#0>
+    //   LDRWui %0:sub_32<def,read-undef>, %stack.0
     //
     if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
       const TargetRegisterClass *FillRC;
       switch (DstMO.getSubReg()) {
       default:
         FillRC = nullptr;
         break;
       case AArch64::sub_32:

lib/Target/X86/README-SSE.txt

cond_next140 (0xa910740, LLVM BB @0xa90beb0):
   %reg1084 = AND32ri8 %reg1039, 15
   CMP32ri8 %reg1084, 0
   JE mbb<cond_next204,0xa914d30>
 
 Still ok. After register allocation:
 
 cond_next140 (0xa910740, LLVM BB @0xa90beb0):
   %eax = MOV32ri -3
-  %edx = MOV32rm <fi#3>, 1, %noreg, 0
+  %edx = MOV32rm %stack.3, 1, %noreg, 0
   ADD32rm %eax<def&use>, %edx, 1, %noreg, 0
-  %edx = MOV32rm <fi#7>, 1, %noreg, 0
+  %edx = MOV32rm %stack.7, 1, %noreg, 0
   %edx = MOV32rm %edx, 1, %noreg, 40
   IMUL32rr %eax<def&use>, %edx
-  %esi = MOV32rm <fi#5>, 1, %noreg, 0
+  %esi = MOV32rm %stack.5, 1, %noreg, 0
   %esi = MOV32rm %esi, 1, %noreg, 0
-  MOV32mr <fi#4>, 1, %noreg, 0, %esi
+  MOV32mr %stack.4, 1, %noreg, 0, %esi
   %eax = LEA32r %esi, 1, %eax, -3
-  %esi = MOV32rm <fi#7>, 1, %noreg, 0
+  %esi = MOV32rm %stack.7, 1, %noreg, 0
   %esi = MOV32rm %esi, 1, %noreg, 32
   %edi = MOV32rr %eax
   SHL32ri %edi<def&use>, 4
   ADD32rr %edi<def&use>, %esi
   %xmm0 = MOVAPSrm %ecx, 1, %noreg, 0
   %xmm1 = MOVAPSrr %xmm0
   SHUFPSrr %xmm1<def&use>, %xmm1, 170
   %xmm2 = MOVAPSrr %xmm0

test/CodeGen/AArch64/tailcall_misched_graph.ll

 ; time.
 
 ; CHECK: Frame Objects
 ; CHECK:  fi#-4: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-3: {{.*}} fixed, at location [SP]
 ; CHECK:  fi#-2: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-1: {{.*}} fixed, at location [SP]
 
-; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui <fi#-1>
-; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui <fi#-2>
-; CHECK:  STRXui %{{.*}}, <fi#-4>
-; CHECK:  STRXui [[VRB]], <fi#-3>
+; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
+; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
+; CHECK:  STRXui %{{.*}}, %fixed-stack.0
+; CHECK:  STRXui [[VRB]], %fixed-stack.1
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
 ; Without this edge the scheduler would be free to move the store accross the load.
 
-; CHECK: SU({{.*}}):   [[VRB]]:gpr64 = LDRXui <fi#-2>
+; CHECK: SU({{.*}}):   [[VRB]]:gpr64 = LDRXui %fixed-stack.2
 ; CHECK-NOT: SU
 ; CHECK:  Successors:
 ; CHECK:   SU([[DEPSTOREB:.*]]): Ord  Latency=0
 ; CHECK:   SU([[DEPSTOREA:.*]]): Ord  Latency=0
 
-; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, <fi#-4>
-; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, <fi#-3>
+; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, %fixed-stack.0
+; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, %fixed-stack.1

test/CodeGen/X86/2010-05-12-FastAllocKills.ll

 ; %reg1034 = MOV_Fp8080 %reg1025
 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
 ; JMP_4 <%bb.5>
 ;    Successors according to CFG: %bb.5
 ;
 ; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
 ;%bb.5: derived from LLVM BB %bb10
 ;    Predecessors according to CFG: %bb.4 %bb.5
-; %fp0 = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
+; %fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
 ; %fp1 = MOV_Fp8080 killed %fp0
 ; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
 ; %fp0 = MOV_Fp8080 %fp2
-; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
-; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
-; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
+; ST_FpP80m %stack.3, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
+; ST_FpP80m %stack.4, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
+; ST_FpP80m %stack.5, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
 ; JMP_4 <%bb.5>
 ;    Successors according to CFG: %bb.5
 
 define fastcc i32 @sqlite3AtoF(i8* %z, double* nocapture %pResult) nounwind ssp {
 entry:
   br i1 undef, label %bb2, label %bb1.i.i