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Differential D40786

[mips] Add partial support for R6 in the long branch pass
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Authored by sdardis on Dec 4 2017, 7:18 AM.

Details

Reviewers
atanasyan
Commits
rGe94fdd125fdd: [mips] Add partial support for R6 in the long branch pass
rL320703: [mips] Add partial support for R6 in the long branch pass
Summary

MIPSR6 introduced several new jump instructions and deprecated
the use of the 'j' instruction. For microMIPS32R6, 'j' was removed
entirely and it only has non delay slot jumps.

This patch adds support for MIPSR6 by using some R6 instructions--
'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'--
and modifies the sequences not to use delay slots for R6.

Diff Detail

Event Timeline

sdardis created this revision.Dec 4 2017, 7:18 AM
Herald added subscribers: arichardson, dschuff. · View Herald TranscriptDec 4 2017, 7:18 AM
atanasyan accepted this revision.Dec 6 2017, 2:47 AM

LGTM with a few nits

lib/Target/Mips/MipsLongBranch.cpp
353

I would revert this condition:

if (Subtarget.hasMips32r6()) {
  LongBrMBB->insert(Pos, ADDiuInstr);
  LongBrMBB->insert(Pos, BalInstr);
} else {
  LongBrMBB->insert(Pos, BalInstr);
  LongBrMBB->insert(Pos, ADDiuInstr);
  LongBrMBB->rbegin()->bundleWithPred();
}
462

And here.

504

And here.

547

I would reduce number of ternary operators a bit:

LongBranchSeqSize = IsPIC
    ? ((ABI.IsN64() || STI.isTargetNaCl()) ? 10 : 9)
    : (STI.hasMips32r6() ? 1 : 2);
This revision is now accepted and ready to land.Dec 6 2017, 2:47 AM
Closed by commit rL320703: [mips] Add partial support for R6 in the long branch pass (authored by sdardis). · Explain WhyDec 14 2017, 6:56 AM
This revision was automatically updated to reflect the committed changes.
sdardis added a comment.Dec 14 2017, 7:50 AM

Thanks for the review.

Revision Contents

PathSize
lib/
Target/
Mips/
163 lines
test/
CodeGen/
Mips/
463 lines

Diff 125339

lib/Target/Mips/MipsLongBranch.cpp

Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Linesvoid MipsLongBranch::expandToLongBranch(MBBInfo &I) {
MBB->replaceSuccessor(TgtMBB, LongBrMBB); MBB->replaceSuccessor(TgtMBB, LongBrMBB);
if (IsPIC) { if (IsPIC) {
MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB); MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
MF->insert(FallThroughMBB, BalTgtMBB); MF->insert(FallThroughMBB, BalTgtMBB);
LongBrMBB->addSuccessor(BalTgtMBB); LongBrMBB->addSuccessor(BalTgtMBB);
BalTgtMBB->addSuccessor(TgtMBB); BalTgtMBB->addSuccessor(TgtMBB);
// We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal // We must select between the MIPS32r6/MIPS64r6 BALC (which is a normal
// instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
// pseudo-instruction wrapping BGEZAL). // pseudo-instruction wrapping BGEZAL).
unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; const unsigned BalOp =
Subtarget.hasMips32r6()
? Subtarget.inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC
: Mips::BAL_BR;
if (!ABI.IsN64()) { if (!ABI.IsN64()) {
// Pre R6:
// $longbr: // $longbr:
// addiu $sp, $sp, -8 // addiu $sp, $sp, -8
// sw $ra, 0($sp) // sw $ra, 0($sp)
// lui $at, %hi($tgt - $baltgt) // lui $at, %hi($tgt - $baltgt)
// bal $baltgt // bal $baltgt
// addiu $at, $at, %lo($tgt - $baltgt) // addiu $at, $at, %lo($tgt - $baltgt)
// $baltgt: // $baltgt:
// addu $at, $ra, $at // addu $at, $ra, $at
// lw $ra, 0($sp) // lw $ra, 0($sp)
// jr $at // jr $at
// addiu $sp, $sp, 8 // addiu $sp, $sp, 8
// $fallthrough: // $fallthrough:
// //
// R6:
// $longbr:
// addiu $sp, $sp, -8
// sw $ra, 0($sp)
// lui $at, %hi($tgt - $baltgt)
// addiu $at, $at, %lo($tgt - $baltgt)
// balc $baltgt
// $baltgt:
// addu $at, $ra, $at
// lw $ra, 0($sp)
// addiu $sp, $sp, 8
// jic $at, 0
// $fallthrough:
Pos = LongBrMBB->begin(); Pos = LongBrMBB->begin();
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP).addImm(-8); .addReg(Mips::SP).addImm(-8);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
.addReg(Mips::SP).addImm(0); .addReg(Mips::SP).addImm(0);
// LUi and ADDiu instructions create 32-bit offset of the target basic // LUi and ADDiu instructions create 32-bit offset of the target basic
// block from the target of BAL instruction. We cannot use immediate // block from the target of BAL(C) instruction. We cannot use immediate
// value for this offset because it cannot be determined accurately when // value for this offset because it cannot be determined accurately when
// the program has inline assembly statements. We therefore use the // the program has inline assembly statements. We therefore use the
// relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
// are resolved during the fixup, so the values will always be correct. // are resolved during the fixup, so the values will always be correct.
// //
// Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt) // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
// expressions at this point (it is possible only at the MC layer), // expressions at this point (it is possible only at the MC layer),
// we replace LUi and ADDiu with pseudo instructions // we replace LUi and ADDiu with pseudo instructions
// LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
// blocks as operands to these instructions. When lowering these pseudo // blocks as operands to these instructions. When lowering these pseudo
// instructions to LUi and ADDiu in the MC layer, we will create // instructions to LUi and ADDiu in the MC layer, we will create
// %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
// operands to lowered instructions. // operands to lowered instructions.
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
.addMBB(TgtMBB).addMBB(BalTgtMBB); .addMBB(TgtMBB).addMBB(BalTgtMBB);
MIBundleBuilder(*LongBrMBB, Pos)
.append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) MachineInstrBuilder BalInstr =
.append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
MachineInstrBuilder ADDiuInstr =
BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
.addReg(Mips::AT) .addReg(Mips::AT)
.addMBB(TgtMBB) .addMBB(TgtMBB)
.addMBB(BalTgtMBB)); .addMBB(BalTgtMBB);
if (!Subtarget.hasMips32r6()) {
atanasyanUnsubmitted
Not Done
ReplyInline Actions

I would revert this condition:

if (Subtarget.hasMips32r6()) {
  LongBrMBB->insert(Pos, ADDiuInstr);
  LongBrMBB->insert(Pos, BalInstr);
} else {
  LongBrMBB->insert(Pos, BalInstr);
  LongBrMBB->insert(Pos, ADDiuInstr);
  LongBrMBB->rbegin()->bundleWithPred();
}
atanasyan: I would revert this condition: ``` if (Subtarget.hasMips32r6()) { LongBrMBB->insert(Pos…
LongBrMBB->insert(Pos, BalInstr);
LongBrMBB->insert(Pos, ADDiuInstr);
LongBrMBB->rbegin()->bundleWithPred();
} else {
LongBrMBB->insert(Pos, ADDiuInstr);
LongBrMBB->insert(Pos, BalInstr);
}
Pos = BalTgtMBB->begin(); Pos = BalTgtMBB->begin();
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
.addReg(Mips::RA).addReg(Mips::AT); .addReg(Mips::RA).addReg(Mips::AT);
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
.addReg(Mips::SP).addImm(0); .addReg(Mips::SP).addImm(0);
if (Subtarget.isTargetNaCl())
// Bundle-align the target of indirect branch JR.
TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
// In NaCl, modifying the sp is not allowed in branch delay slot. // In NaCl, modifying the sp is not allowed in branch delay slot.
if (Subtarget.isTargetNaCl()) // For MIPS32R6, we can skip using a delay slot branch.
if (Subtarget.isTargetNaCl() || Subtarget.hasMips32r6())
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP).addImm(8); .addReg(Mips::SP).addImm(8);
if (Subtarget.hasMips32r6()) if (Subtarget.hasMips32r6()) {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR)) const unsigned JICOp =
.addReg(Mips::ZERO).addReg(Mips::AT); Subtarget.inMicroMipsMode() ? Mips::JIC_MMR6 : Mips::JIC;
else BuildMI(*BalTgtMBB, Pos, DL, TII->get(JICOp))
.addReg(Mips::AT)
.addImm(0);
} else {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT); BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
if (Subtarget.isTargetNaCl()) { if (Subtarget.isTargetNaCl()) {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP)); BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
// Bundle-align the target of indirect branch JR.
TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
} else } else
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP).addImm(8); .addReg(Mips::SP)
.addImm(8);
BalTgtMBB->rbegin()->bundleWithPred(); BalTgtMBB->rbegin()->bundleWithPred();
}
} else { } else {
// Pre R6:
// $longbr: // $longbr:
// daddiu $sp, $sp, -16 // daddiu $sp, $sp, -16
// sd $ra, 0($sp) // sd $ra, 0($sp)
// daddiu $at, $zero, %hi($tgt - $baltgt) // daddiu $at, $zero, %hi($tgt - $baltgt)
// dsll $at, $at, 16 // dsll $at, $at, 16
// bal $baltgt // bal $baltgt
// daddiu $at, $at, %lo($tgt - $baltgt) // daddiu $at, $at, %lo($tgt - $baltgt)
// $baltgt: // $baltgt:
// daddu $at, $ra, $at // daddu $at, $ra, $at
// ld $ra, 0($sp) // ld $ra, 0($sp)
// jr64 $at // jr64 $at
// daddiu $sp, $sp, 16 // daddiu $sp, $sp, 16
// $fallthrough: // $fallthrough:
//
// R6:
// $longbr:
// daddiu $sp, $sp, -16
// sd $ra, 0($sp)
// daddiu $at, $zero, %hi($tgt - $baltgt)
// dsll $at, $at, 16
// daddiu $at, $at, %lo($tgt - $baltgt)
// balc $baltgt
// $baltgt:
// daddu $at, $ra, $at
// ld $ra, 0($sp)
// daddiu $sp, $sp, 16
// jic $at, 0
// $fallthrough:
// We assume the branch is within-function, and that offset is within // We assume the branch is within-function, and that offset is within
// +/- 2GB. High 32 bits will therefore always be zero. // +/- 2GB. High 32 bits will therefore always be zero.
// Note that this will work even if the offset is negative, because // Note that this will work even if the offset is negative, because
// of the +1 modification that's added in that case. For example, if the // of the +1 modification that's added in that case. For example, if the
// offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
// //
Show All 12 Lines if (!ABI.IsN64()) {
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64) BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
.addReg(Mips::SP_64).addImm(0); .addReg(Mips::SP_64).addImm(0);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu), BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
Mips::AT_64).addReg(Mips::ZERO_64) Mips::AT_64).addReg(Mips::ZERO_64)
.addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB); .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64) BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
.addReg(Mips::AT_64).addImm(16); .addReg(Mips::AT_64).addImm(16);
MIBundleBuilder(*LongBrMBB, Pos) MachineInstrBuilder BalInstr =
.append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
.append( MachineInstrBuilder DADDiuInstr =
BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64) BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
.addReg(Mips::AT_64) .addReg(Mips::AT_64)
.addMBB(TgtMBB, MipsII::MO_ABS_LO) .addMBB(TgtMBB, MipsII::MO_ABS_LO)
.addMBB(BalTgtMBB)); .addMBB(BalTgtMBB);
if (!Subtarget.hasMips32r6()) {
atanasyanUnsubmitted
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And here.

atanasyan: And here.
LongBrMBB->insert(Pos, BalInstr);
LongBrMBB->insert(Pos, DADDiuInstr);
LongBrMBB->rbegin()->bundleWithPred();
} else {
LongBrMBB->insert(Pos, DADDiuInstr);
LongBrMBB->insert(Pos, BalInstr);
}
Pos = BalTgtMBB->begin(); Pos = BalTgtMBB->begin();
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
.addReg(Mips::RA_64).addReg(Mips::AT_64); .addReg(Mips::RA_64).addReg(Mips::AT_64);
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
.addReg(Mips::SP_64).addImm(0); .addReg(Mips::SP_64).addImm(0);
if (Subtarget.hasMips64r6()) if (Subtarget.hasMips64r6()) {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR64)) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
.addReg(Mips::ZERO_64).addReg(Mips::AT_64); .addReg(Mips::SP_64)
else .addImm(16);
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JIC64))
.addReg(Mips::AT_64)
.addImm(0);
} else {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64); BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64) BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
.addReg(Mips::SP_64).addImm(16); .addReg(Mips::SP_64)
.addImm(16);
BalTgtMBB->rbegin()->bundleWithPred(); BalTgtMBB->rbegin()->bundleWithPred();
} }
}
assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize); assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
} else { } else {
// $longbr: // Pre R6: R6:
// j $tgt // $longbr: $longbr:
// nop // j $tgt bc $tgt
// nop $fallthrough
// $fallthrough: // $fallthrough:
// //
Pos = LongBrMBB->begin(); Pos = LongBrMBB->begin();
LongBrMBB->addSuccessor(TgtMBB); LongBrMBB->addSuccessor(TgtMBB);
if (!Subtarget.hasMips32r6())
atanasyanUnsubmitted
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And here.

atanasyan: And here.
MIBundleBuilder(*LongBrMBB, Pos) MIBundleBuilder(*LongBrMBB, Pos)
.append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB)) .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
.append(BuildMI(*MF, DL, TII->get(Mips::NOP))); .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
else
BuildMI(*LongBrMBB, Pos, DL,
TII->get(Subtarget.inMicroMipsMode() ? Mips::BC_MMR6 : Mips::BC))
.addMBB(TgtMBB);
assert(LongBrMBB->size() == LongBranchSeqSize); assert(LongBrMBB->size() == LongBranchSeqSize);
} }
if (I.Br->isUnconditionalBranch()) { if (I.Br->isUnconditionalBranch()) {
// Change branch destination. // Change branch destination.
assert(I.Br->getDesc().getNumOperands() == 1); assert(I.Br->getDesc().getNumOperands() == 1);
I.Br->RemoveOperand(0); I.Br->RemoveOperand(0);
Show All 19 Lines const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(F.getSubtarget()); static_cast<const MipsSubtarget &>(F.getSubtarget());
const MipsInstrInfo *TII = const MipsInstrInfo *TII =
static_cast<const MipsInstrInfo *>(STI.getInstrInfo()); static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
const TargetMachine& TM = F.getTarget(); const TargetMachine& TM = F.getTarget();
IsPIC = TM.isPositionIndependent(); IsPIC = TM.isPositionIndependent();
ABI = static_cast<const MipsTargetMachine &>(TM).getABI(); ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
LongBranchSeqSize = LongBranchSeqSize = !IsPIC
atanasyanUnsubmitted
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I would reduce number of ternary operators a bit:

LongBranchSeqSize = IsPIC
    ? ((ABI.IsN64() || STI.isTargetNaCl()) ? 10 : 9)
    : (STI.hasMips32r6() ? 1 : 2);
atanasyan: I would reduce number of ternary operators a bit: ``` LongBranchSeqSize = IsPIC ? ((ABI.
!IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10)); ? (STI.hasMips32r6() ? 1 : 2)
: (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
if (STI.inMips16Mode() || !STI.enableLongBranchPass()) if (STI.inMips16Mode() || !STI.enableLongBranchPass())
return false; return false;
if (IsPIC && static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() && if (IsPIC && static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
F.getInfo<MipsFunctionInfo>()->globalBaseRegSet()) F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
emitGPDisp(F, TII); emitGPDisp(F, TII);
if (SkipLongBranch) if (SkipLongBranch)
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

test/CodeGen/Mips/longbranch.ll

; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s \ ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -O3 -relocation-model=pic < %s \
; RUN: | FileCheck %s -check-prefix=O32 ; RUN: | FileCheck %s -check-prefix=NOLONGBRANCH
; RUN: llc -march=mipsel -mcpu=mips32r6 -force-mips-long-branch -O3 \
; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=O32-R6 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=pic < %s \
; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ ; RUN: | FileCheck %s -check-prefix=O32-PIC
; RUN: < %s | FileCheck %s -check-prefix=N64 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=static < %s \
; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ ; RUN: | FileCheck %s -check-prefix=O32-STATIC
; RUN: < %s | FileCheck %s -check-prefix=N64 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -force-mips-long-branch -O3 \
; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-R6-PIC
; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=N64-R6 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -force-mips-long-branch -O3 \
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \ ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=O32-R6-STATIC
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefix=MIPS4
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefix=MIPS64
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64-R6
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS ; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSSTATIC
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSR6STATIC
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPSR6PIC
; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \ ; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \
; RUN: | FileCheck %s -check-prefix=NACL ; RUN: | FileCheck %s -check-prefix=NACL
@x = external global i32 @x = external global i32
define void @test1(i32 signext %s) { define void @test1(i32 signext %s) {
entry: ; NOLONGBRANCH-LABEL: test1:
%cmp = icmp eq i32 %s, 0 ; NOLONGBRANCH: # BB#0: # %entry
br i1 %cmp, label %end, label %then ; NOLONGBRANCH-NEXT: lui $2, %hi(_gp_disp)
; NOLONGBRANCH-NEXT: addiu $2, $2, %lo(_gp_disp)
then: ; NOLONGBRANCH-NEXT: beqz $4, $BB0_2
store i32 1, i32* @x, align 4 ; NOLONGBRANCH-NEXT: addu $2, $2, $25
br label %end ; NOLONGBRANCH-NEXT: # BB#1: # %then
; NOLONGBRANCH-NEXT: lw $1, %got(x)($2)
end: ; NOLONGBRANCH-NEXT: addiu $2, $zero, 1
ret void ; NOLONGBRANCH-NEXT: sw $2, 0($1)
; NOLONGBRANCH-NEXT: $BB0_2: # %end
; NOLONGBRANCH-NEXT: jr $ra
; First check the normal version (without long branch). beqz jumps to return, ; NOLONGBRANCH-NEXT: nop
; and fallthrough block stores 1 to global variable. ;
; O32-PIC-LABEL: test1:
; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp) ; O32-PIC: # BB#0: # %entry
; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp) ; O32-PIC-NEXT: lui $2, %hi(_gp_disp)
; CHECK: beqz $4, $[[BB0:BB[0-9_]+]] ; O32-PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25 ; O32-PIC-NEXT: bnez $4, $BB0_3
; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; O32-PIC-NEXT: addu $2, $2, $25
; CHECK: addiu $[[R2:[0-9]+]], $zero, 1 ; O32-PIC-NEXT: # BB#1: # %entry
; CHECK: sw $[[R2]], 0($[[R1]]) ; O32-PIC-NEXT: addiu $sp, $sp, -8
; CHECK: $[[BB0]]: ; O32-PIC-NEXT: sw $ra, 0($sp)
; CHECK: jr $ra ; O32-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; CHECK: nop ; O32-PIC-NEXT: bal $BB0_2
; O32-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; O32-PIC-NEXT: $BB0_2: # %entry
; Check the MIPS32 version. Check that branch logic is inverted, so that the ; O32-PIC-NEXT: addu $1, $ra, $1
; target of the new branch (bnez) is the fallthrough block of the original ; O32-PIC-NEXT: lw $ra, 0($sp)
; branch. Check that fallthrough block of the new branch contains long branch ; O32-PIC-NEXT: jr $1
; expansion which at the end indirectly jumps to the target of the original ; O32-PIC-NEXT: addiu $sp, $sp, 8
; branch. ; O32-PIC-NEXT: $BB0_3: # %then
; O32-PIC-NEXT: lw $1, %got(x)($2)
; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp) ; O32-PIC-NEXT: addiu $2, $zero, 1
; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp) ; O32-PIC-NEXT: sw $2, 0($1)
; O32: bnez $4, $[[BB0:BB[0-9_]+]] ; O32-PIC-NEXT: $BB0_4: # %end
; O32: addu $[[GP:[0-9]+]], $[[R0]], $25 ; O32-PIC-NEXT: jr $ra
; O32-PIC-NEXT: nop
; Check for long branch expansion: ;
; O32: addiu $sp, $sp, -8 ; O32-STATIC-LABEL: test1:
; O32-NEXT: sw $ra, 0($sp) ; O32-STATIC: # BB#0: # %entry
; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) ; O32-STATIC-NEXT: bnez $4, $BB0_2
; O32-NEXT: bal $[[BB1]] ; O32-STATIC-NEXT: nop
; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) ; O32-STATIC-NEXT: # BB#1: # %entry
; O32-NEXT: $[[BB1]]: ; O32-STATIC-NEXT: j $BB0_3
; O32-NEXT: addu $1, $ra, $1 ; O32-STATIC-NEXT: nop
; O32-NEXT: lw $ra, 0($sp) ; O32-STATIC-NEXT: $BB0_2: # %then
; O32-NEXT: jr $1 ; O32-STATIC-NEXT: lui $1, %hi(x)
; O32-NEXT: addiu $sp, $sp, 8 ; O32-STATIC-NEXT: addiu $2, $zero, 1
; O32-STATIC-NEXT: sw $2, %lo(x)($1)
; O32: $[[BB0]]: ; O32-STATIC-NEXT: $BB0_3: # %end
; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; O32-STATIC-NEXT: jr $ra
; O32: addiu $[[R2:[0-9]+]], $zero, 1 ; O32-STATIC-NEXT: nop
; O32: sw $[[R2]], 0($[[R1]]) ;
; O32: $[[BB2]]: ; O32-R6-PIC-LABEL: test1:
; O32: jr $ra ; O32-R6-PIC: # BB#0: # %entry
; O32: nop ; O32-R6-PIC-NEXT: lui $2, %hi(_gp_disp)
; O32-R6-PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the ; O32-R6-PIC-NEXT: bnez $4, $BB0_3
; same with the O32 prefix, we use -asm-show-inst in order to make sure that ; O32-R6-PIC-NEXT: addu $2, $2, $25
; the opcode of the MachineInst is a JALR. ; O32-R6-PIC-NEXT: # BB#1: # %entry
; O32-R6: JALR ; O32-R6-PIC-NEXT: addiu $sp, $sp, -8
; O32-R6-PIC-NEXT: sw $ra, 0($sp)
; Check the MIPS64 version. ; O32-R6-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; O32-R6-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1))) ; O32-R6-PIC-NEXT: balc $BB0_2
; N64: bnez $4, [[BB0:\.LBB[0-9_]+]] ; O32-R6-PIC-NEXT: $BB0_2: # %entry
; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25 ; O32-R6-PIC-NEXT: addu $1, $ra, $1
; O32-R6-PIC-NEXT: lw $ra, 0($sp)
; Check for long branch expansion: ; O32-R6-PIC-NEXT: addiu $sp, $sp, 8
; N64: daddiu $sp, $sp, -16 ; O32-R6-PIC-NEXT: jrc $1
; N64-NEXT: sd $ra, 0($sp) ; O32-R6-PIC-NEXT: $BB0_3: # %then
; N64-NEXT: daddiu $1, $zero, %hi([[BB2:\.LBB[0-9_]+]]-[[BB1:\.LBB[0-9_]+]]) ; O32-R6-PIC-NEXT: lw $1, %got(x)($2)
; N64-NEXT: dsll $1, $1, 16 ; O32-R6-PIC-NEXT: addiu $2, $zero, 1
; N64-NEXT: bal [[BB1]] ; O32-R6-PIC-NEXT: sw $2, 0($1)
; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]]) ; O32-R6-PIC-NEXT: $BB0_4: # %end
; N64-NEXT: [[BB1]]: ; O32-R6-PIC-NEXT: jrc $ra
; N64-NEXT: daddu $1, $ra, $1 ;
; N64-NEXT: ld $ra, 0($sp) ; O32-R6-STATIC-LABEL: test1:
; N64-NEXT: jr $1 ; O32-R6-STATIC: # BB#0: # %entry
; N64-NEXT: daddiu $sp, $sp, 16 ; O32-R6-STATIC-NEXT: bnezc $4, $BB0_2
; O32-R6-STATIC-NEXT: nop
; N64: [[BB0]]: ; O32-R6-STATIC-NEXT: # BB#1: # %entry
; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) ; O32-R6-STATIC-NEXT: bc $BB0_3
; N64: addiu $[[R3:[0-9]+]], $zero, 1 ; O32-R6-STATIC-NEXT: $BB0_2: # %then
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; O32-R6-STATIC-NEXT: lui $1, %hi(x)
; N64: sw $[[R3]], 0($[[R2]]) ; O32-R6-STATIC-NEXT: addiu $2, $zero, 1
; N64: [[BB2]]: ; O32-R6-STATIC-NEXT: sw $2, %lo(x)($1)
; N64: jr $ra ; O32-R6-STATIC-NEXT: $BB0_3: # %end
; N64: nop ; O32-R6-STATIC-NEXT: jrc $ra
;
; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the ; MIPS4-LABEL: test1:
; same with the N64 prefix, we use -asm-show-inst in order to make sure that ; MIPS4: # BB#0: # %entry
; the opcode of the MachineInst is a JALR. ; MIPS4-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
; N64-R6: JALR64 ; MIPS4-NEXT: bnez $4, .LBB0_3
; MIPS4-NEXT: daddu $2, $1, $25
; MIPS4-NEXT: # BB#1: # %entry
; Check the microMIPS version. ; MIPS4-NEXT: daddiu $sp, $sp, -16
; MIPS4-NEXT: sd $ra, 0($sp)
; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp) ; MIPS4-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp) ; MIPS4-NEXT: dsll $1, $1, 16
; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]] ; MIPS4-NEXT: bal .LBB0_2
; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25 ; MIPS4-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
; MIPS4-NEXT: .LBB0_2: # %entry
; Check for long branch expansion: ; MIPS4-NEXT: daddu $1, $ra, $1
; MICROMIPS: addiu $sp, $sp, -8 ; MIPS4-NEXT: ld $ra, 0($sp)
; MIPS4-NEXT: jr $1
; MIPS4-NEXT: daddiu $sp, $sp, 16
; MIPS4-NEXT: .LBB0_3: # %then
; MIPS4-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
; MIPS4-NEXT: addiu $2, $zero, 1
; MIPS4-NEXT: ld $1, %got_disp(x)($1)
; MIPS4-NEXT: sw $2, 0($1)
; MIPS4-NEXT: .LBB0_4: # %end
; MIPS4-NEXT: jr $ra
; MIPS4-NEXT: nop
;
; MIPS64-LABEL: test1:
; MIPS64: # BB#0: # %entry
; MIPS64-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
; MIPS64-NEXT: bnez $4, .LBB0_3
; MIPS64-NEXT: daddu $2, $1, $25
; MIPS64-NEXT: # BB#1: # %entry
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: sd $ra, 0($sp)
; MIPS64-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
; MIPS64-NEXT: dsll $1, $1, 16
; MIPS64-NEXT: bal .LBB0_2
; MIPS64-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
; MIPS64-NEXT: .LBB0_2: # %entry
; MIPS64-NEXT: daddu $1, $ra, $1
; MIPS64-NEXT: ld $ra, 0($sp)
; MIPS64-NEXT: jr $1
; MIPS64-NEXT: daddiu $sp, $sp, 16
; MIPS64-NEXT: .LBB0_3: # %then
; MIPS64-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
; MIPS64-NEXT: addiu $2, $zero, 1
; MIPS64-NEXT: ld $1, %got_disp(x)($1)
; MIPS64-NEXT: sw $2, 0($1)
; MIPS64-NEXT: .LBB0_4: # %end
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: nop
;
; N64-R6-LABEL: test1:
; N64-R6: # BB#0: # %entry
; N64-R6-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
; N64-R6-NEXT: bnez $4, .LBB0_3
; N64-R6-NEXT: daddu $2, $1, $25
; N64-R6-NEXT: # BB#1: # %entry
; N64-R6-NEXT: daddiu $sp, $sp, -16
; N64-R6-NEXT: sd $ra, 0($sp)
; N64-R6-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
; N64-R6-NEXT: dsll $1, $1, 16
; N64-R6-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
; N64-R6-NEXT: balc .LBB0_2
; N64-R6-NEXT: .LBB0_2: # %entry
; N64-R6-NEXT: daddu $1, $ra, $1
; N64-R6-NEXT: ld $ra, 0($sp)
; N64-R6-NEXT: daddiu $sp, $sp, 16
; N64-R6-NEXT: jrc $1
; N64-R6-NEXT: .LBB0_3: # %then
; N64-R6-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
; N64-R6-NEXT: addiu $2, $zero, 1
; N64-R6-NEXT: ld $1, %got_disp(x)($1)
; N64-R6-NEXT: sw $2, 0($1)
; N64-R6-NEXT: .LBB0_4: # %end
; N64-R6-NEXT: jrc $ra
;
; MICROMIPS-LABEL: test1:
; MICROMIPS: # BB#0: # %entry
; MICROMIPS-NEXT: lui $2, %hi(_gp_disp)
; MICROMIPS-NEXT: addiu $2, $2, %lo(_gp_disp)
; MICROMIPS-NEXT: bnez $4, $BB0_3
; MICROMIPS-NEXT: addu $2, $2, $25
; MICROMIPS-NEXT: # BB#1: # %entry
; MICROMIPS-NEXT: addiu $sp, $sp, -8
; MICROMIPS-NEXT: sw $ra, 0($sp) ; MICROMIPS-NEXT: sw $ra, 0($sp)
; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) ; MICROMIPS-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; MICROMIPS-NEXT: bal $[[BB1]] ; MICROMIPS-NEXT: bal $BB0_2
; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) ; MICROMIPS-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; MICROMIPS-NEXT: $[[BB1]]: ; MICROMIPS-NEXT: $BB0_2: # %entry
; MICROMIPS-NEXT: addu $1, $ra, $1 ; MICROMIPS-NEXT: addu $1, $ra, $1
; MICROMIPS-NEXT: lw $ra, 0($sp) ; MICROMIPS-NEXT: lw $ra, 0($sp)
; MICROMIPS-NEXT: jr $1 ; MICROMIPS-NEXT: jr $1
; MICROMIPS-NEXT: addiu $sp, $sp, 8 ; MICROMIPS-NEXT: addiu $sp, $sp, 8
; MICROMIPS-NEXT: $BB0_3: # %then
; MICROMIPS: $[[BB0]]: ; MICROMIPS-NEXT: lw $2, %got(x)($2)
; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; MICROMIPS-NEXT: li16 $3, 1
; MICROMIPS: li16 $[[R2:[0-9]+]], 1 ; MICROMIPS-NEXT: sw16 $3, 0($2)
; MICROMIPS: sw16 $[[R2]], 0($[[R1]]) ; MICROMIPS-NEXT: $BB0_4: # %end
; MICROMIPS: $[[BB2]]: ; MICROMIPS-NEXT: jrc $ra
; MICROMIPS: jrc $ra ;
; MICROMIPSSTATIC-LABEL: test1:
; MICROMIPSSTATIC: # BB#0: # %entry
; MICROMIPSSTATIC-NEXT: bnezc $4, $BB0_2
; MICROMIPSSTATIC-NEXT: # BB#1: # %entry
; MICROMIPSSTATIC-NEXT: j $BB0_4
; MICROMIPSSTATIC-NEXT: nop
; MICROMIPSSTATIC-NEXT: $BB0_2: # %entry
; MICROMIPSSTATIC-NEXT: j $BB0_3
; MICROMIPSSTATIC-NEXT: nop
; MICROMIPSSTATIC-NEXT: $BB0_3: # %then
; MICROMIPSSTATIC-NEXT: lui $1, %hi(x)
; MICROMIPSSTATIC-NEXT: li16 $2, 1
; MICROMIPSSTATIC-NEXT: sw $2, %lo(x)($1)
; MICROMIPSSTATIC-NEXT: $BB0_4: # %end
; MICROMIPSSTATIC-NEXT: jrc $ra
;
; MICROMIPSR6STATIC-LABEL: test1:
; MICROMIPSR6STATIC: # BB#0: # %entry
; MICROMIPSR6STATIC-NEXT: bnezc $4, $BB0_2
; MICROMIPSR6STATIC-NEXT: # BB#1: # %entry
; MICROMIPSR6STATIC-NEXT: bc $BB0_4
; MICROMIPSR6STATIC-NEXT: $BB0_2: # %entry
; MICROMIPSR6STATIC-NEXT: bc $BB0_3
; MICROMIPSR6STATIC-NEXT: $BB0_3: # %then
; MICROMIPSR6STATIC-NEXT: lui $1, %hi(x)
; MICROMIPSR6STATIC-NEXT: li16 $2, 1
; MICROMIPSR6STATIC-NEXT: sw $2, %lo(x)($1)
; MICROMIPSR6STATIC-NEXT: $BB0_4: # %end
; MICROMIPSR6STATIC-NEXT: jrc $ra
;
; MICROMIPSR6PIC-LABEL: test1:
; MICROMIPSR6PIC: # BB#0: # %entry
; MICROMIPSR6PIC-NEXT: lui $2, %hi(_gp_disp)
; MICROMIPSR6PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
; MICROMIPSR6PIC-NEXT: addu $2, $2, $25
; MICROMIPSR6PIC-NEXT: bnezc $4, $BB0_3
; MICROMIPSR6PIC-NEXT: # BB#1: # %entry
; MICROMIPSR6PIC-NEXT: addiu $sp, $sp, -8
; MICROMIPSR6PIC-NEXT: sw $ra, 0($sp)
; MICROMIPSR6PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; MICROMIPSR6PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; MICROMIPSR6PIC-NEXT: balc $BB0_2
; MICROMIPSR6PIC-NEXT: $BB0_2: # %entry
; MICROMIPSR6PIC-NEXT: addu $1, $ra, $1
; MICROMIPSR6PIC-NEXT: lw $ra, 0($sp)
; MICROMIPSR6PIC-NEXT: addiu $sp, $sp, 8
; MICROMIPSR6PIC-NEXT: jic $1, 0
; MICROMIPSR6PIC-NEXT: $BB0_3: # %then
; MICROMIPSR6PIC-NEXT: lw $2, %got(x)($2)
; MICROMIPSR6PIC-NEXT: li16 $3, 1
; MICROMIPSR6PIC-NEXT: sw16 $3, 0($2)
; MICROMIPSR6PIC-NEXT: $BB0_4: # %end
; MICROMIPSR6PIC-NEXT: jrc $ra
; Check the NaCl version. Check that sp change is not in the branch delay slot ; Check the NaCl version. Check that sp change is not in the branch delay slot
; of "jr $1" instruction. Check that target of indirect branch "jr $1" is ; of "jr $1" instruction. Check that target of indirect branch "jr $1" is
; bundle aligned. ; bundle aligned.
; NACL: lui $[[R0:[0-9]+]], %hi(_gp_disp) ; NACL-LABEL: test1:
; NACL: addiu $[[R0]], $[[R0]], %lo(_gp_disp) ; NACL: # BB#0:
; NACL: bnez $4, $[[BB0:BB[0-9_]+]] ; NACL-NEXT: lui $2, %hi(_gp_disp)
; NACL: addu $[[GP:[0-9]+]], $[[R0]], $25 ; NACL-NEXT: addiu $2, $2, %lo(_gp_disp)
; NACL-NEXT: bnez $4, $BB0_3
; Check for long branch expansion: ; NACL-NEXT: addu $2, $2, $25
; NACL: addiu $sp, $sp, -8 ; NACL-NEXT: # BB#1:
; NACL-NEXT: addiu $sp, $sp, -8
; NACL-NEXT: sw $ra, 0($sp) ; NACL-NEXT: sw $ra, 0($sp)
; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) ; NACL-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; NACL-NEXT: bal $[[BB1]] ; NACL-NEXT: bal $BB0_2
; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) ; NACL-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; NACL-NEXT: $[[BB1]]: ; NACL-NEXT: $BB0_2:
; NACL-NEXT: addu $1, $ra, $1 ; NACL-NEXT: addu $1, $ra, $1
; NACL-NEXT: lw $ra, 0($sp) ; NACL-NEXT: lw $ra, 0($sp)
; NACL-NEXT: addiu $sp, $sp, 8 ; NACL-NEXT: addiu $sp, $sp, 8
; NACL-NEXT: jr $1 ; NACL-NEXT: jr $1
; NACL-NEXT: nop ; NACL-NEXT: nop
; NACL-NEXT: $BB0_3:
; NACL-NEXT: lw $1, %got(x)($2)
; NACL-NEXT: addiu $2, $zero, 1
; NACL-NEXT: sw $2, 0($1)
; NACL-NEXT: .p2align 4
; NACL-NEXT: $BB0_4:
; NACL-NEXT: jr $ra
; NACL-NEXT: nop
entry:
%cmp = icmp eq i32 %s, 0
br i1 %cmp, label %end, label %then
then:
store i32 1, i32* @x, align 4
br label %end
end:
ret void
; NACL: $[[BB0]]:
; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; NACL: addiu $[[R2:[0-9]+]], $zero, 1
; NACL: sw $[[R2]], 0($[[R1]])
; NACL: .p2align 4
; NACL-NEXT: $[[BB2]]:
; NACL: jr $ra
; NACL: nop
} }