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Differential D40416

[CodeGen] Rename functions PrintReg* to printReg*
ClosedPublic

Authored by thegameg on Nov 24 2017, 3:33 AM.

Details

Reviewers
MatzeB
qcolombet
Commits
rG9d419d3b0cfd: [CodeGen] Rename functions PrintReg* to printReg*
rL319168: [CodeGen] Rename functions PrintReg* to printReg*
Summary

LLVM Coding Standards:

Function names should be verb phrases (as they represent actions), and
command-like function should be imperative. The name should be camel
case, and start with a lower case letter (e.g. openFile() or isFoo()).

Diff Detail

Repository
rL LLVM

Event Timeline

thegameg created this revision.Nov 24 2017, 3:33 AM
Herald added subscribers: javed.absar, JDevlieghere, eraman and 2 others. · View Herald TranscriptNov 24 2017, 3:33 AM
fhahn added a subscriber: fhahn.Nov 24 2017, 3:34 AM
MatzeB accepted this revision.Nov 27 2017, 10:40 AM

LGTM, thanks.

This revision is now accepted and ready to land.Nov 27 2017, 10:40 AM
Closed by commit rL319168: [CodeGen] Rename functions PrintReg* to printReg* (authored by thegameg). · Explain WhyNov 28 2017, 4:43 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
CodeGen/
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lib/
CodeGen/
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AsmPrinter/
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GlobalISel/
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SelectionDAG/
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Target/
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AMDGPU/
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ARC/
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ARM/
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Diff 124546

llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h

Show First 20 Lines • Show All 1,137 Lines • ▼ Show 20 Lines
/// ///
/// The format is: /// The format is:
/// %noreg - NoRegister /// %noreg - NoRegister
/// %vreg5 - a virtual register. /// %vreg5 - a virtual register.
/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
/// %EAX - a physical register /// %EAX - a physical register
/// %physreg17 - a physical register when no TRI instance given. /// %physreg17 - a physical register when no TRI instance given.
/// ///
/// Usage: OS << PrintReg(Reg, TRI) << '\n'; /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
unsigned SubRegIdx = 0); unsigned SubRegIdx = 0);
/// Create Printable object to print register units on a \ref raw_ostream. /// Create Printable object to print register units on a \ref raw_ostream.
/// ///
/// Register units are named after their root registers: /// Register units are named after their root registers:
/// ///
/// AL - Single root. /// AL - Single root.
/// FP0~ST7 - Dual roots. /// FP0~ST7 - Dual roots.
/// ///
/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI); Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
/// \brief Create Printable object to print virtual registers and physical /// \brief Create Printable object to print virtual registers and physical
/// registers on a \ref raw_ostream. /// registers on a \ref raw_ostream.
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI); Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
} // end namespace llvm } // end namespace llvm
#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H

llvm/trunk/lib/CodeGen/AllocationOrder.cpp

Show All 37 LinesAllocationOrder::AllocationOrder(unsigned VirtReg,
if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
HardHints = true; HardHints = true;
rewind(); rewind();
DEBUG({ DEBUG({
if (!Hints.empty()) { if (!Hints.empty()) {
dbgs() << "hints:"; dbgs() << "hints:";
for (unsigned I = 0, E = Hints.size(); I != E; ++I) for (unsigned I = 0, E = Hints.size(); I != E; ++I)
dbgs() << ' ' << PrintReg(Hints[I], TRI); dbgs() << ' ' << printReg(Hints[I], TRI);
dbgs() << '\n'; dbgs() << '\n';
} }
}); });
#ifndef NDEBUG #ifndef NDEBUG
for (unsigned I = 0, E = Hints.size(); I != E; ++I) for (unsigned I = 0, E = Hints.size(); I != E; ++I)
assert(is_contained(Order, Hints[I]) && assert(is_contained(Order, Hints[I]) &&
"Target hint is outside allocation order."); "Target hint is outside allocation order.");
#endif #endif
} }

llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Show First 20 Lines • Show All 796 Lines • ▼ Show 20 Lines
/// emitImplicitDef - This method emits the specified machine instruction /// emitImplicitDef - This method emits the specified machine instruction
/// that is an implicit def. /// that is an implicit def.
void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const { void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
unsigned RegNo = MI->getOperand(0).getReg(); unsigned RegNo = MI->getOperand(0).getReg();
SmallString<128> Str; SmallString<128> Str;
raw_svector_ostream OS(Str); raw_svector_ostream OS(Str);
OS << "implicit-def: " OS << "implicit-def: "
<< PrintReg(RegNo, MF->getSubtarget().getRegisterInfo()); << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
OutStreamer->AddComment(OS.str()); OutStreamer->AddComment(OS.str());
OutStreamer->AddBlankLine(); OutStreamer->AddBlankLine();
} }
static void emitKill(const MachineInstr *MI, AsmPrinter &AP) { static void emitKill(const MachineInstr *MI, AsmPrinter &AP) {
std::string Str; std::string Str;
raw_string_ostream OS(Str); raw_string_ostream OS(Str);
OS << "kill:"; OS << "kill:";
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &Op = MI->getOperand(i); const MachineOperand &Op = MI->getOperand(i);
assert(Op.isReg() && "KILL instruction must have only register operands"); assert(Op.isReg() && "KILL instruction must have only register operands");
OS << ' ' OS << ' '
<< PrintReg(Op.getReg(), << printReg(Op.getReg(),
AP.MF->getSubtarget().getRegisterInfo()) AP.MF->getSubtarget().getRegisterInfo())
<< (Op.isDef() ? "<def>" : "<kill>"); << (Op.isDef() ? "<def>" : "<kill>");
} }
AP.OutStreamer->AddComment(OS.str()); AP.OutStreamer->AddComment(OS.str());
AP.OutStreamer->AddBlankLine(); AP.OutStreamer->AddBlankLine();
} }
/// emitDebugValueComment - This method handles the target-independent form /// emitDebugValueComment - This method handles the target-independent form
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines if (Reg == 0) {
// Suppress offset, it is not meaningful here. // Suppress offset, it is not meaningful here.
OS << "undef"; OS << "undef";
// NOTE: Want this comment at start of line, don't emit with AddComment. // NOTE: Want this comment at start of line, don't emit with AddComment.
AP.OutStreamer->emitRawComment(OS.str()); AP.OutStreamer->emitRawComment(OS.str());
return true; return true;
} }
if (MemLoc) if (MemLoc)
OS << '['; OS << '[';
OS << PrintReg(Reg, AP.MF->getSubtarget().getRegisterInfo()); OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo());
} }
if (MemLoc) if (MemLoc)
OS << '+' << Offset << ']'; OS << '+' << Offset << ']';
// NOTE: Want this comment at start of line, don't emit with AddComment. // NOTE: Want this comment at start of line, don't emit with AddComment.
AP.OutStreamer->emitRawComment(OS.str()); AP.OutStreamer->emitRawComment(OS.str());
return true; return true;
▲ Show 20 Lines • Show All 1,977 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp

Show First 20 Lines • Show All 520 Lines • ▼ Show 20 Lines for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
transferDefinedLanesStep(MO, Info.DefinedLanes); transferDefinedLanesStep(MO, Info.DefinedLanes);
} }
DEBUG( DEBUG(
dbgs() << "Defined/Used lanes:\n"; dbgs() << "Defined/Used lanes:\n";
for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
const VRegInfo &Info = VRegInfos[RegIdx]; const VRegInfo &Info = VRegInfos[RegIdx];
dbgs() << PrintReg(Reg, nullptr) dbgs() << printReg(Reg, nullptr)
<< " Used: " << PrintLaneMask(Info.UsedLanes) << " Used: " << PrintLaneMask(Info.UsedLanes)
<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n'; << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
} }
dbgs() << "\n"; dbgs() << "\n";
); );
bool Again = false; bool Again = false;
// Mark operands as dead/unused. // Mark operands as dead/unused.
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp

Show First 20 Lines • Show All 311 Lines • ▼ Show 20 Lines while (I != B) {
// Some of the clobbered registers are live before I, not a valid insertion // Some of the clobbered registers are live before I, not a valid insertion
// point. // point.
if (!LiveRegUnits.empty()) { if (!LiveRegUnits.empty()) {
DEBUG({ DEBUG({
dbgs() << "Would clobber"; dbgs() << "Would clobber";
for (SparseSet<unsigned>::const_iterator for (SparseSet<unsigned>::const_iterator
i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i) i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
dbgs() << ' ' << PrintRegUnit(*i, TRI); dbgs() << ' ' << printRegUnit(*i, TRI);
dbgs() << " live before " << *I; dbgs() << " live before " << *I;
}); });
continue; continue;
} }
// This is a valid insertion point. // This is a valid insertion point.
InsertionPoint = I; InsertionPoint = I;
DEBUG(dbgs() << "Can insert before " << *I); DEBUG(dbgs() << "Can insert before " << *I);
▲ Show 20 Lines • Show All 489 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/GlobalISel/Localizer.cpp

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines for (MachineInstr &MI : MBB) {
unsigned NewReg = unsigned NewReg =
MRI->createGenericVirtualRegister(MRI->getType(Reg)); MRI->createGenericVirtualRegister(MRI->getType(Reg));
MRI->setRegClassOrRegBank(NewReg, MRI->getRegClassOrRegBank(Reg)); MRI->setRegClassOrRegBank(NewReg, MRI->getRegClassOrRegBank(Reg));
LocalizedMI->getOperand(0).setReg(NewReg); LocalizedMI->getOperand(0).setReg(NewReg);
NewVRegIt = NewVRegIt =
MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first; MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first;
DEBUG(dbgs() << "Inserted: " << *LocalizedMI); DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
} }
DEBUG(dbgs() << "Update use with: " << PrintReg(NewVRegIt->second) DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
<< '\n'); << '\n');
// Update the user reg. // Update the user reg.
MOUse.setReg(NewVRegIt->second); MOUse.setReg(NewVRegIt->second);
} }
} }
} }
return Changed; return Changed;
} }

llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines assert((RepairPt.getNumInsertPoints() == 1 ||
TargetRegisterInfo::isPhysicalRegister(Dst)) && TargetRegisterInfo::isPhysicalRegister(Dst)) &&
"We are about to create several defs for Dst"); "We are about to create several defs for Dst");
// Build the instruction used to repair, then clone it at the right // Build the instruction used to repair, then clone it at the right
// places. Avoiding buildCopy bypasses the check that Src and Dst have the // places. Avoiding buildCopy bypasses the check that Src and Dst have the
// same types because the type is a placeholder when this function is called. // same types because the type is a placeholder when this function is called.
MachineInstr *MI = MachineInstr *MI =
MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src); MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src);
DEBUG(dbgs() << "Copy: " << PrintReg(Src) << " to: " << PrintReg(Dst) DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
<< '\n'); << '\n');
// TODO: // TODO:
// Check if MI is legal. if not, we need to legalize all the // Check if MI is legal. if not, we need to legalize all the
// instructions we are going to insert. // instructions we are going to insert.
std::unique_ptr<MachineInstr *[]> NewInstrs( std::unique_ptr<MachineInstr *[]> NewInstrs(
new MachineInstr *[RepairPt.getNumInsertPoints()]); new MachineInstr *[RepairPt.getNumInsertPoints()]);
bool IsFirst = true; bool IsFirst = true;
unsigned Idx = 0; unsigned Idx = 0;
▲ Show 20 Lines • Show All 836 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

Show First 20 Lines • Show All 426 Lines • ▼ Show 20 Lines for (unsigned OpIdx = 0,
iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs = iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs =
OpdMapper.getVRegs(OpIdx); OpdMapper.getVRegs(OpIdx);
if (NewRegs.begin() == NewRegs.end()) { if (NewRegs.begin() == NewRegs.end()) {
DEBUG(dbgs() << " has not been repaired, nothing to be done\n"); DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
continue; continue;
} }
unsigned OrigReg = MO.getReg(); unsigned OrigReg = MO.getReg();
unsigned NewReg = *NewRegs.begin(); unsigned NewReg = *NewRegs.begin();
DEBUG(dbgs() << " changed, replace " << PrintReg(OrigReg, nullptr)); DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
MO.setReg(NewReg); MO.setReg(NewReg);
DEBUG(dbgs() << " with " << PrintReg(NewReg, nullptr)); DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
// The OperandsMapper creates plain scalar, we may have to fix that. // The OperandsMapper creates plain scalar, we may have to fix that.
// Check if the types match and if not, fix that. // Check if the types match and if not, fix that.
LLT OrigTy = MRI.getType(OrigReg); LLT OrigTy = MRI.getType(OrigReg);
LLT NewTy = MRI.getType(NewReg); LLT NewTy = MRI.getType(NewReg);
if (OrigTy != NewTy) { if (OrigTy != NewTy) {
// The default mapping is not supposed to change the size of // The default mapping is not supposed to change the size of
// the storage. However, right now we don't necessarily bump all // the storage. However, right now we don't necessarily bump all
▲ Show 20 Lines • Show All 302 Lines • ▼ Show 20 Lines const TargetRegisterInfo *TRI =
: nullptr; : nullptr;
bool IsFirst = true; bool IsFirst = true;
for (unsigned Idx = 0; Idx != NumOpds; ++Idx) { for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
if (OpToNewVRegIdx[Idx] == DontKnowIdx) if (OpToNewVRegIdx[Idx] == DontKnowIdx)
continue; continue;
if (!IsFirst) if (!IsFirst)
OS << ", "; OS << ", ";
IsFirst = false; IsFirst = false;
OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
bool IsFirstNewVReg = true; bool IsFirstNewVReg = true;
for (unsigned VReg : getVRegs(Idx)) { for (unsigned VReg : getVRegs(Idx)) {
if (!IsFirstNewVReg) if (!IsFirstNewVReg)
OS << ", "; OS << ", ";
IsFirstNewVReg = false; IsFirstNewVReg = false;
OS << PrintReg(VReg, TRI); OS << printReg(VReg, TRI);
} }
OS << "])"; OS << "])";
} }
} }

llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Show First 20 Lines • Show All 915 Lines • ▼ Show 20 Lines DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
"spill")); "spill"));
++NumSpills; ++NumSpills;
if (IsRealSpill) if (IsRealSpill)
HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original); HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
} }
/// spillAroundUses - insert spill code around each use of Reg. /// spillAroundUses - insert spill code around each use of Reg.
void InlineSpiller::spillAroundUses(unsigned Reg) { void InlineSpiller::spillAroundUses(unsigned Reg) {
DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n'); DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
LiveInterval &OldLI = LIS.getInterval(Reg); LiveInterval &OldLI = LIS.getInterval(Reg);
// Iterate over instructions using Reg. // Iterate over instructions using Reg.
for (MachineRegisterInfo::reg_bundle_iterator for (MachineRegisterInfo::reg_bundle_iterator
RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end(); RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
RegI != E; ) { RegI != E; ) {
MachineInstr *MI = &*(RegI++); MachineInstr *MI = &*(RegI++);
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Linesvoid InlineSpiller::spill(LiveRangeEdit &edit) {
// Share a stack slot among all descendants of Original. // Share a stack slot among all descendants of Original.
Original = VRM.getOriginal(edit.getReg()); Original = VRM.getOriginal(edit.getReg());
StackSlot = VRM.getStackSlot(Original); StackSlot = VRM.getStackSlot(Original);
StackInt = nullptr; StackInt = nullptr;
DEBUG(dbgs() << "Inline spilling " DEBUG(dbgs() << "Inline spilling "
<< TRI.getRegClassName(MRI.getRegClass(edit.getReg())) << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
<< ':' << edit.getParent() << ':' << edit.getParent()
<< "\nFrom original " << PrintReg(Original) << '\n'); << "\nFrom original " << printReg(Original) << '\n');
assert(edit.getParent().isSpillable() && assert(edit.getParent().isSpillable() &&
"Attempting to spill already spilled value."); "Attempting to spill already spilled value.");
assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
collectRegsToSpill(); collectRegsToSpill();
reMaterializeAll(); reMaterializeAll();
// Remat may handle everything. // Remat may handle everything.
▲ Show 20 Lines • Show All 410 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveDebugValues.cpp

Show First 20 Lines • Show All 451 Lines • ▼ Show 20 Linesvoid LiveDebugValues::transferSpillInst(MachineInstr &MI,
unsigned Reg; unsigned Reg;
MachineFunction *MF = MI.getMF(); MachineFunction *MF = MI.getMF();
if (!isSpillInstruction(MI, MF, Reg)) if (!isSpillInstruction(MI, MF, Reg))
return; return;
// Check if the register is the location of a debug value. // Check if the register is the location of a debug value.
for (unsigned ID : OpenRanges.getVarLocs()) { for (unsigned ID : OpenRanges.getVarLocs()) {
if (VarLocIDs[ID].isDescribedByReg() == Reg) { if (VarLocIDs[ID].isDescribedByReg() == Reg) {
DEBUG(dbgs() << "Spilling Register " << PrintReg(Reg, TRI) << '(' DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
<< VarLocIDs[ID].Var.getVar()->getName() << ")\n"); << VarLocIDs[ID].Var.getVar()->getName() << ")\n");
// Create a DBG_VALUE instruction to describe the Var in its spilled // Create a DBG_VALUE instruction to describe the Var in its spilled
// location, but don't insert it yet to avoid invalidating the // location, but don't insert it yet to avoid invalidating the
// iterator in our caller. // iterator in our caller.
unsigned SpillBase; unsigned SpillBase;
int SpillOffset = extractSpillBaseRegAndOffset(MI, SpillBase); int SpillOffset = extractSpillBaseRegAndOffset(MI, SpillBase);
const MachineInstr *DMI = &VarLocIDs[ID].MI; const MachineInstr *DMI = &VarLocIDs[ID].MI;
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveInterval.cpp

Show First 20 Lines • Show All 980 Lines • ▼ Show 20 Lines
} }
void LiveInterval::SubRange::print(raw_ostream &OS) const { void LiveInterval::SubRange::print(raw_ostream &OS) const {
OS << " L" << PrintLaneMask(LaneMask) << ' ' OS << " L" << PrintLaneMask(LaneMask) << ' '
<< static_cast<const LiveRange&>(*this); << static_cast<const LiveRange&>(*this);
} }
void LiveInterval::print(raw_ostream &OS) const { void LiveInterval::print(raw_ostream &OS) const {
OS << PrintReg(reg) << ' '; OS << printReg(reg) << ' ';
super::print(OS); super::print(OS);
// Print subranges // Print subranges
for (const SubRange &SR : subranges()) for (const SubRange &SR : subranges())
OS << SR; OS << SR;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void LiveRange::dump() const { LLVM_DUMP_METHOD void LiveRange::dump() const {
▲ Show 20 Lines • Show All 371 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
} }
void LiveIntervals::print(raw_ostream &OS, const Module* ) const { void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
OS << "********** INTERVALS **********\n"; OS << "********** INTERVALS **********\n";
// Dump the regunits. // Dump the regunits.
for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit) for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)
if (LiveRange *LR = RegUnitRanges[Unit]) if (LiveRange *LR = RegUnitRanges[Unit])
OS << PrintRegUnit(Unit, TRI) << ' ' << *LR << '\n'; OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n';
// Dump the virtregs. // Dump the virtregs.
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i); unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (hasInterval(Reg)) if (hasInterval(Reg))
OS << getInterval(Reg) << '\n'; OS << getInterval(Reg) << '\n';
} }
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines for (const auto &LI : MBB.liveins()) {
LiveRange *LR = RegUnitRanges[Unit]; LiveRange *LR = RegUnitRanges[Unit];
if (!LR) { if (!LR) {
// Use segment set to speed-up initial computation of the live range. // Use segment set to speed-up initial computation of the live range.
LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs); LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
NewRanges.push_back(Unit); NewRanges.push_back(Unit);
} }
VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator()); VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
(void)VNI; (void)VNI;
DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id); DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
} }
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n"); DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
// Compute the 'normal' part of the ranges. // Compute the 'normal' part of the ranges.
for (unsigned Unit : NewRanges) for (unsigned Unit : NewRanges)
▲ Show 20 Lines • Show All 643 Lines • ▼ Show 20 Linesprivate:
/// Update a single live range, assuming an instruction has been moved from /// Update a single live range, assuming an instruction has been moved from
/// OldIdx to NewIdx. /// OldIdx to NewIdx.
void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) { void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
if (!Updated.insert(&LR).second) if (!Updated.insert(&LR).second)
return; return;
DEBUG({ DEBUG({
dbgs() << " "; dbgs() << " ";
if (TargetRegisterInfo::isVirtualRegister(Reg)) { if (TargetRegisterInfo::isVirtualRegister(Reg)) {
dbgs() << PrintReg(Reg); dbgs() << printReg(Reg);
if (LaneMask.any()) if (LaneMask.any())
dbgs() << " L" << PrintLaneMask(LaneMask); dbgs() << " L" << PrintLaneMask(LaneMask);
} else { } else {
dbgs() << PrintRegUnit(Reg, &TRI); dbgs() << printRegUnit(Reg, &TRI);
} }
dbgs() << ":\t" << LR << '\n'; dbgs() << ":\t" << LR << '\n';
}); });
if (SlotIndex::isEarlierInstr(OldIdx, NewIdx)) if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
handleMoveDown(LR); handleMoveDown(LR);
else else
handleMoveUp(LR, Reg, LaneMask); handleMoveUp(LR, Reg, LaneMask);
DEBUG(dbgs() << " -->\t" << LR << '\n'); DEBUG(dbgs() << " -->\t" << LR << '\n');
▲ Show 20 Lines • Show All 588 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
void void
LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const { LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
if (empty()) { if (empty()) {
OS << " empty\n"; OS << " empty\n";
return; return;
} }
for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) { for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
OS << " [" << SI.start() << ' ' << SI.stop() << "):" OS << " [" << SI.start() << ' ' << SI.stop() << "):"
<< PrintReg(SI.value()->reg, TRI); << printReg(SI.value()->reg, TRI);
} }
OS << '\n'; OS << '\n';
} }
#ifndef NDEBUG #ifndef NDEBUG
// Verify the live intervals in this union and add them to the visited set. // Verify the live intervals in this union and add them to the visited set.
void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) { void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI) for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LivePhysRegs.cpp

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Linesvoid LivePhysRegs::print(raw_ostream &OS) const {
} }
if (empty()) { if (empty()) {
OS << " (empty)\n"; OS << " (empty)\n";
return; return;
} }
for (const_iterator I = begin(), E = end(); I != E; ++I) for (const_iterator I = begin(), E = end(); I != E; ++I)
OS << " " << PrintReg(*I, TRI); OS << " " << printReg(*I, TRI);
OS << "\n"; OS << "\n";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void LivePhysRegs::dump() const { LLVM_DUMP_METHOD void LivePhysRegs::dump() const {
dbgs() << " " << *this; dbgs() << " " << *this;
} }
#endif #endif
▲ Show 20 Lines • Show All 192 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Linesbool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
// Using Seen as a visited set, perform a BFS for all reaching defs. // Using Seen as a visited set, perform a BFS for all reaching defs.
for (unsigned i = 0; i != WorkList.size(); ++i) { for (unsigned i = 0; i != WorkList.size(); ++i) {
MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]); MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
#ifndef NDEBUG #ifndef NDEBUG
if (MBB->pred_empty()) { if (MBB->pred_empty()) {
MBB->getParent()->verify(); MBB->getParent()->verify();
errs() << "Use of " << PrintReg(PhysReg) errs() << "Use of " << printReg(PhysReg)
<< " does not have a corresponding definition on every path:\n"; << " does not have a corresponding definition on every path:\n";
const MachineInstr *MI = Indexes->getInstructionFromIndex(Use); const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
if (MI != nullptr) if (MI != nullptr)
errs() << Use << " " << *MI; errs() << Use << " " << *MI;
report_fatal_error("Use not jointly dominated by defs."); report_fatal_error("Use not jointly dominated by defs.");
} }
if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
!MBB->isLiveIn(PhysReg)) { !MBB->isLiveIn(PhysReg)) {
MBB->getParent()->verify(); MBB->getParent()->verify();
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
errs() << "The register " << PrintReg(PhysReg, TRI) errs() << "The register " << printReg(PhysReg, TRI)
<< " needs to be live in to BB#" << MBB->getNumber() << " needs to be live in to BB#" << MBB->getNumber()
<< ", but is missing from the live-in list.\n"; << ", but is missing from the live-in list.\n";
report_fatal_error("Invalid global physical register"); report_fatal_error("Invalid global physical register");
} }
#endif #endif
FoundUndef |= MBB->pred_empty(); FoundUndef |= MBB->pred_empty();
for (MachineBasicBlock *Pred : MBB->predecessors()) { for (MachineBasicBlock *Pred : MBB->predecessors()) {
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp

Show First 20 Lines • Show All 459 Lines • ▼ Show 20 LinesLiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
const MachineLoopInfo &Loops, const MachineLoopInfo &Loops,
const MachineBlockFrequencyInfo &MBFI) { const MachineBlockFrequencyInfo &MBFI) {
VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI); VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
for (unsigned I = 0, Size = size(); I < Size; ++I) { for (unsigned I = 0, Size = size(); I < Size; ++I) {
LiveInterval &LI = LIS.getInterval(get(I)); LiveInterval &LI = LIS.getInterval(get(I));
if (MRI.recomputeRegClass(LI.reg)) if (MRI.recomputeRegClass(LI.reg))
DEBUG({ DEBUG({
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
dbgs() << "Inflated " << PrintReg(LI.reg) << " to " dbgs() << "Inflated " << printReg(LI.reg) << " to "
<< TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
}); });
VRAI.calculateSpillWeightAndHint(LI); VRAI.calculateSpillWeightAndHint(LI);
} }
} }

llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
if (Func(*Units, VRegInterval)) if (Func(*Units, VRegInterval))
return true; return true;
} }
} }
return false; return false;
} }
void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI)
<< " to " << PrintReg(PhysReg, TRI) << ':'); << " to " << printReg(PhysReg, TRI) << ':');
assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
VRM->assignVirt2Phys(VirtReg.reg, PhysReg); VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) { const LiveRange &Range) {
DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
Matrix[Unit].unify(VirtReg, Range); Matrix[Unit].unify(VirtReg, Range);
return false; return false;
}); });
++NumAssigned; ++NumAssigned;
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
void LiveRegMatrix::unassign(LiveInterval &VirtReg) { void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
unsigned PhysReg = VRM->getPhys(VirtReg.reg); unsigned PhysReg = VRM->getPhys(VirtReg.reg);
DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI)
<< " from " << PrintReg(PhysReg, TRI) << ':'); << " from " << printReg(PhysReg, TRI) << ':');
VRM->clearVirt(VirtReg.reg); VRM->clearVirt(VirtReg.reg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) { const LiveRange &Range) {
DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI)); DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
Matrix[Unit].extract(VirtReg, Range); Matrix[Unit].extract(VirtReg, Range);
return false; return false;
}); });
++NumUnassigned; ++NumUnassigned;
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
llvm_unreachable("LLVM Module is supposed to be parsed separately"); llvm_unreachable("LLVM Module is supposed to be parsed separately");
return ""; return "";
} }
}; };
} // end namespace yaml } // end namespace yaml
} // end namespace llvm } // end namespace llvm
static void printReg(unsigned Reg, raw_ostream &OS, static void printRegMIR(unsigned Reg, raw_ostream &OS,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
// TODO: Print Stack Slots. // TODO: Print Stack Slots.
if (!Reg) if (!Reg)
OS << '_'; OS << '_';
else if (TargetRegisterInfo::isVirtualRegister(Reg)) else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
else if (Reg < TRI->getNumRegs()) else if (Reg < TRI->getNumRegs())
OS << '%' << StringRef(TRI->getName(Reg)).lower(); OS << '%' << StringRef(TRI->getName(Reg)).lower();
else else
llvm_unreachable("Can't print this kind of register yet"); llvm_unreachable("Can't print this kind of register yet");
} }
static void printReg(unsigned Reg, yaml::StringValue &Dest, static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
raw_string_ostream OS(Dest.Value); raw_string_ostream OS(Dest.Value);
printReg(Reg, OS, TRI); printRegMIR(Reg, OS, TRI);
} }
void MIRPrinter::print(const MachineFunction &MF) { void MIRPrinter::print(const MachineFunction &MF) {
initRegisterMaskIds(MF); initRegisterMaskIds(MF);
yaml::MachineFunction YamlMF; yaml::MachineFunction YamlMF;
YamlMF.Name = MF.getName(); YamlMF.Name = MF.getName();
YamlMF.Alignment = MF.getAlignment(); YamlMF.Alignment = MF.getAlignment();
Show All 37 Linesstatic void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
OS << StringRef("CustomRegMask("); OS << StringRef("CustomRegMask(");
bool IsRegInRegMaskFound = false; bool IsRegInRegMaskFound = false;
for (int I = 0, E = TRI->getNumRegs(); I < E; I++) { for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
// Check whether the register is asserted in regmask. // Check whether the register is asserted in regmask.
if (RegMask[I / 32] & (1u << (I % 32))) { if (RegMask[I / 32] & (1u << (I % 32))) {
if (IsRegInRegMaskFound) if (IsRegInRegMaskFound)
OS << ','; OS << ',';
printReg(I, OS, TRI); printRegMIR(I, OS, TRI);
IsRegInRegMaskFound = true; IsRegInRegMaskFound = true;
} }
} }
OS << ')'; OS << ')';
} }
static void printRegClassOrBank(unsigned Reg, raw_ostream &OS, static void printRegClassOrBank(unsigned Reg, raw_ostream &OS,
Show All 26 Linesvoid MIRPrinter::convert(yaml::MachineFunction &MF,
// Print the virtual register definitions. // Print the virtual register definitions.
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(I); unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
yaml::VirtualRegisterDefinition VReg; yaml::VirtualRegisterDefinition VReg;
VReg.ID = I; VReg.ID = I;
printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
unsigned PreferredReg = RegInfo.getSimpleHint(Reg); unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
if (PreferredReg) if (PreferredReg)
printReg(PreferredReg, VReg.PreferredRegister, TRI); printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
MF.VirtualRegisters.push_back(VReg); MF.VirtualRegisters.push_back(VReg);
} }
// Print the live ins. // Print the live ins.
for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
yaml::MachineFunctionLiveIn LiveIn; yaml::MachineFunctionLiveIn LiveIn;
printReg(LI.first, LiveIn.Register, TRI); printRegMIR(LI.first, LiveIn.Register, TRI);
if (LI.second) if (LI.second)
printReg(LI.second, LiveIn.VirtualRegister, TRI); printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
MF.LiveIns.push_back(LiveIn); MF.LiveIns.push_back(LiveIn);
} }
// Prints the callee saved registers. // Prints the callee saved registers.
if (RegInfo.isUpdatedCSRsInitialized()) { if (RegInfo.isUpdatedCSRsInitialized()) {
const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs(); const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
std::vector<yaml::FlowStringValue> CalleeSavedRegisters; std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) { for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
yaml::FlowStringValue Reg; yaml::FlowStringValue Reg;
printReg(*I, Reg, TRI); printRegMIR(*I, Reg, TRI);
CalleeSavedRegisters.push_back(Reg); CalleeSavedRegisters.push_back(Reg);
} }
MF.CalleeSavedRegisters = CalleeSavedRegisters; MF.CalleeSavedRegisters = CalleeSavedRegisters;
} }
} }
void MIRPrinter::convert(ModuleSlotTracker &MST, void MIRPrinter::convert(ModuleSlotTracker &MST,
yaml::MachineFrameInfo &YamlMFI, yaml::MachineFrameInfo &YamlMFI,
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
YMF.StackObjects.push_back(YamlObject); YMF.StackObjects.push_back(YamlObject);
StackObjectOperandMapping.insert(std::make_pair( StackObjectOperandMapping.insert(std::make_pair(
I, FrameIndexOperand::create(YamlObject.Name.Value, ID++))); I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
} }
for (const auto &CSInfo : MFI.getCalleeSavedInfo()) { for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
yaml::StringValue Reg; yaml::StringValue Reg;
printReg(CSInfo.getReg(), Reg, TRI); printRegMIR(CSInfo.getReg(), Reg, TRI);
auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx()); auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
assert(StackObjectInfo != StackObjectOperandMapping.end() && assert(StackObjectInfo != StackObjectOperandMapping.end() &&
"Invalid stack object index"); "Invalid stack object index");
const FrameIndexOperand &StackObject = StackObjectInfo->second; const FrameIndexOperand &StackObject = StackObjectInfo->second;
if (StackObject.IsFixed) { if (StackObject.IsFixed) {
YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg; YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored = YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
CSInfo.isRestored(); CSInfo.isRestored();
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Linesvoid MIPrinter::print(const MachineBasicBlock &MBB) {
if (MRI.tracksLiveness() && !MBB.livein_empty()) { if (MRI.tracksLiveness() && !MBB.livein_empty()) {
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
OS.indent(2) << "liveins: "; OS.indent(2) << "liveins: ";
bool First = true; bool First = true;
for (const auto &LI : MBB.liveins()) { for (const auto &LI : MBB.liveins()) {
if (!First) if (!First)
OS << ", "; OS << ", ";
First = false; First = false;
printReg(LI.PhysReg, OS, &TRI); printRegMIR(LI.PhysReg, OS, &TRI);
if (!LI.LaneMask.all()) if (!LI.LaneMask.all())
OS << ":0x" << PrintLaneMask(LI.LaneMask); OS << ":0x" << PrintLaneMask(LI.LaneMask);
} }
OS << "\n"; OS << "\n";
HasLineAttributes = true; HasLineAttributes = true;
} }
if (HasLineAttributes) if (HasLineAttributes)
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines case MachineOperand::MO_Register: {
if (Op.isKill()) if (Op.isKill())
OS << "killed "; OS << "killed ";
if (Op.isUndef()) if (Op.isUndef())
OS << "undef "; OS << "undef ";
if (Op.isEarlyClobber()) if (Op.isEarlyClobber())
OS << "early-clobber "; OS << "early-clobber ";
if (Op.isDebug()) if (Op.isDebug())
OS << "debug-use "; OS << "debug-use ";
printReg(Reg, OS, TRI); printRegMIR(Reg, OS, TRI);
// Print the sub register. // Print the sub register.
if (Op.getSubReg() != 0) if (Op.getSubReg() != 0)
OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
if (TargetRegisterInfo::isVirtualRegister(Reg)) { if (TargetRegisterInfo::isVirtualRegister(Reg)) {
const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo(); const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo();
if (IsDef || MRI.def_empty(Reg)) { if (IsDef || MRI.def_empty(Reg)) {
OS << ':'; OS << ':';
printRegClassOrBank(Reg, OS, MRI, TRI); printRegClassOrBank(Reg, OS, MRI, TRI);
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesvoid MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
case MachineOperand::MO_RegisterLiveOut: { case MachineOperand::MO_RegisterLiveOut: {
const uint32_t *RegMask = Op.getRegLiveOut(); const uint32_t *RegMask = Op.getRegLiveOut();
OS << "liveout("; OS << "liveout(";
bool IsCommaNeeded = false; bool IsCommaNeeded = false;
for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) { for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
if (RegMask[Reg / 32] & (1U << (Reg % 32))) { if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
if (IsCommaNeeded) if (IsCommaNeeded)
OS << ", "; OS << ", ";
printReg(Reg, OS, TRI); printRegMIR(Reg, OS, TRI);
IsCommaNeeded = true; IsCommaNeeded = true;
} }
} }
OS << ")"; OS << ")";
break; break;
} }
case MachineOperand::MO_Metadata: case MachineOperand::MO_Metadata:
Op.getMetadata()->printAsOperand(OS, MST); Op.getMetadata()->printAsOperand(OS, MST);
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
int Reg = TRI->getLLVMRegNum(DwarfReg, true); int Reg = TRI->getLLVMRegNum(DwarfReg, true);
if (Reg == -1) { if (Reg == -1) {
OS << "<badreg>"; OS << "<badreg>";
return; return;
} }
printReg(Reg, OS, TRI); printRegMIR(Reg, OS, TRI);
} }
void MIPrinter::print(const MCCFIInstruction &CFI, void MIPrinter::print(const MCCFIInstruction &CFI,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
switch (CFI.getOperation()) { switch (CFI.getOperation()) {
case MCCFIInstruction::OpSameValue: case MCCFIInstruction::OpSameValue:
OS << "same_value "; OS << "same_value ";
if (CFI.getLabel()) if (CFI.getLabel())
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Linesvoid MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << '\n'; OS << '\n';
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
if (!livein_empty()) { if (!livein_empty()) {
if (Indexes) OS << '\t'; if (Indexes) OS << '\t';
OS << " Live Ins:"; OS << " Live Ins:";
for (const auto &LI : LiveIns) { for (const auto &LI : LiveIns) {
OS << ' ' << PrintReg(LI.PhysReg, TRI); OS << ' ' << printReg(LI.PhysReg, TRI);
if (!LI.LaneMask.all()) if (!LI.LaneMask.all())
OS << ':' << PrintLaneMask(LI.LaneMask); OS << ':' << PrintLaneMask(LI.LaneMask);
} }
OS << '\n'; OS << '\n';
} }
// Print the preds of this block according to the CFG. // Print the preds of this block according to the CFG.
if (!pred_empty()) { if (!pred_empty()) {
if (Indexes) OS << '\t'; if (Indexes) OS << '\t';
▲ Show 20 Lines • Show All 1,040 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineFunction.cpp

Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Linesvoid MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
ConstantPool->print(OS); ConstantPool->print(OS);
const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo(); const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo();
if (RegInfo && !RegInfo->livein_empty()) { if (RegInfo && !RegInfo->livein_empty()) {
OS << "Function Live Ins: "; OS << "Function Live Ins: ";
for (MachineRegisterInfo::livein_iterator for (MachineRegisterInfo::livein_iterator
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
OS << PrintReg(I->first, TRI); OS << printReg(I->first, TRI);
if (I->second) if (I->second)
OS << " in " << PrintReg(I->second, TRI); OS << " in " << printReg(I->second, TRI);
if (std::next(I) != E) if (std::next(I) != E)
OS << ", "; OS << ", ";
} }
OS << '\n'; OS << '\n';
} }
ModuleSlotTracker MST(getFunction()->getParent()); ModuleSlotTracker MST(getFunction()->getParent());
MST.incorporateFunction(*getFunction()); MST.incorporateFunction(*getFunction());
▲ Show 20 Lines • Show All 551 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineInstr.cpp

Show First 20 Lines • Show All 385 Lines • ▼ Show 20 Linesvoid MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
print(OS, DummyMST, TRI, IntrinsicInfo); print(OS, DummyMST, TRI, IntrinsicInfo);
} }
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const { const TargetIntrinsicInfo *IntrinsicInfo) const {
switch (getType()) { switch (getType()) {
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
OS << PrintReg(getReg(), TRI, getSubReg()); OS << printReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isInternalRead() || isEarlyClobber() || isTied()) { isInternalRead() || isEarlyClobber() || isTied()) {
OS << '<'; OS << '<';
bool NeedComma = false; bool NeedComma = false;
if (isDef()) { if (isDef()) {
if (NeedComma) OS << ','; if (NeedComma) OS << ',';
if (isEarlyClobber()) if (isEarlyClobber())
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines case MachineOperand::MO_RegisterMask: {
unsigned NumRegsEmitted = 0; unsigned NumRegsEmitted = 0;
OS << "<regmask"; OS << "<regmask";
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) { for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
unsigned MaskWord = i / 32; unsigned MaskWord = i / 32;
unsigned MaskBit = i % 32; unsigned MaskBit = i % 32;
if (getRegMask()[MaskWord] & (1 << MaskBit)) { if (getRegMask()[MaskWord] & (1 << MaskBit)) {
if (PrintRegMaskNumRegs < 0 || if (PrintRegMaskNumRegs < 0 ||
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) { NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
OS << " " << PrintReg(i, TRI); OS << " " << printReg(i, TRI);
NumRegsEmitted++; NumRegsEmitted++;
} }
NumRegsInMask++; NumRegsInMask++;
} }
} }
if (NumRegsEmitted != NumRegsInMask) if (NumRegsEmitted != NumRegsInMask)
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more..."; OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
OS << ">"; OS << ">";
▲ Show 20 Lines • Show All 1,586 Lines • ▼ Show 20 Lines for (unsigned i = 0; i != VirtRegs.size(); ++i) {
if (!RC) if (!RC)
continue; continue;
// Generic virtual registers do not have register classes. // Generic virtual registers do not have register classes.
if (RC.is<const RegisterBank *>()) if (RC.is<const RegisterBank *>())
OS << " " << RC.get<const RegisterBank *>()->getName(); OS << " " << RC.get<const RegisterBank *>()->getName();
else else
OS << " " OS << " "
<< TRI->getRegClassName(RC.get<const TargetRegisterClass *>()); << TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
OS << ':' << PrintReg(VirtRegs[i]); OS << ':' << printReg(VirtRegs[i]);
for (unsigned j = i+1; j != VirtRegs.size();) { for (unsigned j = i+1; j != VirtRegs.size();) {
if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) { if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
++j; ++j;
continue; continue;
} }
if (VirtRegs[i] != VirtRegs[j]) if (VirtRegs[i] != VirtRegs[j])
OS << "," << PrintReg(VirtRegs[j]); OS << "," << printReg(VirtRegs[j]);
VirtRegs.erase(VirtRegs.begin()+j); VirtRegs.erase(VirtRegs.begin()+j);
} }
} }
} }
// Print debug location information. // Print debug location information.
if (isDebugValue() && getOperand(e - 2).isMetadata()) { if (isDebugValue() && getOperand(e - 2).isMetadata()) {
if (!HaveSemi) if (!HaveSemi)
▲ Show 20 Lines • Show All 321 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
void MachineRegisterInfo::verifyUseList(unsigned Reg) const { void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
#ifndef NDEBUG #ifndef NDEBUG
bool Valid = true; bool Valid = true;
for (MachineOperand &M : reg_operands(Reg)) { for (MachineOperand &M : reg_operands(Reg)) {
MachineOperand *MO = &M; MachineOperand *MO = &M;
MachineInstr *MI = MO->getParent(); MachineInstr *MI = MO->getParent();
if (!MI) { if (!MI) {
errs() << PrintReg(Reg, getTargetRegisterInfo()) errs() << printReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO << " use list MachineOperand " << MO
<< " has no parent instruction.\n"; << " has no parent instruction.\n";
Valid = false; Valid = false;
continue; continue;
} }
MachineOperand *MO0 = &MI->getOperand(0); MachineOperand *MO0 = &MI->getOperand(0);
unsigned NumOps = MI->getNumOperands(); unsigned NumOps = MI->getNumOperands();
if (!(MO >= MO0 && MO < MO0+NumOps)) { if (!(MO >= MO0 && MO < MO0+NumOps)) {
errs() << PrintReg(Reg, getTargetRegisterInfo()) errs() << printReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO << " use list MachineOperand " << MO
<< " doesn't belong to parent MI: " << *MI; << " doesn't belong to parent MI: " << *MI;
Valid = false; Valid = false;
} }
if (!MO->isReg()) { if (!MO->isReg()) {
errs() << PrintReg(Reg, getTargetRegisterInfo()) errs() << printReg(Reg, getTargetRegisterInfo())
<< " MachineOperand " << MO << ": " << *MO << " MachineOperand " << MO << ": " << *MO
<< " is not a register\n"; << " is not a register\n";
Valid = false; Valid = false;
} }
if (MO->getReg() != Reg) { if (MO->getReg() != Reg) {
errs() << PrintReg(Reg, getTargetRegisterInfo()) errs() << printReg(Reg, getTargetRegisterInfo())
<< " use-list MachineOperand " << MO << ": " << " use-list MachineOperand " << MO << ": "
<< *MO << " is the wrong register\n"; << *MO << " is the wrong register\n";
Valid = false; Valid = false;
} }
} }
assert(Valid && "Invalid use list"); assert(Valid && "Invalid use list");
#endif #endif
} }
▲ Show 20 Lines • Show All 413 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineScheduler.cpp

Show First 20 Lines • Show All 1,124 Lines • ▼ Show 20 Lines if (ShouldTrackLaneMasks) {
SUnit &SU = *V2SU.SU; SUnit &SU = *V2SU.SU;
if (SU.isScheduled || &SU == &ExitSU) if (SU.isScheduled || &SU == &ExitSU)
continue; continue;
PressureDiff &PDiff = getPressureDiff(&SU); PressureDiff &PDiff = getPressureDiff(&SU);
PDiff.addPressureChange(Reg, Decrement, &MRI); PDiff.addPressureChange(Reg, Decrement, &MRI);
DEBUG( DEBUG(
dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
<< PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) << printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
<< ' ' << *SU.getInstr(); << ' ' << *SU.getInstr();
dbgs() << " to "; dbgs() << " to ";
PDiff.dump(*TRI); PDiff.dump(*TRI);
); );
} }
} else { } else {
assert(P.LaneMask.any()); assert(P.LaneMask.any());
DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n"); DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
// This may be called before CurrentBottom has been initialized. However, // This may be called before CurrentBottom has been initialized. However,
// BotRPTracker must have a valid position. We want the value live into the // BotRPTracker must have a valid position. We want the value live into the
// instruction or live out of the block, so ask for the previous // instruction or live out of the block, so ask for the previous
// instruction's live-out. // instruction's live-out.
const LiveInterval &LI = LIS->getInterval(Reg); const LiveInterval &LI = LIS->getInterval(Reg);
VNInfo *VNI; VNInfo *VNI;
MachineBasicBlock::const_iterator I = MachineBasicBlock::const_iterator I =
nextIfDebug(BotRPTracker.getPos(), BB->end()); nextIfDebug(BotRPTracker.getPos(), BB->end());
▲ Show 20 Lines • Show All 2,497 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp

Show First 20 Lines • Show All 1,129 Lines • ▼ Show 20 Lines for (;!Stack.empty(); Stack.pop_back()) {
} }
// Update virtual live-in heights. They were added by addLiveIns() with a 0 // Update virtual live-in heights. They were added by addLiveIns() with a 0
// height because the final height isn't known until now. // height because the final height isn't known until now.
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " Live-ins:"); DEBUG(dbgs() << "BB#" << MBB->getNumber() << " Live-ins:");
for (LiveInReg &LIR : TBI.LiveIns) { for (LiveInReg &LIR : TBI.LiveIns) {
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
LIR.Height = Heights.lookup(DefMI); LIR.Height = Heights.lookup(DefMI);
DEBUG(dbgs() << ' ' << PrintReg(LIR.Reg) << '@' << LIR.Height); DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
} }
// Transfer the live regunits to the live-in list. // Transfer the live regunits to the live-in list.
for (SparseSet<LiveRegUnit>::const_iterator for (SparseSet<LiveRegUnit>::const_iterator
RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) { RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) {
TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI) DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI)
<< '@' << RI->Cycle); << '@' << RI->Cycle);
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
if (!TBI.HasValidInstrDepths) if (!TBI.HasValidInstrDepths)
continue; continue;
// Add live-ins to the critical path length. // Add live-ins to the critical path length.
TBI.CriticalPath = std::max(TBI.CriticalPath, TBI.CriticalPath = std::max(TBI.CriticalPath,
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 522 Lines • ▼ Show 20 Linesvoid MachineVerifier::report_context(const VNInfo &VNI) const {
errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n"; errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
} }
void MachineVerifier::report_context_liverange(const LiveRange &LR) const { void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
errs() << "- liverange: " << LR << '\n'; errs() << "- liverange: " << LR << '\n';
} }
void MachineVerifier::report_context_vreg(unsigned VReg) const { void MachineVerifier::report_context_vreg(unsigned VReg) const {
errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n'; errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
} }
void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const { void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) { if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
report_context_vreg(VRegOrUnit); report_context_vreg(VRegOrUnit);
} else { } else {
errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n'; errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
} }
} }
void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const { void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n'; errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
} }
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) { void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
▲ Show 20 Lines • Show All 1,136 Lines • ▼ Show 20 Linesvoid MachineVerifier::visitMachineFunctionAfter() {
// Check for killed virtual registers that should be live out. // Check for killed virtual registers that should be live out.
for (const auto &MBB : *MF) { for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB]; BBInfo &MInfo = MBBInfoMap[&MBB];
for (RegSet::iterator for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
++I) ++I)
if (MInfo.regsKilled.count(*I)) { if (MInfo.regsKilled.count(*I)) {
report("Virtual register killed in block, but needed live out.", &MBB); report("Virtual register killed in block, but needed live out.", &MBB);
errs() << "Virtual register " << PrintReg(*I) errs() << "Virtual register " << printReg(*I)
<< " is used after the block.\n"; << " is used after the block.\n";
} }
} }
if (!MF->empty()) { if (!MF->empty()) {
BBInfo &MInfo = MBBInfoMap[&MF->front()]; BBInfo &MInfo = MBBInfoMap[&MF->front()];
for (RegSet::iterator for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
Show All 16 Lines for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
for (const auto &MBB : *MF) { for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB]; BBInfo &MInfo = MBBInfoMap[&MBB];
// Our vregsRequired should be identical to LiveVariables' AliveBlocks // Our vregsRequired should be identical to LiveVariables' AliveBlocks
if (MInfo.vregsRequired.count(Reg)) { if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MBB.getNumber())) { if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB); report("LiveVariables: Block missing from AliveBlocks", &MBB);
errs() << "Virtual register " << PrintReg(Reg) errs() << "Virtual register " << printReg(Reg)
<< " must be live through the block.\n"; << " must be live through the block.\n";
} }
} else { } else {
if (VI.AliveBlocks.test(MBB.getNumber())) { if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB); report("LiveVariables: Block should not be in AliveBlocks", &MBB);
errs() << "Virtual register " << PrintReg(Reg) errs() << "Virtual register " << printReg(Reg)
<< " is not needed live through the block.\n"; << " is not needed live through the block.\n";
} }
} }
} }
} }
} }
void MachineVerifier::verifyLiveIntervals() { void MachineVerifier::verifyLiveIntervals() {
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i); unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
// Spilling and splitting may leave unused registers around. Skip them. // Spilling and splitting may leave unused registers around. Skip them.
if (MRI->reg_nodbg_empty(Reg)) if (MRI->reg_nodbg_empty(Reg))
continue; continue;
if (!LiveInts->hasInterval(Reg)) { if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF); report("Missing live interval for virtual register", MF);
errs() << PrintReg(Reg, TRI) << " still has defs or uses\n"; errs() << printReg(Reg, TRI) << " still has defs or uses\n";
continue; continue;
} }
const LiveInterval &LI = LiveInts->getInterval(Reg); const LiveInterval &LI = LiveInts->getInterval(Reg);
assert(Reg == LI.reg && "Invalid reg to interval mapping"); assert(Reg == LI.reg && "Invalid reg to interval mapping");
verifyLiveInterval(LI); verifyLiveInterval(LI);
} }
▲ Show 20 Lines • Show All 479 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/PHIElimination.cpp

Show First 20 Lines • Show All 264 Lines • ▼ Show 20 Lines else {
// Can we reuse an earlier PHI node? This only happens for critical edges, // Can we reuse an earlier PHI node? This only happens for critical edges,
// typically those created by tail duplication. // typically those created by tail duplication.
unsigned &entry = LoweredPHIs[MPhi]; unsigned &entry = LoweredPHIs[MPhi];
if (entry) { if (entry) {
// An identical PHI node was already lowered. Reuse the incoming register. // An identical PHI node was already lowered. Reuse the incoming register.
IncomingReg = entry; IncomingReg = entry;
reusedIncoming = true; reusedIncoming = true;
++NumReused; ++NumReused;
DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi);
} else { } else {
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
} }
BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
TII->get(TargetOpcode::COPY), DestReg) TII->get(TargetOpcode::COPY), DestReg)
.addReg(IncomingReg); .addReg(IncomingReg);
} }
▲ Show 20 Lines • Show All 306 Lines • ▼ Show 20 Lines for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
// use. That means the copy we will insert in PreMBB won't be a kill, and // use. That means the copy we will insert in PreMBB won't be a kill, and
// there is a risk it may not be coalesced away. // there is a risk it may not be coalesced away.
// //
// If the copy would be a kill, there is no need to split the edge. // If the copy would be a kill, there is no need to split the edge.
bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB); bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit) if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
continue; continue;
if (ShouldSplit) { if (ShouldSplit) {
DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#"
<< PreMBB->getNumber() << " -> BB#" << MBB.getNumber() << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
<< ": " << *BBI); << ": " << *BBI);
} }
// If Reg is not live-in to MBB, it means it must be live-in to some // If Reg is not live-in to MBB, it means it must be live-in to some
// other PreMBB successor, and we can avoid the interference by splitting // other PreMBB successor, and we can avoid the interference by splitting
// the edge. // the edge.
// //
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Linesvoid RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI,
LiveReg &LR = *LRI; LiveReg &LR = *LRI;
assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping"); assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
if (LR.Dirty) { if (LR.Dirty) {
// If this physreg is used by the instruction, we want to kill it on the // If this physreg is used by the instruction, we want to kill it on the
// instruction, not on the spill. // instruction, not on the spill.
bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI; bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI;
LR.Dirty = false; LR.Dirty = false;
DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI)
<< " in " << PrintReg(LR.PhysReg, TRI)); << " in " << printReg(LR.PhysReg, TRI));
const TargetRegisterClass &RC = *MRI->getRegClass(LRI->VirtReg); const TargetRegisterClass &RC = *MRI->getRegClass(LRI->VirtReg);
int FI = getStackSpaceFor(LRI->VirtReg, RC); int FI = getStackSpaceFor(LRI->VirtReg, RC);
DEBUG(dbgs() << " to stack slot #" << FI << "\n"); DEBUG(dbgs() << " to stack slot #" << FI << "\n");
TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, &RC, TRI); TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, &RC, TRI);
++NumStores; // Update statistics ++NumStores; // Update statistics
// If this register is used by DBG_VALUE then insert new DBG_VALUE to // If this register is used by DBG_VALUE then insert new DBG_VALUE to
// identify spilled location as the place to find corresponding variable's // identify spilled location as the place to find corresponding variable's
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
} }
/// \brief Return the cost of spilling clearing out PhysReg and aliases so it is /// \brief Return the cost of spilling clearing out PhysReg and aliases so it is
/// free for allocation. Returns 0 when PhysReg is free or disabled with all /// free for allocation. Returns 0 when PhysReg is free or disabled with all
/// aliases disabled - it can be allocated directly. /// aliases disabled - it can be allocated directly.
/// \returns spillImpossible when PhysReg or an alias can't be spilled. /// \returns spillImpossible when PhysReg or an alias can't be spilled.
unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
if (isRegUsedInInstr(PhysReg)) { if (isRegUsedInInstr(PhysReg)) {
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); DEBUG(dbgs() << printReg(PhysReg, TRI) << " is already used in instr.\n");
return spillImpossible; return spillImpossible;
} }
switch (unsigned VirtReg = PhysRegState[PhysReg]) { switch (unsigned VirtReg = PhysRegState[PhysReg]) {
case regDisabled: case regDisabled:
break; break;
case regFree: case regFree:
return 0; return 0;
case regReserved: case regReserved:
DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding "
<< PrintReg(PhysReg, TRI) << " is reserved already.\n"); << printReg(PhysReg, TRI) << " is reserved already.\n");
return spillImpossible; return spillImpossible;
default: { default: {
LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
return I->Dirty ? spillDirty : spillClean; return I->Dirty ? spillDirty : spillClean;
} }
} }
// This is a disabled register, add up cost of aliases. // This is a disabled register, add up cost of aliases.
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n");
unsigned Cost = 0; unsigned Cost = 0;
for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
MCPhysReg Alias = *AI; MCPhysReg Alias = *AI;
switch (unsigned VirtReg = PhysRegState[Alias]) { switch (unsigned VirtReg = PhysRegState[Alias]) {
case regDisabled: case regDisabled:
break; break;
case regFree: case regFree:
++Cost; ++Cost;
Show All 10 Linesunsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
} }
return Cost; return Cost;
} }
/// \brief This method updates local state so that we know that PhysReg is the /// \brief This method updates local state so that we know that PhysReg is the
/// proper container for VirtReg now. The physical register must not be used /// proper container for VirtReg now. The physical register must not be used
/// for anything else when this is called. /// for anything else when this is called.
void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) {
DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to "
<< PrintReg(PhysReg, TRI) << "\n"); << printReg(PhysReg, TRI) << "\n");
PhysRegState[PhysReg] = LR.VirtReg; PhysRegState[PhysReg] = LR.VirtReg;
assert(!LR.PhysReg && "Already assigned a physreg"); assert(!LR.PhysReg && "Already assigned a physreg");
LR.PhysReg = PhysReg; LR.PhysReg = PhysReg;
} }
RegAllocFast::LiveRegMap::iterator RegAllocFast::LiveRegMap::iterator
RegAllocFast::assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg) { RegAllocFast::assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg) {
LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
Show All 29 LinesRegAllocFast::LiveRegMap::iterator RegAllocFast::allocVirtReg(MachineInstr &MI,
ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(&RC); ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(&RC);
for (MCPhysReg PhysReg : AO) { for (MCPhysReg PhysReg : AO) {
if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) { if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
assignVirtToPhysReg(*LRI, PhysReg); assignVirtToPhysReg(*LRI, PhysReg);
return LRI; return LRI;
} }
} }
DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from "
<< TRI->getRegClassName(&RC) << "\n"); << TRI->getRegClassName(&RC) << "\n");
unsigned BestReg = 0; unsigned BestReg = 0;
unsigned BestCost = spillImpossible; unsigned BestCost = spillImpossible;
for (MCPhysReg PhysReg : AO) { for (MCPhysReg PhysReg : AO) {
unsigned Cost = calcSpillCost(PhysReg); unsigned Cost = calcSpillCost(PhysReg);
DEBUG(dbgs() << "\tRegister: " << PrintReg(PhysReg, TRI) << "\n"); DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n");
DEBUG(dbgs() << "\tCost: " << Cost << "\n"); DEBUG(dbgs() << "\tCost: " << Cost << "\n");
DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
// Cost is 0 when all aliases are already disabled. // Cost is 0 when all aliases are already disabled.
if (Cost == 0) { if (Cost == 0) {
assignVirtToPhysReg(*LRI, PhysReg); assignVirtToPhysReg(*LRI, PhysReg);
return LRI; return LRI;
} }
if (Cost < BestCost) if (Cost < BestCost)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 LinesRegAllocFast::LiveRegMap::iterator RegAllocFast::reloadVirtReg(MachineInstr &MI,
LiveRegMap::iterator LRI; LiveRegMap::iterator LRI;
bool New; bool New;
std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
MachineOperand &MO = MI.getOperand(OpNum); MachineOperand &MO = MI.getOperand(OpNum);
if (New) { if (New) {
LRI = allocVirtReg(MI, LRI, Hint); LRI = allocVirtReg(MI, LRI, Hint);
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC); int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into " DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
<< PrintReg(LRI->PhysReg, TRI) << "\n"); << printReg(LRI->PhysReg, TRI) << "\n");
TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, &RC, TRI); TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, &RC, TRI);
++NumLoads; ++NumLoads;
} else if (LRI->Dirty) { } else if (LRI->Dirty) {
if (isLastUseOfLocalReg(MO)) { if (isLastUseOfLocalReg(MO)) {
DEBUG(dbgs() << "Killing last use: " << MO << "\n"); DEBUG(dbgs() << "Killing last use: " << MO << "\n");
if (MO.isUse()) if (MO.isUse())
MO.setIsKill(); MO.setIsKill();
else else
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesvoid RegAllocFast::handleThroughOperands(MachineInstr &MI,
for (const MachineOperand &MO : MI.operands()) { for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg()) continue; if (!MO.isReg()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(Reg)) if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue; continue;
if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) ||
(MO.getSubReg() && MI.readsVirtualRegister(Reg))) { (MO.getSubReg() && MI.readsVirtualRegister(Reg))) {
if (ThroughRegs.insert(Reg).second) if (ThroughRegs.insert(Reg).second)
DEBUG(dbgs() << ' ' << PrintReg(Reg)); DEBUG(dbgs() << ' ' << printReg(Reg));
} }
} }
// If any physreg defines collide with preallocated through registers, // If any physreg defines collide with preallocated through registers,
// we must spill and reallocate. // we must spill and reallocate.
DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
for (const MachineOperand &MO : MI.operands()) { for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef()) continue; if (!MO.isReg() || !MO.isDef()) continue;
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesvoid RegAllocFast::handleThroughOperands(MachineInstr &MI,
} }
// Restore UsedInInstr to a state usable for allocating normal virtual uses. // Restore UsedInInstr to a state usable for allocating normal virtual uses.
UsedInInstr.clear(); UsedInInstr.clear();
for (const MachineOperand &MO : MI.operands()) { for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI) DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI)
<< " as used in instr\n"); << " as used in instr\n");
markRegUsedInInstr(Reg); markRegUsedInInstr(Reg);
} }
// Also mark PartialDefs as used to avoid reallocation. // Also mark PartialDefs as used to avoid reallocation.
for (unsigned PartialDef : PartialDefs) for (unsigned PartialDef : PartialDefs)
markRegUsedInInstr(PartialDef); markRegUsedInInstr(PartialDef);
} }
#ifndef NDEBUG #ifndef NDEBUG
void RegAllocFast::dumpState() { void RegAllocFast::dumpState() {
for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
if (PhysRegState[Reg] == regDisabled) continue; if (PhysRegState[Reg] == regDisabled) continue;
dbgs() << " " << TRI->getName(Reg); dbgs() << " " << TRI->getName(Reg);
switch(PhysRegState[Reg]) { switch(PhysRegState[Reg]) {
case regFree: case regFree:
break; break;
case regReserved: case regReserved:
dbgs() << "*"; dbgs() << "*";
break; break;
default: { default: {
dbgs() << '=' << PrintReg(PhysRegState[Reg]); dbgs() << '=' << printReg(PhysRegState[Reg]);
LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]); LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
if (I->Dirty) if (I->Dirty)
dbgs() << "*"; dbgs() << "*";
assert(I->PhysReg == Reg && "Bad inverse map"); assert(I->PhysReg == Reg && "Bad inverse map");
break; break;
} }
} }
▲ Show 20 Lines • Show All 284 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Show First 20 Lines • Show All 756 Lines • ▼ Show 20 Lines if (!PhysReg || Order.isHint())
return PhysReg; return PhysReg;
// PhysReg is available, but there may be a better choice. // PhysReg is available, but there may be a better choice.
// If we missed a simple hint, try to cheaply evict interference from the // If we missed a simple hint, try to cheaply evict interference from the
// preferred register. // preferred register.
if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
if (Order.isHint(Hint)) { if (Order.isHint(Hint)) {
DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n');
EvictionCost MaxCost; EvictionCost MaxCost;
MaxCost.setBrokenHints(1); MaxCost.setBrokenHints(1);
if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
evictInterference(VirtReg, Hint, NewVRegs); evictInterference(VirtReg, Hint, NewVRegs);
return Hint; return Hint;
} }
// Record the missed hint, we may be able to recover // Record the missed hint, we may be able to recover
// at the end if the surrounding allocation changed. // at the end if the surrounding allocation changed.
SetOfBrokenHints.insert(&VirtReg); SetOfBrokenHints.insert(&VirtReg);
} }
// Try to evict interference from a cheaper alternative. // Try to evict interference from a cheaper alternative.
unsigned Cost = TRI->getCostPerUse(PhysReg); unsigned Cost = TRI->getCostPerUse(PhysReg);
// Most registers have 0 additional cost. // Most registers have 0 additional cost.
if (!Cost) if (!Cost)
return PhysReg; return PhysReg;
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " << Cost
<< '\n'); << '\n');
unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
return CheapReg ? CheapReg : PhysReg; return CheapReg ? CheapReg : PhysReg;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Interference eviction // Interference eviction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 13 Lines for (; Units.isValid(); ++Units) {
break; break;
} }
// If no units have interference, break out with the current PhysReg. // If no units have interference, break out with the current PhysReg.
if (!Units.isValid()) if (!Units.isValid())
break; break;
} }
if (PhysReg) if (PhysReg)
DEBUG(dbgs() << "can reassign: " << VirtReg << " from " DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
<< PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) << printReg(PrevReg, TRI) << " to " << printReg(PhysReg, TRI)
<< '\n'); << '\n');
return PhysReg; return PhysReg;
} }
/// shouldEvict - determine if A should evict the assigned live range B. The /// shouldEvict - determine if A should evict the assigned live range B. The
/// eviction policy defined by this function together with the allocation order /// eviction policy defined by this function together with the allocation order
/// defined by enqueue() decides which registers ultimately end up being split /// defined by enqueue() decides which registers ultimately end up being split
/// and spilled. /// and spilled.
▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Linesvoid RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
SmallVectorImpl<unsigned> &NewVRegs) { SmallVectorImpl<unsigned> &NewVRegs) {
// Make sure that VirtReg has a cascade number, and assign that cascade // Make sure that VirtReg has a cascade number, and assign that cascade
// number to every evicted register. These live ranges than then only be // number to every evicted register. These live ranges than then only be
// evicted by a newer cascade, preventing infinite loops. // evicted by a newer cascade, preventing infinite loops.
unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
if (!Cascade) if (!Cascade)
Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
<< " interference: Cascade " << Cascade << '\n'); << " interference: Cascade " << Cascade << '\n');
// Collect all interfering virtregs first. // Collect all interfering virtregs first.
SmallVector<LiveInterval*, 8> Intfs; SmallVector<LiveInterval*, 8> Intfs;
for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
// We usually have the interfering VRegs cached so collectInterferingVRegs() // We usually have the interfering VRegs cached so collectInterferingVRegs()
// should be fast, we may need to recalculate if when different physregs // should be fast, we may need to recalculate if when different physregs
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesunsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
Order.rewind(); Order.rewind();
while (unsigned PhysReg = Order.next(OrderLimit)) { while (unsigned PhysReg = Order.next(OrderLimit)) {
if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit) if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
continue; continue;
// The first use of a callee-saved register in a function has cost 1. // The first use of a callee-saved register in a function has cost 1.
// Don't start using a CSR when the CostPerUseLimit is low. // Don't start using a CSR when the CostPerUseLimit is low.
if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) { if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " DEBUG(dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
<< PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
<< '\n'); << '\n');
continue; continue;
} }
if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
continue; continue;
// Best so far. // Best so far.
▲ Show 20 Lines • Show All 648 Lines • ▼ Show 20 Lines while (unsigned PhysReg = Order.next()) {
if (GlobalCand.size() <= NumCands) if (GlobalCand.size() <= NumCands)
GlobalCand.resize(NumCands+1); GlobalCand.resize(NumCands+1);
GlobalSplitCandidate &Cand = GlobalCand[NumCands]; GlobalSplitCandidate &Cand = GlobalCand[NumCands];
Cand.reset(IntfCache, PhysReg); Cand.reset(IntfCache, PhysReg);
SpillPlacer->prepare(Cand.LiveBundles); SpillPlacer->prepare(Cand.LiveBundles);
BlockFrequency Cost; BlockFrequency Cost;
if (!addSplitConstraints(Cand.Intf, Cost)) { if (!addSplitConstraints(Cand.Intf, Cost)) {
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
continue; continue;
} }
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = "; DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = ";
MBFI->printBlockFreq(dbgs(), Cost)); MBFI->printBlockFreq(dbgs(), Cost));
if (Cost >= BestCost) { if (Cost >= BestCost) {
DEBUG({ DEBUG({
if (BestCand == NoCand) if (BestCand == NoCand)
dbgs() << " worse than no bundles\n"; dbgs() << " worse than no bundles\n";
else else
dbgs() << " worse than " dbgs() << " worse than "
<< PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
}); });
continue; continue;
} }
growRegion(Cand); growRegion(Cand);
SpillPlacer->finish(); SpillPlacer->finish();
// No live bundles, defer to splitSingleBlocks(). // No live bundles, defer to splitSingleBlocks().
Show All 21 Lines while (unsigned PhysReg = Order.next()) {
} }
++NumCands; ++NumCands;
} }
if (CanCauseEvictionChain && BestCand != NoCand) { if (CanCauseEvictionChain && BestCand != NoCand) {
// See splitCanCauseEvictionChain for detailed description of bad // See splitCanCauseEvictionChain for detailed description of bad
// eviction chain scenarios. // eviction chain scenarios.
DEBUG(dbgs() << "Best split candidate of vreg " DEBUG(dbgs() << "Best split candidate of vreg "
<< PrintReg(VirtReg.reg, TRI) << " may "); << printReg(VirtReg.reg, TRI) << " may ");
if (!(*CanCauseEvictionChain)) if (!(*CanCauseEvictionChain))
DEBUG(dbgs() << "not "); DEBUG(dbgs() << "not ");
DEBUG(dbgs() << "cause bad eviction chain\n"); DEBUG(dbgs() << "cause bad eviction chain\n");
} }
return BestCand; return BestCand;
} }
Show All 9 Linesunsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
BundleCand.assign(Bundles->getNumBundles(), NoCand); BundleCand.assign(Bundles->getNumBundles(), NoCand);
// Assign bundles for the best candidate region. // Assign bundles for the best candidate region.
if (BestCand != NoCand) { if (BestCand != NoCand) {
GlobalSplitCandidate &Cand = GlobalCand[BestCand]; GlobalSplitCandidate &Cand = GlobalCand[BestCand];
if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
UsedCands.push_back(BestCand); UsedCands.push_back(BestCand);
Cand.IntvIdx = SE->openIntv(); Cand.IntvIdx = SE->openIntv();
DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
<< B << " bundles, intv " << Cand.IntvIdx << ".\n"); << B << " bundles, intv " << Cand.IntvIdx << ".\n");
(void)B; (void)B;
} }
} }
// Assign bundles for the compact region. // Assign bundles for the compact region.
if (HasCompact) { if (HasCompact) {
GlobalSplitCandidate &Cand = GlobalCand.front(); GlobalSplitCandidate &Cand = GlobalCand.front();
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines while (unsigned PhysReg = Order.next()) {
// It is the spill weight that needs to be evicted. // It is the spill weight that needs to be evicted.
float MaxGap = GapWeight[0]; float MaxGap = GapWeight[0];
while (true) { while (true) {
// Live before/after split? // Live before/after split?
const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' ' DEBUG(dbgs() << printReg(PhysReg, TRI) << ' '
<< Uses[SplitBefore] << '-' << Uses[SplitAfter] << Uses[SplitBefore] << '-' << Uses[SplitAfter]
<< " i=" << MaxGap); << " i=" << MaxGap);
// Stop before the interval gets so big we wouldn't be making progress. // Stop before the interval gets so big we wouldn't be making progress.
if (!LiveBefore && !LiveAfter) { if (!LiveBefore && !LiveAfter) {
DEBUG(dbgs() << " all\n"); DEBUG(dbgs() << " all\n");
break; break;
} }
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Linesunsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter; unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
if (NewGaps >= NumGaps) { if (NewGaps >= NumGaps) {
DEBUG(dbgs() << "Tagging non-progress ranges: "); DEBUG(dbgs() << "Tagging non-progress ranges: ");
assert(!ProgressRequired && "Didn't make progress when it was required."); assert(!ProgressRequired && "Didn't make progress when it was required.");
for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
if (IntvMap[i] == 1) { if (IntvMap[i] == 1) {
setStage(LIS->getInterval(LREdit.get(i)), RS_Split2); setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
DEBUG(dbgs() << PrintReg(LREdit.get(i))); DEBUG(dbgs() << printReg(LREdit.get(i)));
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
++NumLocalSplits; ++NumLocalSplits;
return 0; return 0;
} }
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Linesunsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
// Mark VirtReg as fixed, i.e., it will not be recolored pass this point in // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
// this recoloring "session". // this recoloring "session".
FixedRegisters.insert(VirtReg.reg); FixedRegisters.insert(VirtReg.reg);
SmallVector<unsigned, 4> CurrentNewVRegs; SmallVector<unsigned, 4> CurrentNewVRegs;
Order.rewind(); Order.rewind();
while (unsigned PhysReg = Order.next()) { while (unsigned PhysReg = Order.next()) {
DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
<< PrintReg(PhysReg, TRI) << '\n'); << printReg(PhysReg, TRI) << '\n');
RecoloringCandidates.clear(); RecoloringCandidates.clear();
VirtRegToPhysReg.clear(); VirtRegToPhysReg.clear();
CurrentNewVRegs.clear(); CurrentNewVRegs.clear();
// It is only possible to recolor virtual register interference. // It is only possible to recolor virtual register interference.
if (Matrix->checkInterference(VirtReg, PhysReg) > if (Matrix->checkInterference(VirtReg, PhysReg) >
LiveRegMatrix::IK_VirtReg) { LiveRegMatrix::IK_VirtReg) {
DEBUG(dbgs() << "Some interferences are not with virtual registers.\n"); DEBUG(dbgs() << "Some interferences are not with virtual registers.\n");
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines if (tryRecoloringCandidates(RecoloringQueue, CurrentNewVRegs,
NewVRegs.push_back(NewVReg); NewVRegs.push_back(NewVReg);
// Do not mess up with the global assignment process. // Do not mess up with the global assignment process.
// I.e., VirtReg must be unassigned. // I.e., VirtReg must be unassigned.
Matrix->unassign(VirtReg); Matrix->unassign(VirtReg);
return PhysReg; return PhysReg;
} }
DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
<< PrintReg(PhysReg, TRI) << '\n'); << printReg(PhysReg, TRI) << '\n');
// The recoloring attempt failed, undo the changes. // The recoloring attempt failed, undo the changes.
FixedRegisters = SaveFixedRegisters; FixedRegisters = SaveFixedRegisters;
Matrix->unassign(VirtReg); Matrix->unassign(VirtReg);
// For a newly created vreg which is also in RecoloringCandidates, // For a newly created vreg which is also in RecoloringCandidates,
// don't add it to NewVRegs because its physical register will be restored // don't add it to NewVRegs because its physical register will be restored
// below. Other vregs in CurrentNewVRegs are created by calling // below. Other vregs in CurrentNewVRegs are created by calling
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines if (PhysReg == ~0u || (!PhysReg && !LI->empty()))
return false; return false;
if (!PhysReg) { if (!PhysReg) {
assert(LI->empty() && "Only empty live-range do not require a register"); assert(LI->empty() && "Only empty live-range do not require a register");
DEBUG(dbgs() << "Recoloring of " << *LI << " succeeded. Empty LI.\n"); DEBUG(dbgs() << "Recoloring of " << *LI << " succeeded. Empty LI.\n");
continue; continue;
} }
DEBUG(dbgs() << "Recoloring of " << *LI DEBUG(dbgs() << "Recoloring of " << *LI
<< " succeeded with: " << PrintReg(PhysReg, TRI) << '\n'); << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
Matrix->assign(*LI, PhysReg); Matrix->assign(*LI, PhysReg);
FixedRegisters.insert(LI->reg); FixedRegisters.insert(LI->reg);
} }
return true; return true;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Linesvoid RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) {
HintsInfo Info; HintsInfo Info;
unsigned Reg = VirtReg.reg; unsigned Reg = VirtReg.reg;
unsigned PhysReg = VRM->getPhys(Reg); unsigned PhysReg = VRM->getPhys(Reg);
// Start the recoloring algorithm from the input live-interval, then // Start the recoloring algorithm from the input live-interval, then
// it will propagate to the ones that are copy-related with it. // it will propagate to the ones that are copy-related with it.
Visited.insert(Reg); Visited.insert(Reg);
RecoloringCandidates.push_back(Reg); RecoloringCandidates.push_back(Reg);
DEBUG(dbgs() << "Trying to reconcile hints for: " << PrintReg(Reg, TRI) << '(' DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) << '('
<< PrintReg(PhysReg, TRI) << ")\n"); << printReg(PhysReg, TRI) << ")\n");
do { do {
Reg = RecoloringCandidates.pop_back_val(); Reg = RecoloringCandidates.pop_back_val();
// We cannot recolor physical register. // We cannot recolor physical register.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) if (TargetRegisterInfo::isPhysicalRegister(Reg))
continue; continue;
assert(VRM->hasPhys(Reg) && "We have unallocated variable!!"); assert(VRM->hasPhys(Reg) && "We have unallocated variable!!");
// Get the live interval mapped with this virtual register to be able // Get the live interval mapped with this virtual register to be able
// to check for the interference with the new color. // to check for the interference with the new color.
LiveInterval &LI = LIS->getInterval(Reg); LiveInterval &LI = LIS->getInterval(Reg);
unsigned CurrPhys = VRM->getPhys(Reg); unsigned CurrPhys = VRM->getPhys(Reg);
// Check that the new color matches the register class constraints and // Check that the new color matches the register class constraints and
// that it is free for this live range. // that it is free for this live range.
if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) || if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
Matrix->checkInterference(LI, PhysReg))) Matrix->checkInterference(LI, PhysReg)))
continue; continue;
DEBUG(dbgs() << PrintReg(Reg, TRI) << '(' << PrintReg(CurrPhys, TRI) DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
<< ") is recolorable.\n"); << ") is recolorable.\n");
// Gather the hint info. // Gather the hint info.
Info.clear(); Info.clear();
collectHintInfo(Reg, Info); collectHintInfo(Reg, Info);
// Check if recoloring the live-range will increase the cost of the // Check if recoloring the live-range will increase the cost of the
// non-identity copies. // non-identity copies.
if (CurrPhys != PhysReg) { if (CurrPhys != PhysReg) {
▲ Show 20 Lines • Show All 301 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp

Show First 20 Lines • Show All 662 Lines • ▼ Show 20 Linesvoid RegAllocPBQP::spillVReg(unsigned VReg,
VirtRegMap &VRM, Spiller &VRegSpiller) { VirtRegMap &VRM, Spiller &VRegSpiller) {
VRegsToAlloc.erase(VReg); VRegsToAlloc.erase(VReg);
LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM, LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
nullptr, &DeadRemats); nullptr, &DeadRemats);
VRegSpiller.spill(LRE); VRegSpiller.spill(LRE);
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
(void)TRI; (void)TRI;
DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: " DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: "
<< LRE.getParent().weight << ", New vregs: "); << LRE.getParent().weight << ", New vregs: ");
// Copy any newly inserted live intervals into the list of regs to // Copy any newly inserted live intervals into the list of regs to
// allocate. // allocate.
for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end(); for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
I != E; ++I) { I != E; ++I) {
const LiveInterval &LI = LIS.getInterval(*I); const LiveInterval &LI = LIS.getInterval(*I);
assert(!LI.empty() && "Empty spill range."); assert(!LI.empty() && "Empty spill range.");
DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " "); DEBUG(dbgs() << printReg(LI.reg, &TRI) << " ");
VRegsToAlloc.insert(LI.reg); VRegsToAlloc.insert(LI.reg);
} }
DEBUG(dbgs() << ")\n"); DEBUG(dbgs() << ")\n");
} }
bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G, bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
const PBQP::Solution &Solution, const PBQP::Solution &Solution,
Show All 13 Linesbool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
// Iterate over the nodes mapping the PBQP solution to a register // Iterate over the nodes mapping the PBQP solution to a register
// assignment. // assignment.
for (auto NId : G.nodeIds()) { for (auto NId : G.nodeIds()) {
unsigned VReg = G.getNodeMetadata(NId).getVReg(); unsigned VReg = G.getNodeMetadata(NId).getVReg();
unsigned AllocOption = Solution.getSelection(NId); unsigned AllocOption = Solution.getSelection(NId);
if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) { if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> " DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> "
<< TRI.getName(PReg) << "\n"); << TRI.getName(PReg) << "\n");
assert(PReg != 0 && "Invalid preg selected."); assert(PReg != 0 && "Invalid preg selected.");
VRM.assignVirt2Phys(VReg, PReg); VRM.assignVirt2Phys(VReg, PReg);
} else { } else {
// Spill VReg. If this introduces new intervals we'll need another round // Spill VReg. If this introduces new intervals we'll need another round
// of allocation. // of allocation.
SmallVector<unsigned, 8> NewVRegs; SmallVector<unsigned, 8> NewVRegs;
spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
/// Create Printable object for node and register info. /// Create Printable object for node and register info.
static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId, static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
const PBQP::RegAlloc::PBQPRAGraph &G) { const PBQP::RegAlloc::PBQPRAGraph &G) {
return Printable([NId, &G](raw_ostream &OS) { return Printable([NId, &G](raw_ostream &OS) {
const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo(); const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
unsigned VReg = G.getNodeMetadata(NId).getVReg(); unsigned VReg = G.getNodeMetadata(NId).getVReg();
const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')'; OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')';
}); });
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const { LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
for (auto NId : nodeIds()) { for (auto NId : nodeIds()) {
const Vector &Costs = getNodeCosts(NId); const Vector &Costs = getNodeCosts(NId);
assert(Costs.getLength() != 0 && "Empty vector in graph."); assert(Costs.getLength() != 0 && "Empty vector in graph.");
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
RCI.ProperSubClass = true; RCI.ProperSubClass = true;
RCI.MinCost = uint8_t(MinCost); RCI.MinCost = uint8_t(MinCost);
RCI.LastCostChange = LastCostChange; RCI.LastCostChange = LastCostChange;
DEBUG({ DEBUG({
dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
for (unsigned I = 0; I != RCI.NumRegs; ++I) for (unsigned I = 0; I != RCI.NumRegs; ++I)
dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); dbgs() << ' ' << printReg(RCI.Order[I], TRI);
dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
}); });
// RCI is now up-to-date. // RCI is now up-to-date.
RCI.Tag = Tag; RCI.Tag = Tag;
} }
/// This is not accurate because two overlapping register sets may have some /// This is not accurate because two overlapping register sets may have some
Show All 27 Lines

llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Show First 20 Lines • Show All 563 Lines • ▼ Show 20 Linesbool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent()) if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
return false; return false;
// Okay, we now know that ValS ends in the same block that the CopyMI // Okay, we now know that ValS ends in the same block that the CopyMI
// live-range starts. If there are no intervening live segments between them // live-range starts. If there are no intervening live segments between them
// in IntB, we can merge them. // in IntB, we can merge them.
if (ValS+1 != BS) return false; if (ValS+1 != BS) return false;
DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI)); DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI));
SlotIndex FillerStart = ValS->end, FillerEnd = BS->start; SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
// We are about to delete CopyMI, so need to remove it as the 'instruction // We are about to delete CopyMI, so need to remove it as the 'instruction
// that defines this value #'. Update the valnum with the new defining // that defines this value #'. Update the valnum with the new defining
// instruction #. // instruction #.
BValNo->def = FillerStart; BValNo->def = FillerStart;
// Okay, we can merge them. We need to insert a new liverange: // Okay, we can merge them. We need to insert a new liverange:
▲ Show 20 Lines • Show All 1,052 Lines • ▼ Show 20 Lines if (VNInfo *DefVNI = LRQ.valueDefined()) {
DEBUG(dbgs() << "\tMerged values: " << LI << '\n'); DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
} }
deleteInstr(CopyMI); deleteInstr(CopyMI);
return true; return true;
} }
// Enforce policies. // Enforce policies.
if (CP.isPhys()) { if (CP.isPhys()) {
DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI) DEBUG(dbgs() << "\tConsidering merging " << printReg(CP.getSrcReg(), TRI)
<< " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << " with " << printReg(CP.getDstReg(), TRI, CP.getSrcIdx())
<< '\n'); << '\n');
if (!canJoinPhys(CP)) { if (!canJoinPhys(CP)) {
// Before giving up coalescing, if definition of source is defined by // Before giving up coalescing, if definition of source is defined by
// trivial computation, try rematerializing it. // trivial computation, try rematerializing it.
bool IsDefCopy; bool IsDefCopy;
if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy)) if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
return true; return true;
if (IsDefCopy) if (IsDefCopy)
Again = true; // May be possible to coalesce later. Again = true; // May be possible to coalesce later.
return false; return false;
} }
} else { } else {
// When possible, let DstReg be the larger interval. // When possible, let DstReg be the larger interval.
if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() > if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
LIS->getInterval(CP.getDstReg()).size()) LIS->getInterval(CP.getDstReg()).size())
CP.flip(); CP.flip();
DEBUG({ DEBUG({
dbgs() << "\tConsidering merging to " dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "; << TRI->getRegClassName(CP.getNewRC()) << " with ";
if (CP.getDstIdx() && CP.getSrcIdx()) if (CP.getDstIdx() && CP.getSrcIdx())
dbgs() << PrintReg(CP.getDstReg()) << " in " dbgs() << printReg(CP.getDstReg()) << " in "
<< TRI->getSubRegIndexName(CP.getDstIdx()) << " and " << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
<< PrintReg(CP.getSrcReg()) << " in " << printReg(CP.getSrcReg()) << " in "
<< TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n'; << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
else else
dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in " dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
<< PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
}); });
} }
ShrinkMask = LaneBitmask::getNone(); ShrinkMask = LaneBitmask::getNone();
ShrinkMainRange = false; ShrinkMainRange = false;
// Okay, attempt to join these two intervals. On failure, this returns false. // Okay, attempt to join these two intervals. On failure, this returns false.
// Otherwise, if one of the intervals being joined is a physreg, this method // Otherwise, if one of the intervals being joined is a physreg, this method
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesbool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
// SrcReg is guaranteed to be the register whose live interval that is // SrcReg is guaranteed to be the register whose live interval that is
// being merged. // being merged.
LIS->removeInterval(CP.getSrcReg()); LIS->removeInterval(CP.getSrcReg());
// Update regalloc hint. // Update regalloc hint.
TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
DEBUG({ DEBUG({
dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
<< " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; dbgs() << "\tResult = ";
if (CP.isPhys()) if (CP.isPhys())
dbgs() << PrintReg(CP.getDstReg(), TRI); dbgs() << printReg(CP.getDstReg(), TRI);
else else
dbgs() << LIS->getInterval(CP.getDstReg()); dbgs() << LIS->getInterval(CP.getDstReg());
dbgs() << '\n'; dbgs() << '\n';
}); });
++numJoins; ++numJoins;
return true; return true;
} }
Show All 18 Linesbool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
if (!MRI->isConstantPhysReg(DstReg)) { if (!MRI->isConstantPhysReg(DstReg)) {
for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) { for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
// Abort if not all the regunits are reserved. // Abort if not all the regunits are reserved.
for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) { for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
if (!MRI->isReserved(*RI)) if (!MRI->isReserved(*RI))
return false; return false;
} }
if (RHS.overlaps(LIS->getRegUnit(*UI))) { if (RHS.overlaps(LIS->getRegUnit(*UI))) {
DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n'); DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI) << '\n');
return false; return false;
} }
} }
// We must also check for overlaps with regmask clobbers. // We must also check for overlaps with regmask clobbers.
BitVector RegMaskUsable; BitVector RegMaskUsable;
if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) && if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
!RegMaskUsable.test(DstReg)) { !RegMaskUsable.test(DstReg)) {
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines if (!MRI->isConstantPhysReg(DstReg)) {
DEBUG(dbgs() << "\t\tInterference (read): " << *MI); DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
return false; return false;
} }
} }
} }
// We're going to remove the copy which defines a physical reserved // We're going to remove the copy which defines a physical reserved
// register, so remove its valno, etc. // register, so remove its valno, etc.
DEBUG(dbgs() << "\t\tRemoving phys reg def of " << PrintReg(DstReg, TRI) DEBUG(dbgs() << "\t\tRemoving phys reg def of " << printReg(DstReg, TRI)
<< " at " << CopyRegIdx << "\n"); << " at " << CopyRegIdx << "\n");
LIS->removePhysRegDefAt(DstReg, CopyRegIdx); LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
// Create a new dead def at the new def location. // Create a new dead def at the new def location.
for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) { for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
LiveRange &LR = LIS->getRegUnit(*UI); LiveRange &LR = LIS->getRegUnit(*UI);
LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator()); LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator());
} }
▲ Show 20 Lines • Show All 604 Lines • ▼ Show 20 Linesvoid JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
} }
switch ((V.Resolution = analyzeValue(ValNo, Other))) { switch ((V.Resolution = analyzeValue(ValNo, Other))) {
case CR_Erase: case CR_Erase:
case CR_Merge: case CR_Merge:
// Merge this ValNo into OtherVNI. // Merge this ValNo into OtherVNI.
assert(V.OtherVNI && "OtherVNI not assigned, can't merge."); assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion"); assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
Assignments[ValNo] = Other.Assignments[V.OtherVNI->id]; Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
DEBUG(dbgs() << "\t\tmerge " << PrintReg(Reg) << ':' << ValNo << '@' DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
<< LR.getValNumInfo(ValNo)->def << " into " << LR.getValNumInfo(ValNo)->def << " into "
<< PrintReg(Other.Reg) << ':' << V.OtherVNI->id << '@' << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
<< V.OtherVNI->def << " --> @" << V.OtherVNI->def << " --> @"
<< NewVNInfo[Assignments[ValNo]]->def << '\n'); << NewVNInfo[Assignments[ValNo]]->def << '\n');
break; break;
case CR_Replace: case CR_Replace:
case CR_Unresolved: { case CR_Unresolved: {
// The other value is going to be pruned if this join is successful. // The other value is going to be pruned if this join is successful.
assert(V.OtherVNI && "OtherVNI not assigned, can't prune"); assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
Val &OtherV = Other.Vals[V.OtherVNI->id]; Val &OtherV = Other.Vals[V.OtherVNI->id];
Show All 11 Lines default:
break; break;
} }
} }
bool JoinVals::mapValues(JoinVals &Other) { bool JoinVals::mapValues(JoinVals &Other) {
for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) { for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
computeAssignment(i, Other); computeAssignment(i, Other);
if (Vals[i].Resolution == CR_Impossible) { if (Vals[i].Resolution == CR_Impossible) {
DEBUG(dbgs() << "\t\tinterference at " << PrintReg(Reg) << ':' << i DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
<< '@' << LR.getValNumInfo(i)->def << '\n'); << '@' << LR.getValNumInfo(i)->def << '\n');
return false; return false;
} }
} }
return true; return true;
} }
bool JoinVals:: bool JoinVals::
taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other, taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent) { SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent) {
VNInfo *VNI = LR.getValNumInfo(ValNo); VNInfo *VNI = LR.getValNumInfo(ValNo);
MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def); MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB); SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
// Scan Other.LR from VNI.def to MBBEnd. // Scan Other.LR from VNI.def to MBBEnd.
LiveInterval::iterator OtherI = Other.LR.find(VNI->def); LiveInterval::iterator OtherI = Other.LR.find(VNI->def);
assert(OtherI != Other.LR.end() && "No conflict?"); assert(OtherI != Other.LR.end() && "No conflict?");
do { do {
// OtherI is pointing to a tainted value. Abort the join if the tainted // OtherI is pointing to a tainted value. Abort the join if the tainted
// lanes escape the block. // lanes escape the block.
SlotIndex End = OtherI->end; SlotIndex End = OtherI->end;
if (End >= MBBEnd) { if (End >= MBBEnd) {
DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.Reg) << ':' DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
<< OtherI->valno->id << '@' << OtherI->start << '\n'); << OtherI->valno->id << '@' << OtherI->start << '\n');
return false; return false;
} }
DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.Reg) << ':' DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
<< OtherI->valno->id << '@' << OtherI->start << OtherI->valno->id << '@' << OtherI->start
<< " to " << End << '\n'); << " to " << End << '\n');
// A dead def is not a problem. // A dead def is not a problem.
if (End.isDead()) if (End.isDead())
break; break;
TaintExtent.push_back(std::make_pair(End, TaintedLanes)); TaintExtent.push_back(std::make_pair(End, TaintedLanes));
// Check for another def in the MBB. // Check for another def in the MBB.
Show All 26 Lines
} }
bool JoinVals::resolveConflicts(JoinVals &Other) { bool JoinVals::resolveConflicts(JoinVals &Other) {
for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) { for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
Val &V = Vals[i]; Val &V = Vals[i];
assert(V.Resolution != CR_Impossible && "Unresolvable conflict"); assert(V.Resolution != CR_Impossible && "Unresolvable conflict");
if (V.Resolution != CR_Unresolved) if (V.Resolution != CR_Unresolved)
continue; continue;
DEBUG(dbgs() << "\t\tconflict at " << PrintReg(Reg) << ':' << i DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i
<< '@' << LR.getValNumInfo(i)->def << '\n'); << '@' << LR.getValNumInfo(i)->def << '\n');
if (SubRangeJoin) if (SubRangeJoin)
return false; return false;
++NumLaneConflicts; ++NumLaneConflicts;
assert(V.OtherVNI && "Inconsistent conflict resolution."); assert(V.OtherVNI && "Inconsistent conflict resolution.");
VNInfo *VNI = LR.getValNumInfo(i); VNInfo *VNI = LR.getValNumInfo(i);
const Val &OtherV = Other.Vals[V.OtherVNI->id]; const Val &OtherV = Other.Vals[V.OtherVNI->id];
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines case CR_Replace: {
} }
} }
} }
// This value will reach instructions below, but we need to make sure // This value will reach instructions below, but we need to make sure
// the live range also reaches the instruction at Def. // the live range also reaches the instruction at Def.
if (!EraseImpDef) if (!EraseImpDef)
EndPoints.push_back(Def); EndPoints.push_back(Def);
} }
DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.Reg) << " at " << Def DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
<< ": " << Other.LR << '\n'); << ": " << Other.LR << '\n');
break; break;
} }
case CR_Erase: case CR_Erase:
case CR_Merge: case CR_Merge:
if (isPrunedValue(i, Other)) { if (isPrunedValue(i, Other)) {
// This value is ultimately a copy of a pruned value in LR or Other.LR. // This value is ultimately a copy of a pruned value in LR or Other.LR.
// We can no longer trust the value mapping computed by // We can no longer trust the value mapping computed by
// computeAssignment(), the value that was originally copied could have // computeAssignment(), the value that was originally copied could have
// been replaced. // been replaced.
LIS->pruneValue(LR, Def, &EndPoints); LIS->pruneValue(LR, Def, &EndPoints);
DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(Reg) << " at " DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
<< Def << ": " << LR << '\n'); << Def << ": " << LR << '\n');
} }
break; break;
case CR_Unresolved: case CR_Unresolved:
case CR_Impossible: case CR_Impossible:
llvm_unreachable("Unresolved conflicts"); llvm_unreachable("Unresolved conflicts");
} }
} }
▲ Show 20 Lines • Show All 291 Lines • ▼ Show 20 Lines if (!LHS.hasSubRanges()) {
LHS.createSubRangeFrom(Allocator, Mask, LHS); LHS.createSubRangeFrom(Allocator, Mask, LHS);
} else if (DstIdx != 0) { } else if (DstIdx != 0) {
// Transform LHS lanemasks to new register class if necessary. // Transform LHS lanemasks to new register class if necessary.
for (LiveInterval::SubRange &R : LHS.subranges()) { for (LiveInterval::SubRange &R : LHS.subranges()) {
LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask); LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
R.LaneMask = Mask; R.LaneMask = Mask;
} }
} }
DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg()) DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg())
<< ' ' << LHS << '\n'); << ' ' << LHS << '\n');
// Determine lanemasks of RHS in the coalesced register and merge subranges. // Determine lanemasks of RHS in the coalesced register and merge subranges.
unsigned SrcIdx = CP.getSrcIdx(); unsigned SrcIdx = CP.getSrcIdx();
if (!RHS.hasSubRanges()) { if (!RHS.hasSubRanges()) {
LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask() LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
: TRI->getSubRegIndexLaneMask(SrcIdx); : TRI->getSubRegIndexLaneMask(SrcIdx);
mergeSubRangeInto(LHS, RHS, Mask, CP); mergeSubRangeInto(LHS, RHS, Mask, CP);
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines for (const MachineInstr &MI : MRI->reg_nodbg_instructions(SrcReg)) {
if (OtherReg == SrcReg) if (OtherReg == SrcReg)
OtherReg = OtherSrcReg; OtherReg = OtherSrcReg;
// Check if OtherReg is a non-terminal. // Check if OtherReg is a non-terminal.
if (TargetRegisterInfo::isPhysicalRegister(OtherReg) || if (TargetRegisterInfo::isPhysicalRegister(OtherReg) ||
isTerminalReg(OtherReg, MI, MRI)) isTerminalReg(OtherReg, MI, MRI))
continue; continue;
// Check that OtherReg interfere with DstReg. // Check that OtherReg interfere with DstReg.
if (LIS->getInterval(OtherReg).overlaps(DstLI)) { if (LIS->getInterval(OtherReg).overlaps(DstLI)) {
DEBUG(dbgs() << "Apply terminal rule for: " << PrintReg(DstReg) << '\n'); DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) << '\n');
return true; return true;
} }
} }
return false; return false;
} }
void void
RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) { RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Linesbool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()), InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
InflateRegs.end()); InflateRegs.end());
DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n"); DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) { for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
unsigned Reg = InflateRegs[i]; unsigned Reg = InflateRegs[i];
if (MRI->reg_nodbg_empty(Reg)) if (MRI->reg_nodbg_empty(Reg))
continue; continue;
if (MRI->recomputeRegClass(Reg)) { if (MRI->recomputeRegClass(Reg)) {
DEBUG(dbgs() << PrintReg(Reg) << " inflated to " DEBUG(dbgs() << printReg(Reg) << " inflated to "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
++NumInflated; ++NumInflated;
LiveInterval &LI = LIS->getInterval(Reg); LiveInterval &LI = LIS->getInterval(Reg);
if (LI.hasSubRanges()) { if (LI.hasSubRanges()) {
// If the inflated register class does not support subregisters anymore // If the inflated register class does not support subregisters anymore
// remove the subranges. // remove the subranges.
if (!MRI->shouldTrackSubRegLiveness(Reg)) { if (!MRI->shouldTrackSubRegLiveness(Reg)) {
Show All 24 Lines

llvm/trunk/lib/CodeGen/RegisterPressure.cpp

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
} }
LLVM_DUMP_METHOD LLVM_DUMP_METHOD
void RegisterPressure::dump(const TargetRegisterInfo *TRI) const { void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
dbgs() << "Max Pressure: "; dbgs() << "Max Pressure: ";
dumpRegSetPressure(MaxSetPressure, TRI); dumpRegSetPressure(MaxSetPressure, TRI);
dbgs() << "Live In: "; dbgs() << "Live In: ";
for (const RegisterMaskPair &P : LiveInRegs) { for (const RegisterMaskPair &P : LiveInRegs) {
dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); dbgs() << printVRegOrUnit(P.RegUnit, TRI);
if (!P.LaneMask.all()) if (!P.LaneMask.all())
dbgs() << ':' << PrintLaneMask(P.LaneMask); dbgs() << ':' << PrintLaneMask(P.LaneMask);
dbgs() << ' '; dbgs() << ' ';
} }
dbgs() << '\n'; dbgs() << '\n';
dbgs() << "Live Out: "; dbgs() << "Live Out: ";
for (const RegisterMaskPair &P : LiveOutRegs) { for (const RegisterMaskPair &P : LiveOutRegs) {
dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); dbgs() << printVRegOrUnit(P.RegUnit, TRI);
if (!P.LaneMask.all()) if (!P.LaneMask.all())
dbgs() << ':' << PrintLaneMask(P.LaneMask); dbgs() << ':' << PrintLaneMask(P.LaneMask);
dbgs() << ' '; dbgs() << ' ';
} }
dbgs() << '\n'; dbgs() << '\n';
} }
LLVM_DUMP_METHOD LLVM_DUMP_METHOD
▲ Show 20 Lines • Show All 1,256 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

Show First 20 Lines • Show All 592 Lines • ▼ Show 20 Linesunsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
if (SpillBefore != MBB.end()) { if (SpillBefore != MBB.end()) {
MachineBasicBlock::iterator ReloadAfter = MachineBasicBlock::iterator ReloadAfter =
RestoreAfter ? std::next(MBBI) : MBBI; RestoreAfter ? std::next(MBBI) : MBBI;
MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter); MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n'); DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
Scavenged.Restore = &*std::prev(SpillBefore); Scavenged.Restore = &*std::prev(SpillBefore);
LiveUnits.removeReg(Reg); LiveUnits.removeReg(Reg);
DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI) DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
<< " until " << *SpillBefore); << " until " << *SpillBefore);
} else { } else {
DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n'); DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n');
} }
return Reg; return Reg;
} }
/// Allocate a register for the virtual register \p VReg. The last use of /// Allocate a register for the virtual register \p VReg. The last use of
/// \p VReg is around the current position of the register scavenger \p RS. /// \p VReg is around the current position of the register scavenger \p RS.
/// \p ReserveAfter controls whether the scavenged register needs to be reserved /// \p ReserveAfter controls whether the scavenged register needs to be reserved
/// after the current instruction, otherwise it will only be reserved before the /// after the current instruction, otherwise it will only be reserved before the
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Linesbool RenameIndependentSubregs::renameComponents(LiveInterval &LI) const {
if (!findComponents(Classes, SubRangeInfos, LI)) if (!findComponents(Classes, SubRangeInfos, LI))
return false; return false;
// Create a new VReg for each class. // Create a new VReg for each class.
unsigned Reg = LI.reg; unsigned Reg = LI.reg;
const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
SmallVector<LiveInterval*, 4> Intervals; SmallVector<LiveInterval*, 4> Intervals;
Intervals.push_back(&LI); Intervals.push_back(&LI);
DEBUG(dbgs() << PrintReg(Reg) << ": Found " << Classes.getNumClasses() DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses()
<< " equivalence classes.\n"); << " equivalence classes.\n");
DEBUG(dbgs() << PrintReg(Reg) << ": Splitting into newly created:"); DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses; for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
++I) { ++I) {
unsigned NewVReg = MRI->createVirtualRegister(RegClass); unsigned NewVReg = MRI->createVirtualRegister(RegClass);
LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
Intervals.push_back(&NewLI); Intervals.push_back(&NewLI);
DEBUG(dbgs() << ' ' << PrintReg(NewVReg)); DEBUG(dbgs() << ' ' << printReg(NewVReg));
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
rewriteOperands(Classes, SubRangeInfos, Intervals); rewriteOperands(Classes, SubRangeInfos, Intervals);
distribute(Classes, SubRangeInfos, Intervals); distribute(Classes, SubRangeInfos, Intervals);
computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals); computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
return true; return true;
} }
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llvm/trunk/lib/CodeGen/ScheduleDAG.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Linesraw_ostream &SDep::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
case Output: OS << "Out "; break; case Output: OS << "Out "; break;
case Order: OS << "Ord "; break; case Order: OS << "Ord "; break;
} }
switch (getKind()) { switch (getKind()) {
case Data: case Data:
OS << " Latency=" << getLatency(); OS << " Latency=" << getLatency();
if (TRI && isAssignedRegDep()) if (TRI && isAssignedRegDep())
OS << " Reg=" << PrintReg(getReg(), TRI); OS << " Reg=" << printReg(getReg(), TRI);
break; break;
case Anti: case Anti:
case Output: case Output:
OS << " Latency=" << getLatency(); OS << " Latency=" << getLatency();
break; break;
case Order: case Order:
OS << " Latency=" << getLatency(); OS << " Latency=" << getLatency();
switch(Contents.OrdKind) { switch(Contents.OrdKind) {
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llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Show First 20 Lines • Show All 522 Lines • ▼ Show 20 Lines if (unsigned TF = TI->getTargetFlags())
OS << " [TF=" << TF << ']'; OS << " [TF=" << TF << ']';
} else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
OS << "<"; OS << "<";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
if (LBB) if (LBB)
OS << LBB->getName() << " "; OS << LBB->getName() << " ";
OS << (const void*)BBDN->getBasicBlock() << ">"; OS << (const void*)BBDN->getBasicBlock() << ">";
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
OS << ' ' << PrintReg(R->getReg(), OS << ' ' << printReg(R->getReg(),
G ? G->getSubtarget().getRegisterInfo() : nullptr); G ? G->getSubtarget().getRegisterInfo() : nullptr);
} else if (const ExternalSymbolSDNode *ES = } else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(this)) { dyn_cast<ExternalSymbolSDNode>(this)) {
OS << "'" << ES->getSymbol() << "'"; OS << "'" << ES->getSymbol() << "'";
if (unsigned int TF = ES->getTargetFlags()) if (unsigned int TF = ES->getTargetFlags())
OS << " [TF=" << TF << ']'; OS << " [TF=" << TF << ']';
} else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
if (M->getValue()) if (M->getValue())
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llvm/trunk/lib/CodeGen/SplitKit.cpp

Show First 20 Lines • Show All 1,134 Lines • ▼ Show 20 Lines do {
} }
} else { } else {
RegIdx = 0; RegIdx = 0;
End = std::min(End, AssignI.start()); End = std::min(End, AssignI.start());
} }
// The interval [Start;End) is continuously mapped to RegIdx, ParentVNI. // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx
<< '(' << PrintReg(Edit->get(RegIdx)) << ')'); << '(' << printReg(Edit->get(RegIdx)) << ')');
LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx)); LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
// Check for a simply defined value that can be blitted directly. // Check for a simply defined value that can be blitted directly.
ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id)); ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
if (VNInfo *VNI = VFP.getPointer()) { if (VNInfo *VNI = VFP.getPointer()) {
DEBUG(dbgs() << ':' << VNI->id); DEBUG(dbgs() << ':' << VNI->id);
LI.addSegment(LiveInterval::Segment(Start, End, VNI)); LI.addSegment(LiveInterval::Segment(Start, End, VNI));
Start = End; Start = End;
▲ Show 20 Lines • Show All 663 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Linesbool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
ArrayRef<MCPhysReg> Exceptions) const { ArrayRef<MCPhysReg> Exceptions) const {
// Check that all super registers of reserved regs are reserved as well. // Check that all super registers of reserved regs are reserved as well.
BitVector Checked(getNumRegs()); BitVector Checked(getNumRegs());
for (unsigned Reg : RegisterSet.set_bits()) { for (unsigned Reg : RegisterSet.set_bits()) {
if (Checked[Reg]) if (Checked[Reg])
continue; continue;
for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
dbgs() << "Error: Super register " << PrintReg(*SR, this) dbgs() << "Error: Super register " << printReg(*SR, this)
<< " of reserved register " << PrintReg(Reg, this) << " of reserved register " << printReg(Reg, this)
<< " is not reserved.\n"; << " is not reserved.\n";
return false; return false;
} }
// We transitively check superregs. So we can remember this for later // We transitively check superregs. So we can remember this for later
// to avoid compiletime explosion in deep register hierarchies. // to avoid compiletime explosion in deep register hierarchies.
Checked.set(*SR); Checked.set(*SR);
} }
} }
return true; return true;
} }
namespace llvm { namespace llvm {
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
unsigned SubIdx) { unsigned SubIdx) {
return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
if (!Reg) if (!Reg)
OS << "%noreg"; OS << "%noreg";
else if (TargetRegisterInfo::isStackSlot(Reg)) else if (TargetRegisterInfo::isStackSlot(Reg))
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg)) else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
else if (TRI && Reg < TRI->getNumRegs()) else if (TRI && Reg < TRI->getNumRegs())
OS << '%' << TRI->getName(Reg); OS << '%' << TRI->getName(Reg);
else else
OS << "%physreg" << Reg; OS << "%physreg" << Reg;
if (SubIdx) { if (SubIdx) {
if (TRI) if (TRI)
OS << ':' << TRI->getSubRegIndexName(SubIdx); OS << ':' << TRI->getSubRegIndexName(SubIdx);
else else
OS << ":sub(" << SubIdx << ')'; OS << ":sub(" << SubIdx << ')';
} }
}); });
} }
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) { return Printable([Unit, TRI](raw_ostream &OS) {
// Generic printout when TRI is missing. // Generic printout when TRI is missing.
if (!TRI) { if (!TRI) {
OS << "Unit~" << Unit; OS << "Unit~" << Unit;
return; return;
} }
// Check for invalid register units. // Check for invalid register units.
if (Unit >= TRI->getNumRegUnits()) { if (Unit >= TRI->getNumRegUnits()) {
OS << "BadUnit~" << Unit; OS << "BadUnit~" << Unit;
return; return;
} }
// Normal units have at least one root. // Normal units have at least one root.
MCRegUnitRootIterator Roots(Unit, TRI); MCRegUnitRootIterator Roots(Unit, TRI);
assert(Roots.isValid() && "Unit has no roots."); assert(Roots.isValid() && "Unit has no roots.");
OS << TRI->getName(*Roots); OS << TRI->getName(*Roots);
for (++Roots; Roots.isValid(); ++Roots) for (++Roots; Roots.isValid(); ++Roots)
OS << '~' << TRI->getName(*Roots); OS << '~' << TRI->getName(*Roots);
}); });
} }
Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) { return Printable([Unit, TRI](raw_ostream &OS) {
if (TRI && TRI->isVirtualRegister(Unit)) { if (TRI && TRI->isVirtualRegister(Unit)) {
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
} else { } else {
OS << PrintRegUnit(Unit, TRI); OS << printRegUnit(Unit, TRI);
} }
}); });
} }
} // end namespace llvm } // end namespace llvm
/// getAllocatableClass - Return the maximal subclass of the given register /// getAllocatableClass - Return the maximal subclass of the given register
/// class that is alloctable, or NULL. /// class that is alloctable, or NULL.
▲ Show 20 Lines • Show All 278 Lines • ▼ Show 20 Lines if ((mask0[I] & mask1[I]) != mask0[I])
return false; return false;
return true; return true;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD LLVM_DUMP_METHOD
void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
} }
#endif #endif

llvm/trunk/lib/CodeGen/VirtRegMap.cpp

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Linesvoid VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
Virt2StackSlotMap[virtReg] = SS; Virt2StackSlotMap[virtReg] = SS;
} }
void VirtRegMap::print(raw_ostream &OS, const Module*) const { void VirtRegMap::print(raw_ostream &OS, const Module*) const {
OS << "********** REGISTER MAP **********\n"; OS << "********** REGISTER MAP **********\n";
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i); unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) { if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
OS << '[' << PrintReg(Reg, TRI) << " -> " OS << '[' << printReg(Reg, TRI) << " -> "
<< PrintReg(Virt2PhysMap[Reg], TRI) << "] " << printReg(Virt2PhysMap[Reg], TRI) << "] "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
} }
} }
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i); unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
<< "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
} }
} }
OS << '\n'; OS << '\n';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void VirtRegMap::dump() const { LLVM_DUMP_METHOD void VirtRegMap::dump() const {
▲ Show 20 Lines • Show All 394 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

Show First 20 Lines • Show All 734 Lines • ▼ Show 20 Lines for (auto I = MBB->rbegin(); I != MBB->rend(); LR.stepBackward(*I), ++I) {
LoadInfo NewLdI(LdI); LoadInfo NewLdI(LdI);
NewLdI.BaseReg = ScratchReg; NewLdI.BaseReg = ScratchReg;
unsigned NewTag = *getTag(TRI, MI, NewLdI); unsigned NewTag = *getTag(TRI, MI, NewLdI);
// Scratch reg tag would collide too, so don't use it. // Scratch reg tag would collide too, so don't use it.
if (TagMap.count(NewTag)) if (TagMap.count(NewTag))
continue; continue;
DEBUG(dbgs() << "Changing base reg to: " << PrintReg(ScratchReg, TRI) DEBUG(dbgs() << "Changing base reg to: " << printReg(ScratchReg, TRI)
<< '\n'); << '\n');
// Rewrite: // Rewrite:
// Xd = LOAD Xb, off // Xd = LOAD Xb, off
// to: // to:
// Xc = MOV Xb // Xc = MOV Xb
// Xd = LOAD Xc, off // Xd = LOAD Xc, off
DebugLoc DL = MI.getDebugLoc(); DebugLoc DL = MI.getDebugLoc();
BuildMI(*MBB, &MI, DL, TII->get(AArch64::ORRXrs), ScratchReg) BuildMI(*MBB, &MI, DL, TII->get(AArch64::ORRXrs), ScratchReg)
.addReg(AArch64::XZR) .addReg(AArch64::XZR)
.addReg(LdI.BaseReg) .addReg(LdI.BaseReg)
.addImm(0); .addImm(0);
MachineOperand &BaseOpnd = MI.getOperand(LdI.BaseRegIdx); MachineOperand &BaseOpnd = MI.getOperand(LdI.BaseRegIdx);
BaseOpnd.setReg(ScratchReg); BaseOpnd.setReg(ScratchReg);
// If the load does a pre/post increment, then insert a MOV after as // If the load does a pre/post increment, then insert a MOV after as
// well to update the real base register. // well to update the real base register.
if (LdI.IsPrePost) { if (LdI.IsPrePost) {
DEBUG(dbgs() << "Doing post MOV of incremented reg: " DEBUG(dbgs() << "Doing post MOV of incremented reg: "
<< PrintReg(ScratchReg, TRI) << '\n'); << printReg(ScratchReg, TRI) << '\n');
MI.getOperand(0).setReg( MI.getOperand(0).setReg(
ScratchReg); // Change tied operand pre/post update dest. ScratchReg); // Change tied operand pre/post update dest.
BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL, BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL,
TII->get(AArch64::ORRXrs), LdI.BaseReg) TII->get(AArch64::ORRXrs), LdI.BaseReg)
.addReg(AArch64::XZR) .addReg(AArch64::XZR)
.addReg(ScratchReg) .addReg(ScratchReg)
.addImm(0); .addImm(0);
} }
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

Show First 20 Lines • Show All 1,202 Lines • ▼ Show 20 Lines if (produceCompactUnwindFrame(MF) && !SavedRegs.test(PairedReg)) {
if (AArch64::GPR64RegClass.contains(PairedReg) && if (AArch64::GPR64RegClass.contains(PairedReg) &&
!RegInfo->isReservedReg(MF, PairedReg)) !RegInfo->isReservedReg(MF, PairedReg))
ExtraCSSpill = PairedReg; ExtraCSSpill = PairedReg;
} }
} }
DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:"; DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";
for (unsigned Reg : SavedRegs.set_bits()) for (unsigned Reg : SavedRegs.set_bits())
dbgs() << ' ' << PrintReg(Reg, RegInfo); dbgs() << ' ' << printReg(Reg, RegInfo);
dbgs() << "\n";); dbgs() << "\n";);
// If any callee-saved registers are used, the frame cannot be eliminated. // If any callee-saved registers are used, the frame cannot be eliminated.
unsigned NumRegsSpilled = SavedRegs.count(); unsigned NumRegsSpilled = SavedRegs.count();
bool CanEliminateFrame = NumRegsSpilled == 0; bool CanEliminateFrame = NumRegsSpilled == 0;
// The CSR spill slots have not been allocated yet, so estimateStackSize // The CSR spill slots have not been allocated yet, so estimateStackSize
// won't include them. // won't include them.
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned CFSize = MFI.estimateStackSize(MF) + 8 * NumRegsSpilled; unsigned CFSize = MFI.estimateStackSize(MF) + 8 * NumRegsSpilled;
DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n"); DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n");
unsigned EstimatedStackSizeLimit = estimateRSStackSizeLimit(MF); unsigned EstimatedStackSizeLimit = estimateRSStackSizeLimit(MF);
bool BigStack = (CFSize > EstimatedStackSizeLimit); bool BigStack = (CFSize > EstimatedStackSizeLimit);
if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
AFI->setHasStackFrame(true); AFI->setHasStackFrame(true);
// Estimate if we might need to scavenge a register at some point in order // Estimate if we might need to scavenge a register at some point in order
// to materialize a stack offset. If so, either spill one additional // to materialize a stack offset. If so, either spill one additional
// callee-saved register or reserve a special spill slot to facilitate // callee-saved register or reserve a special spill slot to facilitate
// register scavenging. If we already spilled an extra callee-saved register // register scavenging. If we already spilled an extra callee-saved register
// above to keep the number of spills even, we don't need to do anything else // above to keep the number of spills even, we don't need to do anything else
// here. // here.
if (BigStack) { if (BigStack) {
if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
DEBUG(dbgs() << "Spilling " << PrintReg(UnspilledCSGPR, RegInfo) DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
<< " to get a scratch register.\n"); << " to get a scratch register.\n");
SavedRegs.set(UnspilledCSGPR); SavedRegs.set(UnspilledCSGPR);
// MachO's compact unwind format relies on all registers being stored in // MachO's compact unwind format relies on all registers being stored in
// pairs, so if we need to spill one extra for BigStack, then we need to // pairs, so if we need to spill one extra for BigStack, then we need to
// store the pair. // store the pair.
if (produceCompactUnwindFrame(MF)) if (produceCompactUnwindFrame(MF))
SavedRegs.set(UnspilledCSGPRPaired); SavedRegs.set(UnspilledCSGPRPaired);
ExtraCSSpill = UnspilledCSGPRPaired; ExtraCSSpill = UnspilledCSGPRPaired;
Show All 27 Lines

llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
unsigned Ra) { unsigned Ra) {
LiveIntervals &LIs = G.getMetadata().LIS; LiveIntervals &LIs = G.getMetadata().LIS;
// Do some Chain management // Do some Chain management
if (Chains.count(Ra)) { if (Chains.count(Ra)) {
if (Rd != Ra) { if (Rd != Ra) {
DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to " DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) << " to "
<< PrintReg(Rd, TRI) << '\n';); << printReg(Rd, TRI) << '\n';);
Chains.remove(Ra); Chains.remove(Ra);
Chains.insert(Rd); Chains.insert(Rd);
} }
} else { } else {
DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI) DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI)
<< '\n';); << '\n';);
Chains.insert(Rd); Chains.insert(Rd);
} }
PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
const LiveInterval &ld = LIs.getInterval(Rd); const LiveInterval &ld = LIs.getInterval(Rd);
for (auto r : Chains) { for (auto r : Chains) {
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines for (const auto &MBB: MF) {
Chains.clear(); // FIXME: really needed ? Could not work at MF level ? Chains.clear(); // FIXME: really needed ? Could not work at MF level ?
for (const auto &MI: MBB) { for (const auto &MI: MBB) {
// Forget Chains which have expired // Forget Chains which have expired
for (auto r : Chains) { for (auto r : Chains) {
SmallVector<unsigned, 8> toDel; SmallVector<unsigned, 8> toDel;
if(regJustKilledBefore(LIs, r, MI)) { if(regJustKilledBefore(LIs, r, MI)) {
DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at "; DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at ";
MI.print(dbgs());); MI.print(dbgs()););
toDel.push_back(r); toDel.push_back(r);
} }
while (!toDel.empty()) { while (!toDel.empty()) {
Chains.remove(toDel.back()); Chains.remove(toDel.back());
toDel.pop_back(); toDel.pop_back();
} }
Show All 32 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

Show All 21 Lines
void ArgDescriptor::print(raw_ostream &OS, void ArgDescriptor::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
if (!isSet()) { if (!isSet()) {
OS << "<not set>\n"; OS << "<not set>\n";
return; return;
} }
if (isRegister()) if (isRegister())
OS << "Reg " << PrintReg(getRegister(), TRI) << '\n'; OS << "Reg " << printReg(getRegister(), TRI) << '\n';
else else
OS << "Stack offset " << getStackOffset() << '\n'; OS << "Stack offset " << getStackOffset() << '\n';
} }
char AMDGPUArgumentUsageInfo::ID = 0; char AMDGPUArgumentUsageInfo::ID = 0;
const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{}; const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) { LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) {
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
dbgs() << "=PHIInfo Start=\n"; dbgs() << "=PHIInfo Start=\n";
for (auto PII : this->PHIInfo) { for (auto PII : this->PHIInfo) {
PHIInfoElementT &Element = *PII; PHIInfoElementT &Element = *PII;
dbgs() << "Dest: " << PrintReg(Element.DestReg, TRI) dbgs() << "Dest: " << printReg(Element.DestReg, TRI)
<< " Sources: {"; << " Sources: {";
for (auto &SI : Element.Sources) { for (auto &SI : Element.Sources) {
dbgs() << PrintReg(SI.first, TRI) << "(BB#" dbgs() << printReg(SI.first, TRI) << "(BB#"
<< SI.second->getNumber() << "),"; << SI.second->getNumber() << "),";
} }
dbgs() << "}\n"; dbgs() << "}\n";
} }
dbgs() << "=PHIInfo End=\n"; dbgs() << "=PHIInfo End=\n";
} }
#endif #endif
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Linespublic:
MBBMRT *getMBBMRT() override { return this; } MBBMRT *getMBBMRT() override { return this; }
MachineBasicBlock *getMBB() { return MBB; } MachineBasicBlock *getMBB() { return MBB; }
void dump(const TargetRegisterInfo *TRI, int depth = 0) override { void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
dumpDepth(depth); dumpDepth(depth);
dbgs() << "MBB: " << getMBB()->getNumber(); dbgs() << "MBB: " << getMBB()->getNumber();
dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI); dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n"; dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
} }
}; };
class RegionMRT : public MRT { class RegionMRT : public MRT {
protected: protected:
MachineRegion *Region; MachineRegion *Region;
LinearizedRegion *LRegion = nullptr; LinearizedRegion *LRegion = nullptr;
MachineBasicBlock *Succ = nullptr; MachineBasicBlock *Succ = nullptr;
Show All 32 Linespublic:
void addChild(MRT *Tree) { Children.insert(Tree); } void addChild(MRT *Tree) { Children.insert(Tree); }
SetVector<MRT *> *getChildren() { return &Children; } SetVector<MRT *> *getChildren() { return &Children; }
void dump(const TargetRegisterInfo *TRI, int depth = 0) override { void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
dumpDepth(depth); dumpDepth(depth);
dbgs() << "Region: " << (void *)Region; dbgs() << "Region: " << (void *)Region;
dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI); dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n"; dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
dumpDepth(depth); dumpDepth(depth);
if (getSucc()) if (getSucc())
dbgs() << "Succ: " << getSucc()->getNumber() << "\n"; dbgs() << "Succ: " << getSucc()->getNumber() << "\n";
else else
dbgs() << "Succ: none \n"; dbgs() << "Succ: none \n";
for (auto MRTI : Children) { for (auto MRTI : Children) {
MRTI->dump(TRI, depth + 1); MRTI->dump(TRI, depth + 1);
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
} }
void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg,
MachineInstr *DefInstr, MachineInstr *DefInstr,
const MachineRegisterInfo *MRI, const MachineRegisterInfo *MRI,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
PHILinearize &PHIInfo) { PHILinearize &PHIInfo) {
if (TRI->isVirtualRegister(Reg)) { if (TRI->isVirtualRegister(Reg)) {
DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n"); DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n");
// If this is a source register to a PHI we are chaining, it // If this is a source register to a PHI we are chaining, it
// must be live out. // must be live out.
if (PHIInfo.isSource(Reg)) { if (PHIInfo.isSource(Reg)) {
DEBUG(dbgs() << "Add LiveOut (PHI): " << PrintReg(Reg, TRI) << "\n"); DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg); addLiveOut(Reg);
} else { } else {
// If this is live out of the MBB // If this is live out of the MBB
for (auto &UI : MRI->use_operands(Reg)) { for (auto &UI : MRI->use_operands(Reg)) {
if (UI.getParent()->getParent() != MBB) { if (UI.getParent()->getParent() != MBB) {
DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber() DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber()
<< "): " << PrintReg(Reg, TRI) << "\n"); << "): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg); addLiveOut(Reg);
} else { } else {
// If the use is in the same MBB we have to make sure // If the use is in the same MBB we have to make sure
// it is after the def, otherwise it is live out in a loop // it is after the def, otherwise it is live out in a loop
MachineInstr *UseInstr = UI.getParent(); MachineInstr *UseInstr = UI.getParent();
for (MachineBasicBlock::instr_iterator for (MachineBasicBlock::instr_iterator
MII = UseInstr->getIterator(), MII = UseInstr->getIterator(),
MIE = UseInstr->getParent()->instr_end(); MIE = UseInstr->getParent()->instr_end();
MII != MIE; ++MII) { MII != MIE; ++MII) {
if ((&(*MII)) == DefInstr) { if ((&(*MII)) == DefInstr) {
DEBUG(dbgs() << "Add LiveOut (Loop): " << PrintReg(Reg, TRI) DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI)
<< "\n"); << "\n");
addLiveOut(Reg); addLiveOut(Reg);
} }
} }
} }
} }
} }
} }
} }
void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg, void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg,
MachineInstr *DefInstr, MachineInstr *DefInstr,
const MachineRegisterInfo *MRI, const MachineRegisterInfo *MRI,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
PHILinearize &PHIInfo) { PHILinearize &PHIInfo) {
if (TRI->isVirtualRegister(Reg)) { if (TRI->isVirtualRegister(Reg)) {
DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n"); DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n");
for (auto &UI : MRI->use_operands(Reg)) { for (auto &UI : MRI->use_operands(Reg)) {
if (!Region->contains(UI.getParent()->getParent())) { if (!Region->contains(UI.getParent()->getParent())) {
DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region
<< "): " << PrintReg(Reg, TRI) << "\n"); << "): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg); addLiveOut(Reg);
} }
} }
} }
} }
void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB,
const MachineRegisterInfo *MRI, const MachineRegisterInfo *MRI,
Show All 20 Lines for (auto &II : *(*SI)) {
if (II.isPHI()) { if (II.isPHI()) {
MachineInstr &PHI = II; MachineInstr &PHI = II;
int numPreds = getPHINumInputs(PHI); int numPreds = getPHINumInputs(PHI);
for (int i = 0; i < numPreds; ++i) { for (int i = 0; i < numPreds; ++i) {
if (getPHIPred(PHI, i) == MBB) { if (getPHIPred(PHI, i) == MBB) {
unsigned PHIReg = getPHISourceReg(PHI, i); unsigned PHIReg = getPHISourceReg(PHI, i);
DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber() DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber()
<< " -> BB#" << (*SI)->getNumber() << " -> BB#" << (*SI)->getNumber()
<< "): " << PrintReg(PHIReg, TRI) << "\n"); << "): " << printReg(PHIReg, TRI) << "\n");
addLiveOut(PHIReg); addLiveOut(PHIReg);
} }
} }
} }
} }
} }
DEBUG(dbgs() << "-Store Live Outs Endn-\n"); DEBUG(dbgs() << "-Store Live Outs Endn-\n");
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines if (CurrentTopRegion == nullptr) {
for (auto &II : *Succ) { for (auto &II : *Succ) {
if (II.isPHI()) { if (II.isPHI()) {
MachineInstr &PHI = II; MachineInstr &PHI = II;
int numPreds = getPHINumInputs(PHI); int numPreds = getPHINumInputs(PHI);
for (int i = 0; i < numPreds; ++i) { for (int i = 0; i < numPreds; ++i) {
if (Region->contains(getPHIPred(PHI, i))) { if (Region->contains(getPHIPred(PHI, i))) {
unsigned PHIReg = getPHISourceReg(PHI, i); unsigned PHIReg = getPHISourceReg(PHI, i);
DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region
<< "): " << PrintReg(PHIReg, TRI) << "\n"); << "): " << printReg(PHIReg, TRI) << "\n");
addLiveOut(PHIReg); addLiveOut(PHIReg);
} }
} }
} }
} }
} }
} }
#ifndef NDEBUG #ifndef NDEBUG
void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) { void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
OS << "Linearized Region {"; OS << "Linearized Region {";
bool IsFirst = true; bool IsFirst = true;
for (const auto &MBB : MBBs) { for (const auto &MBB : MBBs) {
if (IsFirst) { if (IsFirst) {
IsFirst = false; IsFirst = false;
} else { } else {
OS << " ,"; OS << " ,";
} }
OS << MBB->getNumber(); OS << MBB->getNumber();
} }
OS << "} (" << Entry->getNumber() << ", " OS << "} (" << Entry->getNumber() << ", "
<< (Exit == nullptr ? -1 : Exit->getNumber()) << (Exit == nullptr ? -1 : Exit->getNumber())
<< "): In:" << PrintReg(getBBSelectRegIn(), TRI) << "): In:" << printReg(getBBSelectRegIn(), TRI)
<< " Out:" << PrintReg(getBBSelectRegOut(), TRI) << " {"; << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {";
for (auto &LI : LiveOuts) { for (auto &LI : LiveOuts) {
OS << PrintReg(LI, TRI) << " "; OS << printReg(LI, TRI) << " ";
} }
OS << "} \n"; OS << "} \n";
} }
#endif #endif
unsigned LinearizedRegion::getBBSelectRegIn() { unsigned LinearizedRegion::getBBSelectRegIn() {
return getRegionMRT()->getBBSelectRegIn(); return getRegionMRT()->getBBSelectRegIn();
} }
Show All 22 Lines
void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister,
MachineRegisterInfo *MRI, MachineRegisterInfo *MRI,
bool ReplaceInside, bool ReplaceOutside, bool ReplaceInside, bool ReplaceOutside,
bool IncludeLoopPHI) { bool IncludeLoopPHI) {
assert(Register != NewRegister && "Cannot replace a reg with itself"); assert(Register != NewRegister && "Cannot replace a reg with itself");
DEBUG(dbgs() << "Pepareing to replace register (region): " DEBUG(dbgs() << "Pepareing to replace register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo()) << " with " << printReg(Register, MRI->getTargetRegisterInfo()) << " with "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
// If we are replacing outside, we also need to update the LiveOuts // If we are replacing outside, we also need to update the LiveOuts
if (ReplaceOutside && if (ReplaceOutside &&
(isLiveOut(Register) || this->getParent()->isLiveOut(Register))) { (isLiveOut(Register) || this->getParent()->isLiveOut(Register))) {
LinearizedRegion *Current = this; LinearizedRegion *Current = this;
while (Current != nullptr && Current->getEntry() != nullptr) { while (Current != nullptr && Current->getEntry() != nullptr) {
DEBUG(dbgs() << "Region before register replace\n"); DEBUG(dbgs() << "Region before register replace\n");
DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo())); DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo()));
Show All 19 Lines bool IsLoopPHI = IsInside && (O.getParent()->isPHI() &&
O.getParent()->getParent() == getEntry()); O.getParent()->getParent() == getEntry());
bool ShouldReplace = (IsInside && ReplaceInside) || bool ShouldReplace = (IsInside && ReplaceInside) ||
(!IsInside && ReplaceOutside) || (!IsInside && ReplaceOutside) ||
(IncludeLoopPHI && IsLoopPHI); (IncludeLoopPHI && IsLoopPHI);
if (ShouldReplace) { if (ShouldReplace) {
if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) {
DEBUG(dbgs() << "Trying to substitute physical register: " DEBUG(dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n"); << "\n");
llvm_unreachable("Cannot substitute physical registers"); llvm_unreachable("Cannot substitute physical registers");
} else { } else {
DEBUG(dbgs() << "Replacing register (region): " DEBUG(dbgs() << "Replacing register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo()) << printReg(Register, MRI->getTargetRegisterInfo())
<< " with " << " with "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n"); << "\n");
O.setReg(NewRegister); O.setReg(NewRegister);
} }
} }
} }
} }
void LinearizedRegion::replaceRegisterInsideRegion(unsigned Register, void LinearizedRegion::replaceRegisterInsideRegion(unsigned Register,
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines for (auto &II : *MBB) {
for (auto &RI : II.uses()) { for (auto &RI : II.uses()) {
if (RI.isReg()) { if (RI.isReg()) {
unsigned Reg = RI.getReg(); unsigned Reg = RI.getReg();
if (TRI->isVirtualRegister(Reg)) { if (TRI->isVirtualRegister(Reg)) {
if (hasNoDef(Reg, MRI)) if (hasNoDef(Reg, MRI))
continue; continue;
if (!MRI->hasOneDef(Reg)) { if (!MRI->hasOneDef(Reg)) {
DEBUG(this->getEntry()->getParent()->dump()); DEBUG(this->getEntry()->getParent()->dump());
DEBUG(dbgs() << PrintReg(Reg, TRI) << "\n"); DEBUG(dbgs() << printReg(Reg, TRI) << "\n");
} }
if (MRI->def_begin(Reg) == MRI->def_end()) { if (MRI->def_begin(Reg) == MRI->def_end()) {
DEBUG(dbgs() << "Register " DEBUG(dbgs() << "Register "
<< PrintReg(Reg, MRI->getTargetRegisterInfo()) << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has NO defs\n"); << " has NO defs\n");
} else if (!MRI->hasOneDef(Reg)) { } else if (!MRI->hasOneDef(Reg)) {
DEBUG(dbgs() << "Register " DEBUG(dbgs() << "Register "
<< PrintReg(Reg, MRI->getTargetRegisterInfo()) << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has multiple defs\n"); << " has multiple defs\n");
} }
assert(MRI->hasOneDef(Reg) && "Register has multiple definitions"); assert(MRI->hasOneDef(Reg) && "Register has multiple definitions");
MachineOperand *Def = &(*(MRI->def_begin(Reg))); MachineOperand *Def = &(*(MRI->def_begin(Reg)));
MachineOperand *UseOperand = &(RI); MachineOperand *UseOperand = &(RI);
bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB; bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
if (UseIsOutsideDefMBB && UseOperand->isKill()) { if (UseIsOutsideDefMBB && UseOperand->isKill()) {
DEBUG(dbgs() << "Removing kill flag on register: " DEBUG(dbgs() << "Removing kill flag on register: "
<< PrintReg(Reg, TRI) << "\n"); << printReg(Reg, TRI) << "\n");
UseOperand->setIsKill(false); UseOperand->setIsKill(false);
} }
} }
} }
} }
} }
} }
} }
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines
bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
unsigned CombinedSourceReg, unsigned CombinedSourceReg,
MachineBasicBlock *SourceMBB, MachineBasicBlock *SourceMBB,
SmallVector<unsigned, 2> &PHIIndices, SmallVector<unsigned, 2> &PHIIndices,
unsigned *ReplaceReg) { unsigned *ReplaceReg) {
DEBUG(dbgs() << "Shrink PHI: "); DEBUG(dbgs() << "Shrink PHI: ");
DEBUG(PHI.dump()); DEBUG(PHI.dump());
DEBUG(dbgs() << " to " << PrintReg(getPHIDestReg(PHI), TRI) DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI)
<< "<def> = PHI("); << "<def> = PHI(");
bool Replaced = false; bool Replaced = false;
unsigned NumInputs = getPHINumInputs(PHI); unsigned NumInputs = getPHINumInputs(PHI);
int SingleExternalEntryIndex = -1; int SingleExternalEntryIndex = -1;
for (unsigned i = 0; i < NumInputs; ++i) { for (unsigned i = 0; i < NumInputs; ++i) {
if (!isPHIRegionIndex(PHIIndices, i)) { if (!isPHIRegionIndex(PHIIndices, i)) {
if (SingleExternalEntryIndex == -1) { if (SingleExternalEntryIndex == -1) {
Show All 14 Linesbool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
} else { } else {
MachineBasicBlock *MBB = PHI.getParent(); MachineBasicBlock *MBB = PHI.getParent();
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
getPHIDestReg(PHI)); getPHIDestReg(PHI));
if (SourceMBB) { if (SourceMBB) {
MIB.addReg(CombinedSourceReg); MIB.addReg(CombinedSourceReg);
MIB.addMBB(SourceMBB); MIB.addMBB(SourceMBB);
DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< SourceMBB->getNumber()); << SourceMBB->getNumber());
} }
for (unsigned i = 0; i < NumInputs; ++i) { for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIIndices, i)) { if (isPHIRegionIndex(PHIIndices, i)) {
continue; continue;
} }
unsigned SourceReg = getPHISourceReg(PHI, i); unsigned SourceReg = getPHISourceReg(PHI, i);
MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg); MIB.addReg(SourceReg);
MIB.addMBB(SourcePred); MIB.addMBB(SourcePred);
DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber()); << SourcePred->getNumber());
} }
DEBUG(dbgs() << ")\n"); DEBUG(dbgs() << ")\n");
} }
PHI.eraseFromParent(); PHI.eraseFromParent();
return Replaced; return Replaced;
} }
void AMDGPUMachineCFGStructurizer::replacePHI( void AMDGPUMachineCFGStructurizer::replacePHI(
MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *LastMerge, MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *LastMerge,
SmallVector<unsigned, 2> &PHIRegionIndices) { SmallVector<unsigned, 2> &PHIRegionIndices) {
DEBUG(dbgs() << "Replace PHI: "); DEBUG(dbgs() << "Replace PHI: ");
DEBUG(PHI.dump()); DEBUG(PHI.dump());
DEBUG(dbgs() << " with " << PrintReg(getPHIDestReg(PHI), TRI) DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI)
<< "<def> = PHI("); << "<def> = PHI(");
bool HasExternalEdge = false; bool HasExternalEdge = false;
unsigned NumInputs = getPHINumInputs(PHI); unsigned NumInputs = getPHINumInputs(PHI);
for (unsigned i = 0; i < NumInputs; ++i) { for (unsigned i = 0; i < NumInputs; ++i) {
if (!isPHIRegionIndex(PHIRegionIndices, i)) { if (!isPHIRegionIndex(PHIRegionIndices, i)) {
HasExternalEdge = true; HasExternalEdge = true;
} }
} }
if (HasExternalEdge) { if (HasExternalEdge) {
MachineBasicBlock *MBB = PHI.getParent(); MachineBasicBlock *MBB = PHI.getParent();
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
getPHIDestReg(PHI)); getPHIDestReg(PHI));
MIB.addReg(CombinedSourceReg); MIB.addReg(CombinedSourceReg);
MIB.addMBB(LastMerge); MIB.addMBB(LastMerge);
DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< LastMerge->getNumber()); << LastMerge->getNumber());
for (unsigned i = 0; i < NumInputs; ++i) { for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIRegionIndices, i)) { if (isPHIRegionIndex(PHIRegionIndices, i)) {
continue; continue;
} }
unsigned SourceReg = getPHISourceReg(PHI, i); unsigned SourceReg = getPHISourceReg(PHI, i);
MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg); MIB.addReg(SourceReg);
MIB.addMBB(SourcePred); MIB.addMBB(SourcePred);
DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber()); << SourcePred->getNumber());
} }
DEBUG(dbgs() << ")\n"); DEBUG(dbgs() << ")\n");
} else { } else {
replaceRegisterWith(getPHIDestReg(PHI), CombinedSourceReg); replaceRegisterWith(getPHIDestReg(PHI), CombinedSourceReg);
} }
PHI.eraseFromParent(); PHI.eraseFromParent();
} }
Show All 11 Lines for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIRegionIndices, i)) { if (isPHIRegionIndex(PHIRegionIndices, i)) {
NumNonRegionInputs--; NumNonRegionInputs--;
} }
} }
if (NumNonRegionInputs == 0) { if (NumNonRegionInputs == 0) {
auto DestReg = getPHIDestReg(PHI); auto DestReg = getPHIDestReg(PHI);
replaceRegisterWith(DestReg, CombinedSourceReg); replaceRegisterWith(DestReg, CombinedSourceReg);
DEBUG(dbgs() << " register " << PrintReg(CombinedSourceReg, TRI) << "\n"); DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI) << "\n");
PHI.eraseFromParent(); PHI.eraseFromParent();
} else { } else {
DEBUG(dbgs() << PrintReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("); DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << "<def> = PHI(");
MachineBasicBlock *MBB = PHI.getParent(); MachineBasicBlock *MBB = PHI.getParent();
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
getPHIDestReg(PHI)); getPHIDestReg(PHI));
MIB.addReg(CombinedSourceReg); MIB.addReg(CombinedSourceReg);
MIB.addMBB(IfMBB); MIB.addMBB(IfMBB);
DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< IfMBB->getNumber()); << IfMBB->getNumber());
unsigned NumInputs = getPHINumInputs(PHI); unsigned NumInputs = getPHINumInputs(PHI);
for (unsigned i = 0; i < NumInputs; ++i) { for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIRegionIndices, i)) { if (isPHIRegionIndex(PHIRegionIndices, i)) {
continue; continue;
} }
unsigned SourceReg = getPHISourceReg(PHI, i); unsigned SourceReg = getPHISourceReg(PHI, i);
MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg); MIB.addReg(SourceReg);
MIB.addMBB(SourcePred); MIB.addMBB(SourcePred);
DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber()); << SourcePred->getNumber());
} }
DEBUG(dbgs() << ")\n"); DEBUG(dbgs() << ")\n");
PHI.eraseFromParent(); PHI.eraseFromParent();
} }
} }
void AMDGPUMachineCFGStructurizer::replaceLiveOutRegs( void AMDGPUMachineCFGStructurizer::replaceLiveOutRegs(
MachineInstr &PHI, SmallVector<unsigned, 2> &PHIRegionIndices, MachineInstr &PHI, SmallVector<unsigned, 2> &PHIRegionIndices,
unsigned CombinedSourceReg, LinearizedRegion *LRegion) { unsigned CombinedSourceReg, LinearizedRegion *LRegion) {
bool WasLiveOut = false; bool WasLiveOut = false;
for (auto PII : PHIRegionIndices) { for (auto PII : PHIRegionIndices) {
unsigned Reg = getPHISourceReg(PHI, PII); unsigned Reg = getPHISourceReg(PHI, PII);
if (LRegion->isLiveOut(Reg)) { if (LRegion->isLiveOut(Reg)) {
bool IsDead = true; bool IsDead = true;
// Check if register is live out of the basic block // Check if register is live out of the basic block
MachineBasicBlock *DefMBB = getDefInstr(Reg)->getParent(); MachineBasicBlock *DefMBB = getDefInstr(Reg)->getParent();
for (auto UI = MRI->use_begin(Reg), E = MRI->use_end(); UI != E; ++UI) { for (auto UI = MRI->use_begin(Reg), E = MRI->use_end(); UI != E; ++UI) {
if ((*UI).getParent()->getParent() != DefMBB) { if ((*UI).getParent()->getParent() != DefMBB) {
IsDead = false; IsDead = false;
} }
} }
DEBUG(dbgs() << "Register " << PrintReg(Reg, TRI) << " is " DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is "
<< (IsDead ? "dead" : "alive") << " after PHI replace\n"); << (IsDead ? "dead" : "alive") << " after PHI replace\n");
if (IsDead) { if (IsDead) {
LRegion->removeLiveOut(Reg); LRegion->removeLiveOut(Reg);
} }
WasLiveOut = true; WasLiveOut = true;
} }
} }
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Linesvoid AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB,
unsigned IfSourceRegister, unsigned IfSourceRegister,
unsigned CodeSourceRegister, unsigned CodeSourceRegister,
bool IsUndefIfSource) { bool IsUndefIfSource) {
// If this is the function exit block, we don't need a phi. // If this is the function exit block, we don't need a phi.
if (MergeBB->succ_begin() == MergeBB->succ_end()) { if (MergeBB->succ_begin() == MergeBB->succ_end()) {
return; return;
} }
DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber() DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber()
<< "): " << PrintReg(DestRegister, TRI) << "<def> = PHI(" << "): " << printReg(DestRegister, TRI) << "<def> = PHI("
<< PrintReg(IfSourceRegister, TRI) << ", BB#" << printReg(IfSourceRegister, TRI) << ", BB#"
<< IfBB->getNumber() << PrintReg(CodeSourceRegister, TRI) << IfBB->getNumber() << printReg(CodeSourceRegister, TRI)
<< ", BB#" << CodeBB->getNumber() << ")\n"); << ", BB#" << CodeBB->getNumber() << ")\n");
const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin()); const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin());
MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL, MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL,
TII->get(TargetOpcode::PHI), DestRegister); TII->get(TargetOpcode::PHI), DestRegister);
if (IsUndefIfSource && false) { if (IsUndefIfSource && false) {
MIB.addReg(IfSourceRegister, RegState::Undef); MIB.addReg(IfSourceRegister, RegState::Undef);
} else { } else {
MIB.addReg(IfSourceRegister); MIB.addReg(IfSourceRegister);
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines TII->insertVectorSelect(*CodeBB, CodeBB->getFirstTerminator(), DL,
BBSelectReg, Cond, TrueBBReg, FalseBBReg); BBSelectReg, Cond, TrueBBReg, FalseBBReg);
} }
insertUnconditionalBranch(CodeBB, MergeBB, DL); insertUnconditionalBranch(CodeBB, MergeBB, DL);
} }
MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) { MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) {
if (MRI->def_begin(Reg) == MRI->def_end()) { if (MRI->def_begin(Reg) == MRI->def_end()) {
DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo()) DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has NO defs\n"); << " has NO defs\n");
} else if (!MRI->hasOneDef(Reg)) { } else if (!MRI->hasOneDef(Reg)) {
DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo()) DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has multiple defs\n"); << " has multiple defs\n");
DEBUG(dbgs() << "DEFS BEGIN:\n"); DEBUG(dbgs() << "DEFS BEGIN:\n");
for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) { for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) {
DEBUG(DI->getParent()->dump()); DEBUG(DI->getParent()->dump());
} }
DEBUG(dbgs() << "DEFS END\n"); DEBUG(dbgs() << "DEFS END\n");
} }
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesvoid AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB,
DenseSet<unsigned> *LiveOuts = InnerRegion->getLiveOuts(); DenseSet<unsigned> *LiveOuts = InnerRegion->getLiveOuts();
SmallVector<unsigned, 4> OldLiveOuts; SmallVector<unsigned, 4> OldLiveOuts;
bool IsSingleBB = InnerRegion->getEntry() == InnerRegion->getExit(); bool IsSingleBB = InnerRegion->getEntry() == InnerRegion->getExit();
for (auto OLI : *LiveOuts) { for (auto OLI : *LiveOuts) {
OldLiveOuts.push_back(OLI); OldLiveOuts.push_back(OLI);
} }
for (auto LI : OldLiveOuts) { for (auto LI : OldLiveOuts) {
DEBUG(dbgs() << "LiveOut: " << PrintReg(LI, TRI)); DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI));
if (!containsDef(CodeBB, InnerRegion, LI) || if (!containsDef(CodeBB, InnerRegion, LI) ||
(!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) { (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) {
// If the register simly lives through the CodeBB, we don't have // If the register simly lives through the CodeBB, we don't have
// to rewrite anything since the register is not defined in this // to rewrite anything since the register is not defined in this
// part of the code. // part of the code.
DEBUG(dbgs() << "- through"); DEBUG(dbgs() << "- through");
continue; continue;
} }
Show All 9 Lines if (/*!PHIInfo.isSource(Reg) &&*/ Reg != InnerRegion->getBBSelectRegOut()) {
// and replace all uses outside of the region with the new dest // and replace all uses outside of the region with the new dest
// register, unless it is the outgoing BB select register. We have // register, unless it is the outgoing BB select register. We have
// already creaed phi nodes for these. // already creaed phi nodes for these.
const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
unsigned PHIDestReg = MRI->createVirtualRegister(RegClass); unsigned PHIDestReg = MRI->createVirtualRegister(RegClass);
unsigned IfSourceReg = MRI->createVirtualRegister(RegClass); unsigned IfSourceReg = MRI->createVirtualRegister(RegClass);
// Create initializer, this value is never used, but is needed // Create initializer, this value is never used, but is needed
// to satisfy SSA. // to satisfy SSA.
DEBUG(dbgs() << "Initializer for reg: " << PrintReg(Reg) << "\n"); DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n");
TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(), TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(),
IfSourceReg, 0); IfSourceReg, 0);
InnerRegion->replaceRegisterOutsideRegion(Reg, PHIDestReg, true, MRI); InnerRegion->replaceRegisterOutsideRegion(Reg, PHIDestReg, true, MRI);
DEBUG(dbgs() << "Insert Non-Chained Live out PHI\n"); DEBUG(dbgs() << "Insert Non-Chained Live out PHI\n");
insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, PHIDestReg, insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, PHIDestReg,
IfSourceReg, Reg, true); IfSourceReg, Reg, true);
} }
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Linesvoid AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegion,
if (NumSources == 1) { if (NumSources == 1) {
auto SRI = PHIInfo.sources_begin(DestReg); auto SRI = PHIInfo.sources_begin(DestReg);
unsigned SourceReg = (*SRI).first; unsigned SourceReg = (*SRI).first;
replaceRegisterWith(DestReg, SourceReg); replaceRegisterWith(DestReg, SourceReg);
} else { } else {
const DebugLoc &DL = Entry->findDebugLoc(Entry->begin()); const DebugLoc &DL = Entry->findDebugLoc(Entry->begin());
MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL, MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL,
TII->get(TargetOpcode::PHI), DestReg); TII->get(TargetOpcode::PHI), DestReg);
DEBUG(dbgs() << "Entry PHI " << PrintReg(DestReg, TRI) << "<def> = PHI("); DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << "<def> = PHI(");
unsigned CurrentBackedgeReg = 0; unsigned CurrentBackedgeReg = 0;
for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
unsigned SourceReg = (*SRI).first; unsigned SourceReg = (*SRI).first;
if (CurrentRegion->contains((*SRI).second)) { if (CurrentRegion->contains((*SRI).second)) {
if (CurrentBackedgeReg == 0) { if (CurrentBackedgeReg == 0) {
CurrentBackedgeReg = SourceReg; CurrentBackedgeReg = SourceReg;
} else { } else {
MachineInstr *PHIDefInstr = getDefInstr(SourceReg); MachineInstr *PHIDefInstr = getDefInstr(SourceReg);
MachineBasicBlock *PHIDefMBB = PHIDefInstr->getParent(); MachineBasicBlock *PHIDefMBB = PHIDefInstr->getParent();
const TargetRegisterClass *RegClass = const TargetRegisterClass *RegClass =
MRI->getRegClass(CurrentBackedgeReg); MRI->getRegClass(CurrentBackedgeReg);
unsigned NewBackedgeReg = MRI->createVirtualRegister(RegClass); unsigned NewBackedgeReg = MRI->createVirtualRegister(RegClass);
MachineInstrBuilder BackedgePHI = MachineInstrBuilder BackedgePHI =
BuildMI(*PHIDefMBB, PHIDefMBB->instr_begin(), DL, BuildMI(*PHIDefMBB, PHIDefMBB->instr_begin(), DL,
TII->get(TargetOpcode::PHI), NewBackedgeReg); TII->get(TargetOpcode::PHI), NewBackedgeReg);
BackedgePHI.addReg(CurrentBackedgeReg); BackedgePHI.addReg(CurrentBackedgeReg);
BackedgePHI.addMBB(getPHIPred(*PHIDefInstr, 0)); BackedgePHI.addMBB(getPHIPred(*PHIDefInstr, 0));
BackedgePHI.addReg(getPHISourceReg(*PHIDefInstr, 1)); BackedgePHI.addReg(getPHISourceReg(*PHIDefInstr, 1));
BackedgePHI.addMBB((*SRI).second); BackedgePHI.addMBB((*SRI).second);
CurrentBackedgeReg = NewBackedgeReg; CurrentBackedgeReg = NewBackedgeReg;
DEBUG(dbgs() << "Inserting backedge PHI: " DEBUG(dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI(" << printReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" << printReg(CurrentBackedgeReg, TRI) << ", BB#"
<< getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " << getPHIPred(*PHIDefInstr, 0)->getNumber() << ", "
<< PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI)
<< ", BB#" << (*SRI).second->getNumber()); << ", BB#" << (*SRI).second->getNumber());
} }
} else { } else {
MIB.addReg(SourceReg); MIB.addReg(SourceReg);
MIB.addMBB((*SRI).second); MIB.addMBB((*SRI).second);
DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< (*SRI).second->getNumber() << ", "); << (*SRI).second->getNumber() << ", ");
} }
} }
// Add the final backedge register source to the entry phi // Add the final backedge register source to the entry phi
if (CurrentBackedgeReg != 0) { if (CurrentBackedgeReg != 0) {
MIB.addReg(CurrentBackedgeReg); MIB.addReg(CurrentBackedgeReg);
MIB.addMBB(Exit); MIB.addMBB(Exit);
DEBUG(dbgs() << PrintReg(CurrentBackedgeReg, TRI) << ", BB#" DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", BB#"
<< Exit->getNumber() << ")\n"); << Exit->getNumber() << ")\n");
} else { } else {
DEBUG(dbgs() << ")\n"); DEBUG(dbgs() << ")\n");
} }
} }
} }
void AMDGPUMachineCFGStructurizer::createEntryPHIs(LinearizedRegion *CurrentRegion) { void AMDGPUMachineCFGStructurizer::createEntryPHIs(LinearizedRegion *CurrentRegion) {
Show All 14 Linesvoid AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register,
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register), for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
E = MRI->reg_end(); E = MRI->reg_end();
I != E;) { I != E;) {
MachineOperand &O = *I; MachineOperand &O = *I;
++I; ++I;
if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) {
DEBUG(dbgs() << "Trying to substitute physical register: " DEBUG(dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n"); << "\n");
llvm_unreachable("Cannot substitute physical registers"); llvm_unreachable("Cannot substitute physical registers");
// We don't handle physical registers, but if we need to // We don't handle physical registers, but if we need to
// in the future This is how we do it: // in the future This is how we do it:
// O.substPhysReg(NewRegister, *TRI); // O.substPhysReg(NewRegister, *TRI);
} else { } else {
DEBUG(dbgs() << "Replacing register: " DEBUG(dbgs() << "Replacing register: "
<< PrintReg(Register, MRI->getTargetRegisterInfo()) << printReg(Register, MRI->getTargetRegisterInfo())
<< " with " << " with "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n"); << "\n");
O.setReg(NewRegister); O.setReg(NewRegister);
} }
} }
PHIInfo.deleteDef(Register); PHIInfo.deleteDef(Register);
getRegionMRT()->replaceLiveOutReg(Register, NewRegister); getRegionMRT()->replaceLiveOutReg(Register, NewRegister);
DEBUG(PHIInfo.dump(MRI)); DEBUG(PHIInfo.dump(MRI));
} }
void AMDGPUMachineCFGStructurizer::resolvePHIInfos(MachineBasicBlock *FunctionEntry) { void AMDGPUMachineCFGStructurizer::resolvePHIInfos(MachineBasicBlock *FunctionEntry) {
DEBUG(dbgs() << "Resolve PHI Infos\n"); DEBUG(dbgs() << "Resolve PHI Infos\n");
DEBUG(PHIInfo.dump(MRI)); DEBUG(PHIInfo.dump(MRI));
for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE; for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
++DRI) { ++DRI) {
unsigned DestReg = *DRI; unsigned DestReg = *DRI;
DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) << "\n"); DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n");
auto SRI = PHIInfo.sources_begin(DestReg); auto SRI = PHIInfo.sources_begin(DestReg);
unsigned SourceReg = (*SRI).first; unsigned SourceReg = (*SRI).first;
DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI)
<< " SourceReg: " << PrintReg(SourceReg, TRI) << "\n"); << " SourceReg: " << printReg(SourceReg, TRI) << "\n");
assert(PHIInfo.sources_end(DestReg) == ++SRI && assert(PHIInfo.sources_end(DestReg) == ++SRI &&
"More than one phi source in entry node"); "More than one phi source in entry node");
replaceRegisterWith(DestReg, SourceReg); replaceRegisterWith(DestReg, SourceReg);
} }
} }
static bool isFunctionEntryBlock(MachineBasicBlock *MBB) { static bool isFunctionEntryBlock(MachineBasicBlock *MBB) {
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Linesvoid AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI,
} }
const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
unsigned NewDestReg = MRI->createVirtualRegister(RegClass); unsigned NewDestReg = MRI->createVirtualRegister(RegClass);
LRegion->replaceRegisterInsideRegion(PHIDest, NewDestReg, false, MRI); LRegion->replaceRegisterInsideRegion(PHIDest, NewDestReg, false, MRI);
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(), BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(),
TII->get(TargetOpcode::PHI), NewDestReg); TII->get(TargetOpcode::PHI), NewDestReg);
DEBUG(dbgs() << "Split Entry PHI " << PrintReg(NewDestReg, TRI) DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI)
<< "<def> = PHI("); << "<def> = PHI(");
MIB.addReg(PHISource); MIB.addReg(PHISource);
MIB.addMBB(Entry); MIB.addMBB(Entry);
DEBUG(dbgs() << PrintReg(PHISource, TRI) << ", BB#" << Entry->getNumber()); DEBUG(dbgs() << printReg(PHISource, TRI) << ", BB#" << Entry->getNumber());
MIB.addReg(RegionSourceReg); MIB.addReg(RegionSourceReg);
MIB.addMBB(RegionSourceMBB); MIB.addMBB(RegionSourceMBB);
DEBUG(dbgs() << " ," << PrintReg(RegionSourceReg, TRI) << ", BB#" DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", BB#"
<< RegionSourceMBB->getNumber() << ")\n"); << RegionSourceMBB->getNumber() << ")\n");
} }
void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry, void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry,
MachineBasicBlock *EntrySucc, MachineBasicBlock *EntrySucc,
LinearizedRegion *LRegion) { LinearizedRegion *LRegion) {
SmallVector<MachineInstr *, 2> PHIs; SmallVector<MachineInstr *, 2> PHIs;
collectPHIs(Entry, PHIs); collectPHIs(Entry, PHIs);
▲ Show 20 Lines • Show All 206 Lines • ▼ Show 20 Lines if (Child->isRegion()) {
if (!InnerLRegion->getExit()->isSuccessor(CurrentMerge)) if (!InnerLRegion->getExit()->isSuccessor(CurrentMerge))
InnerLRegion->getExit()->addSuccessor(CurrentMerge); InnerLRegion->getExit()->addSuccessor(CurrentMerge);
continue; continue;
} }
BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegOut = Child->getBBSelectRegOut();
BBSelectRegIn = Child->getBBSelectRegIn(); BBSelectRegIn = Child->getBBSelectRegIn();
DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI) DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
<< "\n"); << "\n");
DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI) DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
<< "\n"); << "\n");
MachineBasicBlock *IfEnd = CurrentMerge; MachineBasicBlock *IfEnd = CurrentMerge;
CurrentMerge = createIfRegion(CurrentMerge, InnerLRegion, LRegion, CurrentMerge = createIfRegion(CurrentMerge, InnerLRegion, LRegion,
Child->getRegionMRT()->getEntry(), Child->getRegionMRT()->getEntry(),
BBSelectRegIn, BBSelectRegOut); BBSelectRegIn, BBSelectRegOut);
TII->convertNonUniformIfRegion(CurrentMerge, IfEnd); TII->convertNonUniformIfRegion(CurrentMerge, IfEnd);
} else { } else {
MachineBasicBlock *MBB = Child->getMBBMRT()->getMBB(); MachineBasicBlock *MBB = Child->getMBBMRT()->getMBB();
DEBUG(dbgs() << "Linearizing block: " << MBB->getNumber() << "\n"); DEBUG(dbgs() << "Linearizing block: " << MBB->getNumber() << "\n");
if (MBB == getSingleExitNode(*(MBB->getParent()))) { if (MBB == getSingleExitNode(*(MBB->getParent()))) {
// If this is the exit block then we need to skip to the next. // If this is the exit block then we need to skip to the next.
// The "in" register will be transferred to "out" in the next // The "in" register will be transferred to "out" in the next
// iteration. // iteration.
continue; continue;
} }
BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegOut = Child->getBBSelectRegOut();
BBSelectRegIn = Child->getBBSelectRegIn(); BBSelectRegIn = Child->getBBSelectRegIn();
DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI) DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
<< "\n"); << "\n");
DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI) DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
<< "\n"); << "\n");
MachineBasicBlock *IfEnd = CurrentMerge; MachineBasicBlock *IfEnd = CurrentMerge;
// This is a basic block that is not part of an inner region, we // This is a basic block that is not part of an inner region, we
// need to put it in the current linearized region. // need to put it in the current linearized region.
CurrentMerge = createIfRegion(CurrentMerge, MBB, LRegion, BBSelectRegIn, CurrentMerge = createIfRegion(CurrentMerge, MBB, LRegion, BBSelectRegIn,
BBSelectRegOut); BBSelectRegOut);
if (CurrentMerge) { if (CurrentMerge) {
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Linesvoid AMDGPUMachineCFGStructurizer::initFallthroughMap(MachineFunction &MF) {
} }
} }
void AMDGPUMachineCFGStructurizer::createLinearizedRegion(RegionMRT *Region, void AMDGPUMachineCFGStructurizer::createLinearizedRegion(RegionMRT *Region,
unsigned SelectOut) { unsigned SelectOut) {
LinearizedRegion *LRegion = new LinearizedRegion(); LinearizedRegion *LRegion = new LinearizedRegion();
if (SelectOut) { if (SelectOut) {
LRegion->addLiveOut(SelectOut); LRegion->addLiveOut(SelectOut);
DEBUG(dbgs() << "Add LiveOut (BBSelect): " << PrintReg(SelectOut, TRI) DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI)
<< "\n"); << "\n");
} }
LRegion->setRegionMRT(Region); LRegion->setRegionMRT(Region);
Region->setLinearizedRegion(LRegion); Region->setLinearizedRegion(LRegion);
LRegion->setParent(Region->getParent() LRegion->setParent(Region->getParent()
? Region->getParent()->getLinearizedRegion() ? Region->getParent()->getLinearizedRegion()
: nullptr); : nullptr);
} }
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
if (!LIS.hasInterval(Reg)) if (!LIS.hasInterval(Reg))
continue; continue;
const auto &LI = LIS.getInterval(Reg); const auto &LI = LIS.getInterval(Reg);
if (LI.hasSubRanges()) { if (LI.hasSubRanges()) {
bool firstTime = true; bool firstTime = true;
for (const auto &S : LI.subranges()) { for (const auto &S : LI.subranges()) {
if (!S.liveAt(SI)) continue; if (!S.liveAt(SI)) continue;
if (firstTime) { if (firstTime) {
dbgs() << " " << PrintReg(Reg, MRI.getTargetRegisterInfo()) dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
<< '\n'; << '\n';
firstTime = false; firstTime = false;
} }
dbgs() << " " << S << '\n'; dbgs() << " " << S << '\n';
++Num; ++Num;
} }
} else if (LI.liveAt(SI)) { } else if (LI.liveAt(SI)) {
dbgs() << " " << LI << '\n'; dbgs() << " " << LI << '\n';
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Lines
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD LLVM_DUMP_METHOD
static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
const GCNRPTracker::LiveRegSet &TrackedLR, const GCNRPTracker::LiveRegSet &TrackedLR,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
for (auto const &P : TrackedLR) { for (auto const &P : TrackedLR) {
auto I = LISLR.find(P.first); auto I = LISLR.find(P.first);
if (I == LISLR.end()) { if (I == LISLR.end()) {
dbgs() << " " << PrintReg(P.first, TRI) dbgs() << " " << printReg(P.first, TRI)
<< ":L" << PrintLaneMask(P.second) << ":L" << PrintLaneMask(P.second)
<< " isn't found in LIS reported set\n"; << " isn't found in LIS reported set\n";
} }
else if (I->second != P.second) { else if (I->second != P.second) {
dbgs() << " " << PrintReg(P.first, TRI) dbgs() << " " << printReg(P.first, TRI)
<< " masks doesn't match: LIS reported " << " masks doesn't match: LIS reported "
<< PrintLaneMask(I->second) << PrintLaneMask(I->second)
<< ", tracked " << ", tracked "
<< PrintLaneMask(P.second) << PrintLaneMask(P.second)
<< '\n'; << '\n';
} }
} }
for (auto const &P : LISLR) { for (auto const &P : LISLR) {
auto I = TrackedLR.find(P.first); auto I = TrackedLR.find(P.first);
if (I == TrackedLR.end()) { if (I == TrackedLR.end()) {
dbgs() << " " << PrintReg(P.first, TRI) dbgs() << " " << printReg(P.first, TRI)
<< ":L" << PrintLaneMask(P.second) << ":L" << PrintLaneMask(P.second)
<< " isn't found in tracked set\n"; << " isn't found in tracked set\n";
} }
} }
} }
bool GCNUpwardRPTracker::isValid() const { bool GCNUpwardRPTracker::isValid() const {
const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex(); const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
Show All 21 Lines
void GCNRPTracker::printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs, void GCNRPTracker::printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
const MachineRegisterInfo &MRI) { const MachineRegisterInfo &MRI) {
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(I); unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
auto It = LiveRegs.find(Reg); auto It = LiveRegs.find(Reg);
if (It != LiveRegs.end() && It->second.any()) if (It != LiveRegs.end() && It->second.any())
OS << ' ' << PrintVRegOrUnit(Reg, TRI) << ':' OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
<< PrintLaneMask(It->second); << PrintLaneMask(It->second);
} }
OS << '\n'; OS << '\n';
} }
#endif #endif

llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp

Show First 20 Lines • Show All 589 Lines • ▼ Show 20 Linesvoid SIScheduleBlock::printDebug(bool full) {
if (Scheduled) { if (Scheduled) {
dbgs() << "LiveInPressure " << LiveInPressure[DAG->getSGPRSetID()] << ' ' dbgs() << "LiveInPressure " << LiveInPressure[DAG->getSGPRSetID()] << ' '
<< LiveInPressure[DAG->getVGPRSetID()] << '\n'; << LiveInPressure[DAG->getVGPRSetID()] << '\n';
dbgs() << "LiveOutPressure " << LiveOutPressure[DAG->getSGPRSetID()] << ' ' dbgs() << "LiveOutPressure " << LiveOutPressure[DAG->getSGPRSetID()] << ' '
<< LiveOutPressure[DAG->getVGPRSetID()] << "\n\n"; << LiveOutPressure[DAG->getVGPRSetID()] << "\n\n";
dbgs() << "LiveIns:\n"; dbgs() << "LiveIns:\n";
for (unsigned Reg : LiveInRegs) for (unsigned Reg : LiveInRegs)
dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
dbgs() << "\nLiveOuts:\n"; dbgs() << "\nLiveOuts:\n";
for (unsigned Reg : LiveOutRegs) for (unsigned Reg : LiveOutRegs)
dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
} }
dbgs() << "\nInstructions:\n"; dbgs() << "\nInstructions:\n";
if (!Scheduled) { if (!Scheduled) {
for (SUnit* SU : SUnits) { for (SUnit* SU : SUnits) {
SU->dump(DAG); SU->dump(DAG);
} }
} else { } else {
▲ Show 20 Lines • Show All 1,019 Lines • ▼ Show 20 Lines if (SregCurrentUsage > maxSregUsage)
maxSregUsage = SregCurrentUsage; maxSregUsage = SregCurrentUsage;
DEBUG( DEBUG(
dbgs() << "Picking New Blocks\n"; dbgs() << "Picking New Blocks\n";
dbgs() << "Available: "; dbgs() << "Available: ";
for (SIScheduleBlock* Block : ReadyBlocks) for (SIScheduleBlock* Block : ReadyBlocks)
dbgs() << Block->getID() << ' '; dbgs() << Block->getID() << ' ';
dbgs() << "\nCurrent Live:\n"; dbgs() << "\nCurrent Live:\n";
for (unsigned Reg : LiveRegs) for (unsigned Reg : LiveRegs)
dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
dbgs() << '\n'; dbgs() << '\n';
dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n'; dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n';
dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n'; dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n';
); );
Cand.Block = nullptr; Cand.Block = nullptr;
for (std::vector<SIScheduleBlock*>::iterator I = ReadyBlocks.begin(), for (std::vector<SIScheduleBlock*>::iterator I = ReadyBlocks.begin(),
E = ReadyBlocks.end(); I != E; ++I) { E = ReadyBlocks.end(); I != E; ++I) {
▲ Show 20 Lines • Show All 412 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Lines for (MachineBasicBlock::iterator J
break; break;
} }
bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI); bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI);
if (J->modifiesRegister(CopyToExec, TRI)) { if (J->modifiesRegister(CopyToExec, TRI)) {
if (SaveExecInst) { if (SaveExecInst) {
DEBUG(dbgs() << "Multiple instructions modify " DEBUG(dbgs() << "Multiple instructions modify "
<< PrintReg(CopyToExec, TRI) << '\n'); << printReg(CopyToExec, TRI) << '\n');
SaveExecInst = nullptr; SaveExecInst = nullptr;
break; break;
} }
unsigned SaveExecOp = getSaveExecOp(J->getOpcode()); unsigned SaveExecOp = getSaveExecOp(J->getOpcode());
if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END) if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END)
break; break;
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines MachineMemOperand *MMO = MF.getMachineMemOperand(
MachinePointerInfo::getFixedStack(MF, FrameIndex), MachinePointerInfo::getFixedStack(MF, FrameIndex),
MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), Align); MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), Align);
assert(MMO && "Couldn't get MachineMemOperand for store to stack."); assert(MMO && "Couldn't get MachineMemOperand for store to stack.");
assert(TRI->getSpillSize(*RC) == 4 && assert(TRI->getSpillSize(*RC) == 4 &&
"Only support 4-byte stores to stack now."); "Only support 4-byte stores to stack now.");
assert(ARC::GPR32RegClass.hasSubClassEq(RC) && assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
"Only support GPR32 stores to stack now."); "Only support GPR32 stores to stack now.");
DEBUG(dbgs() << "Created store reg=" << PrintReg(SrcReg, TRI) DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)
<< " to FrameIndex=" << FrameIndex << "\n"); << " to FrameIndex=" << FrameIndex << "\n");
BuildMI(MBB, I, dl, get(ARC::ST_rs9)) BuildMI(MBB, I, dl, get(ARC::ST_rs9))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIndex) .addFrameIndex(FrameIndex)
.addImm(0) .addImm(0)
.addMemOperand(MMO); .addMemOperand(MMO);
} }
Show All 10 Lines MachineMemOperand *MMO = MF.getMachineMemOperand(
MachinePointerInfo::getFixedStack(MF, FrameIndex), MachinePointerInfo::getFixedStack(MF, FrameIndex),
MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), Align); MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), Align);
assert(MMO && "Couldn't get MachineMemOperand for store to stack."); assert(MMO && "Couldn't get MachineMemOperand for store to stack.");
assert(TRI->getSpillSize(*RC) == 4 && assert(TRI->getSpillSize(*RC) == 4 &&
"Only support 4-byte loads from stack now."); "Only support 4-byte loads from stack now.");
assert(ARC::GPR32RegClass.hasSubClassEq(RC) && assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
"Only support GPR32 stores to stack now."); "Only support GPR32 stores to stack now.");
DEBUG(dbgs() << "Created load reg=" << PrintReg(DestReg, TRI) DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI)
<< " from FrameIndex=" << FrameIndex << "\n"); << " from FrameIndex=" << FrameIndex << "\n");
BuildMI(MBB, I, dl, get(ARC::LD_rs9)) BuildMI(MBB, I, dl, get(ARC::LD_rs9))
.addReg(DestReg, RegState::Define) .addReg(DestReg, RegState::Define)
.addFrameIndex(FrameIndex) .addFrameIndex(FrameIndex)
.addImm(0) .addImm(0)
.addMemOperand(MMO); .addMemOperand(MMO);
} }
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARC/ARCRegisterInfo.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
if (!BaseReg) { if (!BaseReg) {
// We can be sure that the scavenged-register slot is within the range // We can be sure that the scavenged-register slot is within the range
// of the load offset. // of the load offset.
const TargetRegisterInfo *TRI = const TargetRegisterInfo *TRI =
MBB.getParent()->getSubtarget().getRegisterInfo(); MBB.getParent()->getSubtarget().getRegisterInfo();
BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
assert(BaseReg && "Register scavenging failed."); assert(BaseReg && "Register scavenging failed.");
DEBUG(dbgs() << "Scavenged register " << PrintReg(BaseReg, TRI) DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
<< " for FrameReg=" << PrintReg(FrameReg, TRI) << " for FrameReg=" << printReg(FrameReg, TRI)
<< "+Offset=" << Offset << "\n"); << "+Offset=" << Offset << "\n");
(void)TRI; (void)TRI;
RS->setRegUsed(BaseReg); RS->setRegUsed(BaseReg);
} }
unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
BuildMI(MBB, II, dl, TII.get(AddOpc)) BuildMI(MBB, II, dl, TII.get(AddOpc))
.addReg(BaseReg, RegState::Define) .addReg(BaseReg, RegState::Define)
.addReg(FrameReg) .addReg(FrameReg)
▲ Show 20 Lines • Show All 155 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
// Find the thing we're subreg copying out of - is it of the same // Find the thing we're subreg copying out of - is it of the same
// regclass as DPRMI? (i.e. a DPR or QPR). // regclass as DPRMI? (i.e. a DPR or QPR).
unsigned FullReg = SPRMI->getOperand(1).getReg(); unsigned FullReg = SPRMI->getOperand(1).getReg();
const TargetRegisterClass *TRC = const TargetRegisterClass *TRC =
MRI->getRegClass(MI->getOperand(1).getReg()); MRI->getRegClass(MI->getOperand(1).getReg());
if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
DEBUG(dbgs() << "Subreg copy is compatible - returning "); DEBUG(dbgs() << "Subreg copy is compatible - returning ");
DEBUG(dbgs() << PrintReg(FullReg) << "\n"); DEBUG(dbgs() << printReg(FullReg) << "\n");
eraseInstrWithNoUses(MI); eraseInstrWithNoUses(MI);
return FullReg; return FullReg;
} }
} }
return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg()); return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
} }
} }
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines for (MachineInstr *MI : DefSrcs) {
// match what we're replacing. Otherwise we can optimize a DPR_VFP2 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
// reference into a plain DPR, and that will end poorly. NewReg is // reference into a plain DPR, and that will end poorly. NewReg is
// always virtual here, so there will always be a matching subclass // always virtual here, so there will always be a matching subclass
// to find. // to find.
MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
DEBUG(dbgs() << "Replacing operand " DEBUG(dbgs() << "Replacing operand "
<< **I << " with " << **I << " with "
<< PrintReg(NewReg) << "\n"); << printReg(NewReg) << "\n");
(*I)->substVirtReg(NewReg, 0, *TRI); (*I)->substVirtReg(NewReg, 0, *TRI);
} }
} }
Replacements[MI] = NewReg; Replacements[MI] = NewReg;
} }
} }
return Modified; return Modified;
} }
Show All 36 Lines

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

Show First 20 Lines • Show All 1,791 Lines • ▼ Show 20 Lines if (AFI->isThumb1OnlyFunction()) {
SmallVector<unsigned, 4> AvailableRegs; SmallVector<unsigned, 4> AvailableRegs;
// Unused argument registers (r0-r3) can be clobbered in the prologue for // Unused argument registers (r0-r3) can be clobbered in the prologue for
// free. // free.
int EntryRegDeficit = 0; int EntryRegDeficit = 0;
for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
if (!MF.getRegInfo().isLiveIn(Reg)) { if (!MF.getRegInfo().isLiveIn(Reg)) {
--EntryRegDeficit; --EntryRegDeficit;
DEBUG(dbgs() << PrintReg(Reg, TRI) DEBUG(dbgs() << printReg(Reg, TRI)
<< " is unused argument register, EntryRegDeficit = " << " is unused argument register, EntryRegDeficit = "
<< EntryRegDeficit << "\n"); << EntryRegDeficit << "\n");
} }
} }
// Unused return registers can be clobbered in the epilogue for free. // Unused return registers can be clobbered in the epilogue for free.
int ExitRegDeficit = AFI->getReturnRegsCount() - 4; int ExitRegDeficit = AFI->getReturnRegsCount() - 4;
DEBUG(dbgs() << AFI->getReturnRegsCount() DEBUG(dbgs() << AFI->getReturnRegsCount()
<< " return regs used, ExitRegDeficit = " << ExitRegDeficit << " return regs used, ExitRegDeficit = " << ExitRegDeficit
<< "\n"); << "\n");
int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit); int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n"); DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");
// r4-r6 can be used in the prologue if they are pushed by the first push // r4-r6 can be used in the prologue if they are pushed by the first push
// instruction. // instruction.
for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
if (SavedRegs.test(Reg)) { if (SavedRegs.test(Reg)) {
--RegDeficit; --RegDeficit;
DEBUG(dbgs() << PrintReg(Reg, TRI) DEBUG(dbgs() << printReg(Reg, TRI)
<< " is saved low register, RegDeficit = " << RegDeficit << " is saved low register, RegDeficit = " << RegDeficit
<< "\n"); << "\n");
} else { } else {
AvailableRegs.push_back(Reg); AvailableRegs.push_back(Reg);
DEBUG(dbgs() DEBUG(dbgs()
<< PrintReg(Reg, TRI) << printReg(Reg, TRI)
<< " is non-saved low register, adding to AvailableRegs\n"); << " is non-saved low register, adding to AvailableRegs\n");
} }
} }
// r7 can be used if it is not being used as the frame pointer. // r7 can be used if it is not being used as the frame pointer.
if (!HasFP) { if (!HasFP) {
if (SavedRegs.test(ARM::R7)) { if (SavedRegs.test(ARM::R7)) {
--RegDeficit; --RegDeficit;
DEBUG(dbgs() << "%R7 is saved low register, RegDeficit = " DEBUG(dbgs() << "%R7 is saved low register, RegDeficit = "
<< RegDeficit << "\n"); << RegDeficit << "\n");
} else { } else {
AvailableRegs.push_back(ARM::R7); AvailableRegs.push_back(ARM::R7);
DEBUG(dbgs() DEBUG(dbgs()
<< "%R7 is non-saved low register, adding to AvailableRegs\n"); << "%R7 is non-saved low register, adding to AvailableRegs\n");
} }
} }
// Each of r8-r11 needs to be copied to a low register, then pushed. // Each of r8-r11 needs to be copied to a low register, then pushed.
for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
if (SavedRegs.test(Reg)) { if (SavedRegs.test(Reg)) {
++RegDeficit; ++RegDeficit;
DEBUG(dbgs() << PrintReg(Reg, TRI) DEBUG(dbgs() << printReg(Reg, TRI)
<< " is saved high register, RegDeficit = " << RegDeficit << " is saved high register, RegDeficit = " << RegDeficit
<< "\n"); << "\n");
} }
} }
// LR can only be used by PUSH, not POP, and can't be used at all if the // LR can only be used by PUSH, not POP, and can't be used at all if the
// llvm.returnaddress intrinsic is used. This is only worth doing if we // llvm.returnaddress intrinsic is used. This is only worth doing if we
// are more limited at function entry than exit. // are more limited at function entry than exit.
Show All 13 Lines if (AFI->isThumb1OnlyFunction()) {
// If there are more high registers that need pushing than low registers // If there are more high registers that need pushing than low registers
// available, push some more low registers so that we can use fewer push // available, push some more low registers so that we can use fewer push
// instructions. This might not reduce RegDeficit all the way to zero, // instructions. This might not reduce RegDeficit all the way to zero,
// because we can only guarantee that r4-r6 are available, but r8-r11 may // because we can only guarantee that r4-r6 are available, but r8-r11 may
// need saving. // need saving.
DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n"); DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) { for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {
unsigned Reg = AvailableRegs.pop_back_val(); unsigned Reg = AvailableRegs.pop_back_val();
DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
<< " to make up reg deficit\n"); << " to make up reg deficit\n");
SavedRegs.set(Reg); SavedRegs.set(Reg);
NumGPRSpills++; NumGPRSpills++;
CS1Spilled = true; CS1Spilled = true;
assert(!MRI.isReserved(Reg) && "Should not be reserved"); assert(!MRI.isReserved(Reg) && "Should not be reserved");
if (!MRI.isPhysRegUsed(Reg)) if (!MRI.isPhysRegUsed(Reg))
ExtraCSSpill = true; ExtraCSSpill = true;
UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg)); UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));
Show All 28 Lines if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
unsigned Reg = UnspilledCS1GPRs[i]; unsigned Reg = UnspilledCS1GPRs[i];
// Don't spill high register if the function is thumb. In the case of // Don't spill high register if the function is thumb. In the case of
// Windows on ARM, accept R11 (frame pointer) // Windows on ARM, accept R11 (frame pointer)
if (!AFI->isThumbFunction() || if (!AFI->isThumbFunction() ||
(STI.isTargetWindows() && Reg == ARM::R11) || (STI.isTargetWindows() && Reg == ARM::R11) ||
isARMLowRegister(Reg) || Reg == ARM::LR) { isARMLowRegister(Reg) || Reg == ARM::LR) {
SavedRegs.set(Reg); SavedRegs.set(Reg);
DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
<< " to make up alignment\n"); << " to make up alignment\n");
if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
ExtraCSSpill = true; ExtraCSSpill = true;
break; break;
} }
} }
} else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
unsigned Reg = UnspilledCS2GPRs.front(); unsigned Reg = UnspilledCS2GPRs.front();
SavedRegs.set(Reg); SavedRegs.set(Reg);
DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
<< " to make up alignment\n"); << " to make up alignment\n");
if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
ExtraCSSpill = true; ExtraCSSpill = true;
} }
} }
// Estimate if we might need to scavenge a register at some point in order // Estimate if we might need to scavenge a register at some point in order
// to materialize a stack offset. If so, either spill one additional // to materialize a stack offset. If so, either spill one additional
▲ Show 20 Lines • Show All 527 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/BitTracker.cpp

Show First 20 Lines • Show All 176 Lines • ▼ Show 20 Lines raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) {
return OS; return OS;
} }
} // end namespace llvm } // end namespace llvm
void BitTracker::print_cells(raw_ostream &OS) const { void BitTracker::print_cells(raw_ostream &OS) const {
for (const std::pair<unsigned, RegisterCell> P : Map) for (const std::pair<unsigned, RegisterCell> P : Map)
dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
} }
BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F)
: Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) {} : Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) {}
BitTracker::~BitTracker() { BitTracker::~BitTracker() {
delete &Map; delete &Map;
} }
▲ Show 20 Lines • Show All 595 Lines • ▼ Show 20 Lines if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
if (Trace) if (Trace)
dbgs() << " not executable\n"; dbgs() << " not executable\n";
continue; continue;
} }
RegisterRef RU = PI.getOperand(i); RegisterRef RU = PI.getOperand(i);
RegisterCell ResC = ME.getCell(RU, Map); RegisterCell ResC = ME.getCell(RU, Map);
if (Trace) if (Trace)
dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
<< " cell: " << ResC << "\n"; << " cell: " << ResC << "\n";
Changed |= DefC.meet(ResC, DefRR.Reg); Changed |= DefC.meet(ResC, DefRR.Reg);
} }
if (Changed) { if (Changed) {
if (Trace) if (Trace)
dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub) dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
<< " cell: " << DefC << "\n"; << " cell: " << DefC << "\n";
ME.putCell(DefRR, DefC, Map); ME.putCell(DefRR, DefC, Map);
visitUsesOf(DefRR.Reg); visitUsesOf(DefRR.Reg);
} }
} }
void BT::visitNonBranch(const MachineInstr &MI) { void BT::visitNonBranch(const MachineInstr &MI) {
if (Trace) { if (Trace) {
int ThisN = MI.getParent()->getNumber(); int ThisN = MI.getParent()->getNumber();
dbgs() << "Visit MI(BB#" << ThisN << "): " << MI; dbgs() << "Visit MI(BB#" << ThisN << "): " << MI;
} }
if (MI.isDebugValue()) if (MI.isDebugValue())
return; return;
assert(!MI.isBranch() && "Unexpected branch instruction"); assert(!MI.isBranch() && "Unexpected branch instruction");
CellMapType ResMap; CellMapType ResMap;
bool Eval = ME.evaluate(MI, Map, ResMap); bool Eval = ME.evaluate(MI, Map, ResMap);
if (Trace && Eval) { if (Trace && Eval) {
for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
const MachineOperand &MO = MI.getOperand(i); const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse()) if (!MO.isReg() || !MO.isUse())
continue; continue;
RegisterRef RU(MO); RegisterRef RU(MO);
dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
<< " cell: " << ME.getCell(RU, Map) << "\n"; << " cell: " << ME.getCell(RU, Map) << "\n";
} }
dbgs() << "Outputs:\n"; dbgs() << "Outputs:\n";
for (const std::pair<unsigned, RegisterCell> &P : ResMap) { for (const std::pair<unsigned, RegisterCell> &P : ResMap) {
RegisterRef RD(P.first); RegisterRef RD(P.first);
dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: " dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "
<< ME.getCell(RD, ResMap) << "\n"; << ME.getCell(RD, ResMap) << "\n";
} }
} }
// Iterate over all definitions of the instruction, and update the // Iterate over all definitions of the instruction, and update the
// cells accordingly. // cells accordingly.
for (const MachineOperand &MO : MI.operands()) { for (const MachineOperand &MO : MI.operands()) {
// Visit register defs only. // Visit register defs only.
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesvoid BT::visitBranchesFrom(const MachineInstr &BI) {
} }
for (const MachineBasicBlock *TB : Targets) for (const MachineBasicBlock *TB : Targets)
FlowQ.push(CFGEdge(ThisN, TB->getNumber())); FlowQ.push(CFGEdge(ThisN, TB->getNumber()));
} }
void BT::visitUsesOf(unsigned Reg) { void BT::visitUsesOf(unsigned Reg) {
if (Trace) if (Trace)
dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; dbgs() << "visiting uses of " << printReg(Reg, &ME.TRI) << "\n";
for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) { for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) {
if (!InstrExec.count(&UseI)) if (!InstrExec.count(&UseI))
continue; continue;
if (UseI.isPHI()) if (UseI.isPHI())
visitPHI(UseI); visitPHI(UseI);
else if (!UseI.isBranch()) else if (!UseI.isBranch())
visitNonBranch(UseI); visitNonBranch(UseI);
▲ Show 20 Lines • Show All 140 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines private:
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
}; };
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P)
LLVM_ATTRIBUTE_UNUSED; LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{'; OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
OS << ' ' << PrintReg(R, P.TRI); OS << ' ' << printReg(R, P.TRI);
OS << " }"; OS << " }";
return OS; return OS;
} }
class Transformation; class Transformation;
class HexagonBitSimplify : public MachineFunctionPass { class HexagonBitSimplify : public MachineFunctionPass {
public: public:
▲ Show 20 Lines • Show All 2,263 Lines • ▼ Show 20 Lines if (TopV.is(0) || TopV.is(1)) {
Signed = true; Signed = true;
} }
// This would be just a copy. It should be handled elsewhere. // This would be just a copy. It should be handled elsewhere.
if (Len == RW) if (Len == RW)
return false; return false;
DEBUG({ DEBUG({
dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub) dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
<< ", MI: " << *MI; << ", MI: " << *MI;
dbgs() << "Cell: " << RC << '\n'; dbgs() << "Cell: " << RC << '\n';
dbgs() << "Expected bitfield size: " << Len << " bits, " dbgs() << "Expected bitfield size: " << Len << " bits, "
<< (Signed ? "sign" : "zero") << "-extended\n"; << (Signed ? "sign" : "zero") << "-extended\n";
}); });
bool Changed = false; bool Changed = false;
▲ Show 20 Lines • Show All 534 Lines • ▼ Show 20 Lines if (BadUse || !GoodUse)
continue; continue;
Phis.push_back(PhiInfo(I, *C.LB)); Phis.push_back(PhiInfo(I, *C.LB));
} }
DEBUG({ DEBUG({
dbgs() << "Phis: {"; dbgs() << "Phis: {";
for (auto &I : Phis) { for (auto &I : Phis) {
dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
<< PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
<< ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
<< I.LB->getNumber() << ')'; << I.LB->getNumber() << ')';
} }
dbgs() << " }\n"; dbgs() << " }\n";
}); });
if (Phis.empty()) if (Phis.empty())
return false; return false;
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines for (unsigned i = 0, n = ShufIns.size(); i < n; ++i) {
G.Inp.Reg = Inputs.find_first(); G.Inp.Reg = Inputs.find_first();
Groups.push_back(G); Groups.push_back(G);
} }
DEBUG({ DEBUG({
for (unsigned i = 0, n = Groups.size(); i < n; ++i) { for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
InstrGroup &G = Groups[i]; InstrGroup &G = Groups[i];
dbgs() << "Group[" << i << "] inp: " dbgs() << "Group[" << i << "] inp: "
<< PrintReg(G.Inp.Reg, HRI, G.Inp.Sub) << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
<< " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
for (unsigned j = 0, m = G.Ins.size(); j < m; ++j) for (unsigned j = 0, m = G.Ins.size(); j < m; ++j)
dbgs() << " " << *G.Ins[j]; dbgs() << " " << *G.Ins[j];
} }
}); });
for (unsigned i = 0, n = Groups.size(); i < n; ++i) { for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
InstrGroup &G = Groups[i]; InstrGroup &G = Groups[i];
if (!isShuffleOf(G.Out.Reg, G.Inp.Reg)) if (!isShuffleOf(G.Out.Reg, G.Inp.Reg))
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines switch (ID) {
case Hexagon::DoubleRegsRegClassID: case Hexagon::DoubleRegsRegClassID:
case Hexagon::HvxWRRegClassID: case Hexagon::HvxWRRegClassID:
return IsSubLo ? BT::BitMask(0, RW-1) return IsSubLo ? BT::BitMask(0, RW-1)
: BT::BitMask(RW, 2*RW-1); : BT::BitMask(RW, 2*RW-1);
default: default:
break; break;
} }
#ifndef NDEBUG #ifndef NDEBUG
dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class " dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
<< TRI.getRegClassName(&RC) << '\n'; << TRI.getRegClassName(&RC) << '\n';
#endif #endif
llvm_unreachable("Unexpected register/subregister"); llvm_unreachable("Unexpected register/subregister");
} }
uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const { uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
assert(TargetRegisterInfo::isPhysicalRegister(Reg)); assert(TargetRegisterInfo::isPhysicalRegister(Reg));
▲ Show 20 Lines • Show All 1,140 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp

Show First 20 Lines • Show All 525 Lines • ▼ Show 20 Linesraw_ostream &llvm::operator<<(raw_ostream &OS,
} }
return OS; return OS;
} }
raw_ostream &llvm::operator<<(raw_ostream &OS, raw_ostream &llvm::operator<<(raw_ostream &OS,
const HexagonBlockRanges::PrintRangeMap &P) { const HexagonBlockRanges::PrintRangeMap &P) {
for (auto &I : P.Map) { for (auto &I : P.Map) {
const HexagonBlockRanges::RangeList &RL = I.second; const HexagonBlockRanges::RangeList &RL = I.second;
OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
} }
return OS; return OS;
} }

llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp

Show First 20 Lines • Show All 416 Lines • ▼ Show 20 Lines PrintRegister(HCE::Register R, const HexagonRegisterInfo &I)
: Rs(R), HRI(I) {} : Rs(R), HRI(I) {}
HCE::Register Rs; HCE::Register Rs;
const HexagonRegisterInfo &HRI; const HexagonRegisterInfo &HRI;
}; };
LLVM_ATTRIBUTE_UNUSED LLVM_ATTRIBUTE_UNUSED
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) {
if (P.Rs.Reg != 0) if (P.Rs.Reg != 0)
OS << PrintReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
else else
OS << "noreg"; OS << "noreg";
return OS; return OS;
} }
struct PrintExpr { struct PrintExpr {
PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I) PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I)
: Ex(E), HRI(I) {} : Ex(E), HRI(I) {}
const HCE::ExtExpr &Ex; const HCE::ExtExpr &Ex;
const HexagonRegisterInfo &HRI; const HexagonRegisterInfo &HRI;
}; };
LLVM_ATTRIBUTE_UNUSED LLVM_ATTRIBUTE_UNUSED
raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) {
OS << "## " << (P.Ex.Neg ? "- " : "+ "); OS << "## " << (P.Ex.Neg ? "- " : "+ ");
if (P.Ex.Rs.Reg != 0) if (P.Ex.Rs.Reg != 0)
OS << PrintReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
else else
OS << "__"; OS << "__";
OS << " << " << P.Ex.S; OS << " << " << P.Ex.S;
return OS; return OS;
} }
struct PrintInit { struct PrintInit {
PrintInit(const HCE::ExtenderInit &EI, const HexagonRegisterInfo &I) PrintInit(const HCE::ExtenderInit &EI, const HexagonRegisterInfo &I)
Show All 12 Linesnamespace {
LLVM_ATTRIBUTE_UNUSED LLVM_ATTRIBUTE_UNUSED
raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtDesc &ED) { raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtDesc &ED) {
assert(ED.OpNum != -1u); assert(ED.OpNum != -1u);
const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent(); const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent();
const MachineFunction &MF = *MBB.getParent(); const MachineFunction &MF = *MBB.getParent();
const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
OS << "bb#" << MBB.getNumber() << ": "; OS << "bb#" << MBB.getNumber() << ": ";
if (ED.Rd.Reg != 0) if (ED.Rd.Reg != 0)
OS << PrintReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
else else
OS << "__"; OS << "__";
OS << " = " << PrintExpr(ED.Expr, HRI); OS << " = " << PrintExpr(ED.Expr, HRI);
if (ED.IsDef) if (ED.IsDef)
OS << ", def"; OS << ", def";
return OS; return OS;
} }
▲ Show 20 Lines • Show All 1,395 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Linesnamespace {
struct Register { struct Register {
unsigned Reg, SubReg; unsigned Reg, SubReg;
explicit Register(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {} explicit Register(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
explicit Register(const MachineOperand &MO) explicit Register(const MachineOperand &MO)
: Reg(MO.getReg()), SubReg(MO.getSubReg()) {} : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
void print(const TargetRegisterInfo *TRI = nullptr) const { void print(const TargetRegisterInfo *TRI = nullptr) const {
dbgs() << PrintReg(Reg, TRI, SubReg); dbgs() << printReg(Reg, TRI, SubReg);
} }
bool operator== (const Register &R) const { bool operator== (const Register &R) const {
return (Reg == R.Reg) && (SubReg == R.SubReg); return (Reg == R.Reg) && (SubReg == R.SubReg);
} }
}; };
// Lattice cell, based on that was described in the W-Z paper on constant // Lattice cell, based on that was described in the W-Z paper on constant
▲ Show 20 Lines • Show All 505 Lines • ▼ Show 20 Linesuint32_t LatticeCell::properties() const {
} }
return Ps; return Ps;
} }
#ifndef NDEBUG #ifndef NDEBUG
void MachineConstPropagator::CellMap::print(raw_ostream &os, void MachineConstPropagator::CellMap::print(raw_ostream &os,
const TargetRegisterInfo &TRI) const { const TargetRegisterInfo &TRI) const {
for (auto &I : Map) for (auto &I : Map)
dbgs() << " " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n'; dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
} }
#endif #endif
void MachineConstPropagator::visitPHI(const MachineInstr &PN) { void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
const MachineBasicBlock *MB = PN.getParent(); const MachineBasicBlock *MB = PN.getParent();
unsigned MBN = MB->getNumber(); unsigned MBN = MB->getNumber();
DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN); DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN);
Show All 32 Lines if (!TargetRegisterInfo::isVirtualRegister(UseR.Reg))
goto Bottomize; goto Bottomize;
// If there is no cell for an input register, it means top. // If there is no cell for an input register, it means top.
if (!Cells.has(UseR.Reg)) if (!Cells.has(UseR.Reg))
continue; continue;
LatticeCell SrcC; LatticeCell SrcC;
bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
DEBUG(dbgs() << " edge from BB#" << PBN << ": " DEBUG(dbgs() << " edge from BB#" << PBN << ": "
<< PrintReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
<< SrcC << '\n'); << SrcC << '\n');
Changed |= Eval ? DefC.meet(SrcC) Changed |= Eval ? DefC.meet(SrcC)
: DefC.setBottom(); : DefC.setBottom();
Cells.update(DefR.Reg, DefC); Cells.update(DefR.Reg, DefC);
if (DefC.isBottom()) if (DefC.isBottom())
break; break;
} }
if (Changed) if (Changed)
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Linesvoid MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
for (const MachineBasicBlock *TB : Targets) { for (const MachineBasicBlock *TB : Targets) {
unsigned TBN = TB->getNumber(); unsigned TBN = TB->getNumber();
DEBUG(dbgs() << " pushing edge BB#" << MBN << " -> BB#" << TBN << "\n"); DEBUG(dbgs() << " pushing edge BB#" << MBN << " -> BB#" << TBN << "\n");
FlowQ.push(CFGEdge(MBN, TBN)); FlowQ.push(CFGEdge(MBN, TBN));
} }
} }
void MachineConstPropagator::visitUsesOf(unsigned Reg) { void MachineConstPropagator::visitUsesOf(unsigned Reg) {
DEBUG(dbgs() << "Visiting uses of " << PrintReg(Reg, &MCE.TRI) DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
<< Cells.get(Reg) << '\n'); << Cells.get(Reg) << '\n');
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
// Do not process non-executable instructions. They can become exceutable // Do not process non-executable instructions. They can become exceutable
// later (via a flow-edge in the work queue). In such case, the instruc- // later (via a flow-edge in the work queue). In such case, the instruc-
// tion will be visited at that time. // tion will be visited at that time.
if (!InstrExec.count(&MI)) if (!InstrExec.count(&MI))
continue; continue;
if (MI.isPHI()) if (MI.isPHI())
▲ Show 20 Lines • Show All 1,993 Lines • ▼ Show 20 Lines for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue; continue;
Register R(MO); Register R(MO);
if (!TargetRegisterInfo::isVirtualRegister(R.Reg)) if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
continue; continue;
HasUse = true; HasUse = true;
// PHIs can legitimately have "top" cells after propagation. // PHIs can legitimately have "top" cells after propagation.
if (!MI.isPHI() && !Inputs.has(R.Reg)) { if (!MI.isPHI() && !Inputs.has(R.Reg)) {
dbgs() << "Top " << PrintReg(R.Reg, &HRI, R.SubReg) dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
<< " in MI: " << MI; << " in MI: " << MI;
continue; continue;
} }
const LatticeCell &L = Inputs.get(R.Reg); const LatticeCell &L = Inputs.get(R.Reg);
Const &= L.isSingle(); Const &= L.isSingle();
if (!Const) if (!Const)
break; break;
} }
if (HasUse && Const) { if (HasUse && Const) {
if (!MI.isCopy()) { if (!MI.isCopy()) {
dbgs() << "CONST: " << MI; dbgs() << "CONST: " << MI;
for (const MachineOperand &MO : MI.operands()) { for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue; continue;
unsigned R = MO.getReg(); unsigned R = MO.getReg();
dbgs() << PrintReg(R, &TRI) << ": " << Inputs.get(R) << "\n"; dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
} }
} }
} }
} }
#endif #endif
// Avoid generating TFRIs for register transfers---this will keep the // Avoid generating TFRIs for register transfers---this will keep the
// coalescing opportunities. // coalescing opportunities.
▲ Show 20 Lines • Show All 351 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines struct PrintFP {
const FlowPattern &FP; const FlowPattern &FP;
const TargetRegisterInfo &TRI; const TargetRegisterInfo &TRI;
friend raw_ostream &operator<< (raw_ostream &OS, const PrintFP &P); friend raw_ostream &operator<< (raw_ostream &OS, const PrintFP &P);
}; };
raw_ostream &operator<<(raw_ostream &OS, raw_ostream &operator<<(raw_ostream &OS,
const PrintFP &P) LLVM_ATTRIBUTE_UNUSED; const PrintFP &P) LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) { raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) {
OS << "{ SplitB:" << PrintMB(P.FP.SplitB) OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
<< ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
<< ", TrueB:" << PrintMB(P.FP.TrueB) << ", TrueB:" << PrintMB(P.FP.TrueB)
<< ", FalseB:" << PrintMB(P.FP.FalseB) << ", FalseB:" << PrintMB(P.FP.FalseB)
<< ", JoinB:" << PrintMB(P.FP.JoinB) << " }"; << ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
return OS; return OS;
} }
class HexagonEarlyIfConversion : public MachineFunctionPass { class HexagonEarlyIfConversion : public MachineFunctionPass {
public: public:
▲ Show 20 Lines • Show All 923 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp

Show First 20 Lines • Show All 1,131 Lines • ▼ Show 20 Linesbool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
if (L2.empty()) if (L2.empty())
return false; return false;
if (L1.hasSubRanges() || L2.hasSubRanges()) if (L1.hasSubRanges() || L2.hasSubRanges())
return false; return false;
bool Overlap = L1.overlaps(L2); bool Overlap = L1.overlaps(L2);
DEBUG(dbgs() << "compatible registers: (" DEBUG(dbgs() << "compatible registers: ("
<< (Overlap ? "overlap" : "disjoint") << ")\n " << (Overlap ? "overlap" : "disjoint") << ")\n "
<< PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
<< PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
if (R1.Sub || R2.Sub) if (R1.Sub || R2.Sub)
return false; return false;
if (Overlap) if (Overlap)
return false; return false;
// Coalescing could have a negative impact on scheduling, so try to limit // Coalescing could have a negative impact on scheduling, so try to limit
// to some reasonable extent. Only consider coalescing segments, when one // to some reasonable extent. Only consider coalescing segments, when one
// of them does not cross basic block boundaries. // of them does not cross basic block boundaries.
▲ Show 20 Lines • Show All 181 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp

Show First 20 Lines • Show All 1,365 Lines • ▼ Show 20 Linesstatic bool needToReserveScavengingSpillSlots(MachineFunction &MF,
return true; return true;
} }
#ifndef NDEBUG #ifndef NDEBUG
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
dbgs() << '{'; dbgs() << '{';
for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
unsigned R = x; unsigned R = x;
dbgs() << ' ' << PrintReg(R, &TRI); dbgs() << ' ' << printReg(R, &TRI);
} }
dbgs() << " }"; dbgs() << " }";
} }
#endif #endif
bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const { const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
DEBUG(dbgs() << __func__ << " on " DEBUG(dbgs() << __func__ << " on "
<< MF.getFunction()->getName() << '\n'); << MF.getFunction()->getName() << '\n');
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
BitVector SRegs(Hexagon::NUM_TARGET_REGS); BitVector SRegs(Hexagon::NUM_TARGET_REGS);
// Generate a set of unique, callee-saved registers (SRegs), where each // Generate a set of unique, callee-saved registers (SRegs), where each
// register in the set is maximal in terms of sub-/super-register relation, // register in the set is maximal in terms of sub-/super-register relation,
// i.e. for each R in SRegs, no proper super-register of R is also in SRegs. // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
// (1) For each callee-saved register, add that register and all of its // (1) For each callee-saved register, add that register and all of its
// sub-registers to SRegs. // sub-registers to SRegs.
DEBUG(dbgs() << "Initial CS registers: {"); DEBUG(dbgs() << "Initial CS registers: {");
for (unsigned i = 0, n = CSI.size(); i < n; ++i) { for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
unsigned R = CSI[i].getReg(); unsigned R = CSI[i].getReg();
DEBUG(dbgs() << ' ' << PrintReg(R, TRI)); DEBUG(dbgs() << ' ' << printReg(R, TRI));
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
SRegs[*SR] = true; SRegs[*SR] = true;
} }
DEBUG(dbgs() << " }\n"); DEBUG(dbgs() << " }\n");
DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
// (2) For each reserved register, remove that register and all of its // (2) For each reserved register, remove that register and all of its
// sub- and super-registers from SRegs. // sub- and super-registers from SRegs.
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
SRegs[R] = false; SRegs[R] = false;
} }
DEBUG({ DEBUG({
dbgs() << "CS information: {"; dbgs() << "CS information: {";
for (unsigned i = 0, n = CSI.size(); i < n; ++i) { for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
int FI = CSI[i].getFrameIdx(); int FI = CSI[i].getFrameIdx();
int Off = MFI.getObjectOffset(FI); int Off = MFI.getObjectOffset(FI);
dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
if (Off >= 0) if (Off >= 0)
dbgs() << '+'; dbgs() << '+';
dbgs() << Off; dbgs() << Off;
} }
dbgs() << " }\n"; dbgs() << " }\n";
}); });
#ifndef NDEBUG #ifndef NDEBUG
// Verify that all registers were handled. // Verify that all registers were handled.
bool MissedReg = false; bool MissedReg = false;
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
unsigned R = x; unsigned R = x;
dbgs() << PrintReg(R, TRI) << ' '; dbgs() << printReg(R, TRI) << ' ';
MissedReg = true; MissedReg = true;
} }
if (MissedReg) if (MissedReg)
llvm_unreachable("...there are unhandled callee-saved registers!"); llvm_unreachable("...there are unhandled callee-saved registers!");
#endif #endif
return true; return true;
} }
▲ Show 20 Lines • Show All 687 Lines • ▼ Show 20 Lines for (auto FI : BlockFIMap[&B]) {
assert(EI.mayLoad() && "Unexpected end instruction"); assert(EI.mayLoad() && "Unexpected end instruction");
MachineOperand &SrcOp = SI.getOperand(2); MachineOperand &SrcOp = SI.getOperand(2);
HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
SrcOp.getSubReg() }; SrcOp.getSubReg() };
auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
// The this-> is needed to unconfuse MSVC. // The this-> is needed to unconfuse MSVC.
unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC); unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n'); DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n');
if (FoundR == 0) if (FoundR == 0)
continue; continue;
#ifndef NDEBUG #ifndef NDEBUG
if (HasOptLimit) { if (HasOptLimit) {
if (SpillOptCount >= SpillOptMax) if (SpillOptCount >= SpillOptMax)
return; return;
SpillOptCount++; SpillOptCount++;
} }
▲ Show 20 Lines • Show All 263 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Linesnamespace {
private: private:
const RegisterSet &RS; const RegisterSet &RS;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
}; };
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{'; OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
OS << ' ' << PrintReg(R, P.TRI); OS << ' ' << printReg(R, P.TRI);
OS << " }"; OS << " }";
return OS; return OS;
} }
// A convenience class to associate unsigned numbers (such as virtual // A convenience class to associate unsigned numbers (such as virtual
// registers) with unsigned numbers. // registers) with unsigned numbers.
struct UnsignedMap : public DenseMap<unsigned,unsigned> { struct UnsignedMap : public DenseMap<unsigned,unsigned> {
UnsignedMap() = default; UnsignedMap() = default;
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 Linesnamespace {
}; };
raw_ostream &operator<< (raw_ostream &OS, const PrintORL &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintORL &P) {
OS << '('; OS << '(';
OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end(); OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end();
for (OrderedRegisterList::const_iterator I = B; I != E; ++I) { for (OrderedRegisterList::const_iterator I = B; I != E; ++I) {
if (I != B) if (I != B)
OS << ", "; OS << ", ";
OS << PrintReg(*I, P.TRI); OS << printReg(*I, P.TRI);
} }
OS << ')'; OS << ')';
return OS; return OS;
} }
} // end anonymous namespace } // end anonymous namespace
void OrderedRegisterList::insert(unsigned VR) { void OrderedRegisterList::insert(unsigned VR) {
Show All 31 Lines private:
friend raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P); friend raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P);
const IFRecord &IFR; const IFRecord &IFR;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
}; };
raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) {
unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;
OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
<< ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')'; << ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')';
return OS; return OS;
} }
using IFRecordWithRegSet = std::pair<IFRecord, RegisterSet>; using IFRecordWithRegSet = std::pair<IFRecord, RegisterSet>;
} // end anonymous namespace } // end anonymous namespace
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
} // end anonymous namespace } // end anonymous namespace
char HexagonGenInsert::ID = 0; char HexagonGenInsert::ID = 0;
void HexagonGenInsert::dump_map() const { void HexagonGenInsert::dump_map() const {
using iterator = IFMapType::const_iterator; using iterator = IFMapType::const_iterator;
for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) { for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
dbgs() << " " << PrintReg(I->first, HRI) << ":\n"; dbgs() << " " << printReg(I->first, HRI) << ":\n";
const IFListType &LL = I->second; const IFListType &LL = I->second;
for (unsigned i = 0, n = LL.size(); i < n; ++i) for (unsigned i = 0, n = LL.size(); i < n; ++i)
dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
<< PrintRegSet(LL[i].second, HRI) << '\n'; << PrintRegSet(LL[i].second, HRI) << '\n';
} }
} }
void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Linesunsigned HexagonGenInsert::distance(MachineBasicBlock::const_iterator FromI,
unsigned D2 = distance(FB, TB, RPO, M); unsigned D2 = distance(FB, TB, RPO, M);
unsigned D3 = std::distance(FromI, FB->end()); unsigned D3 = std::distance(FromI, FB->end());
return D1+D2+D3; return D1+D2+D3;
} }
bool HexagonGenInsert::findRecordInsertForms(unsigned VR, bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
OrderedRegisterList &AVs) { OrderedRegisterList &AVs) {
if (isDebug()) { if (isDebug()) {
dbgs() << __func__ << ": " << PrintReg(VR, HRI) dbgs() << __func__ << ": " << printReg(VR, HRI)
<< " AVs: " << PrintORL(AVs, HRI) << "\n"; << " AVs: " << PrintORL(AVs, HRI) << "\n";
} }
if (AVs.size() == 0) if (AVs.size() == 0)
return false; return false;
using iterator = OrderedRegisterList::iterator; using iterator = OrderedRegisterList::iterator;
BitValueOrdering BVO(BaseOrd); BitValueOrdering BVO(BaseOrd);
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines if (B != E) {
LM[L].push_back(std::make_pair(*I, S)); LM[L].push_back(std::make_pair(*I, S));
// If B!=E, then we found a range of registers whose prefixes cover the // If B!=E, then we found a range of registers whose prefixes cover the
// rest of VR from position S. There is no need to further advance S. // rest of VR from position S. There is no need to further advance S.
break; break;
} }
} }
if (isDebug()) { if (isDebug()) {
dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n"; dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) { for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) {
dbgs() << " L=" << I->first << ':'; dbgs() << " L=" << I->first << ':';
const RSListType &LL = I->second; const RSListType &LL = I->second;
for (unsigned i = 0, n = LL.size(); i < n; ++i) for (unsigned i = 0, n = LL.size(); i < n; ++i)
dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
<< LL[i].second << ')'; << LL[i].second << ')';
dbgs() << '\n'; dbgs() << '\n';
} }
} }
bool Recorded = false; bool Recorded = false;
for (iterator I = AVs.begin(), E = AVs.end(); I != E; ++I) { for (iterator I = AVs.begin(), E = AVs.end(); I != E; ++I) {
Show All 30 Lines for (uint16_t L = MinL; L < W; ++L) {
uint16_t EL = L-MinL; uint16_t EL = L-MinL;
uint16_t LowS = (EL < FD) ? FD-EL : 0; uint16_t LowS = (EL < FD) ? FD-EL : 0;
if (S < LowS) // Starts too early. if (S < LowS) // Starts too early.
continue; continue;
unsigned InsR = LL[i].first; unsigned InsR = LL[i].first;
if (!isValidInsertForm(VR, SrcR, InsR, L, S)) if (!isValidInsertForm(VR, SrcR, InsR, L, S))
continue; continue;
if (isDebug()) { if (isDebug()) {
dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI) dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
<< ',' << PrintReg(InsR, HRI) << ",#" << L << ",#" << ',' << printReg(InsR, HRI) << ",#" << L << ",#"
<< S << ")\n"; << S << ")\n";
} }
IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet()); IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet());
IFMap[VR].push_back(RR); IFMap[VR].push_back(RR);
Recorded = true; Recorded = true;
} }
} }
} }
▲ Show 20 Lines • Show All 608 Lines • ▼ Show 20 Linesbool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
buildOrderingMF(BaseOrd); buildOrderingMF(BaseOrd);
buildOrderingBT(BaseOrd, CellOrd); buildOrderingBT(BaseOrd, CellOrd);
if (isDebug()) { if (isDebug()) {
dbgs() << "Cell ordering:\n"; dbgs() << "Cell ordering:\n";
for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end(); for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end();
I != E; ++I) { I != E; ++I) {
unsigned VR = I->first, Pos = I->second; unsigned VR = I->first, Pos = I->second;
dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n"; dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
} }
} }
// Collect candidates for conversion into the insert forms. // Collect candidates for conversion into the insert forms.
MachineBasicBlock *RootB = MDT->getRoot(); MachineBasicBlock *RootB = MDT->getRoot();
OrderedRegisterList AvailR(CellOrd); OrderedRegisterList AvailR(CellOrd);
const char *const TGName = "hexinsert"; const char *const TGName = "hexinsert";
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Linesnamespace {
private: private:
Register Reg; Register Reg;
const TargetRegisterInfo &TRI; const TargetRegisterInfo &TRI;
}; };
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
LLVM_ATTRIBUTE_UNUSED; LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
} }
class HexagonGenPredicate : public MachineFunctionPass { class HexagonGenPredicate : public MachineFunctionPass {
public: public:
static char ID; static char ID;
HexagonGenPredicate() : MachineFunctionPass(ID) { HexagonGenPredicate() : MachineFunctionPass(ID) {
initializeHexagonGenPredicatePass(*PassRegistry::getPassRegistry()); initializeHexagonGenPredicatePass(*PassRegistry::getPassRegistry());
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
break; break;
} }
} }
} }
} }
void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
DEBUG(dbgs() << __func__ << ": " DEBUG(dbgs() << __func__ << ": "
<< PrintReg(Reg.R, TRI, Reg.S) << "\n"); << printReg(Reg.R, TRI, Reg.S) << "\n");
using use_iterator = MachineRegisterInfo::use_iterator; using use_iterator = MachineRegisterInfo::use_iterator;
use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
if (I == E) { if (I == E) {
DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n'); DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
MachineInstr *DefI = MRI->getVRegDef(Reg.R); MachineInstr *DefI = MRI->getVRegDef(Reg.R);
DefI->eraseFromParent(); DefI->eraseFromParent();
return; return;
} }
for (; I != E; ++I) { for (; I != E; ++I) {
MachineInstr *UseI = I->getParent(); MachineInstr *UseI = I->getParent();
if (isConvertibleToPredForm(UseI)) if (isConvertibleToPredForm(UseI))
▲ Show 20 Lines • Show All 301 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp

Show First 20 Lines • Show All 351 Lines • ▼ Show 20 Lines public:
} }
unsigned getImm() const { unsigned getImm() const {
assert(isImm() && "Wrong CountValue accessor"); assert(isImm() && "Wrong CountValue accessor");
return Contents.ImmVal; return Contents.ImmVal;
} }
void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const { void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
if (isImm()) { OS << Contents.ImmVal; } if (isImm()) { OS << Contents.ImmVal; }
} }
}; };
} // end anonymous namespace } // end anonymous namespace
INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops", INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops",
"Hexagon Hardware Loops", false, false) "Hexagon Hardware Loops", false, false)
▲ Show 20 Lines • Show All 1,639 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

Show First 20 Lines • Show All 824 Lines • ▼ Show 20 Lines if (Hexagon::HvxQRRegClass.contains(DestReg) &&
Hexagon::HvxVRRegClass.contains(SrcReg)) { Hexagon::HvxVRRegClass.contains(SrcReg)) {
llvm_unreachable("Unimplemented vec to pred"); llvm_unreachable("Unimplemented vec to pred");
return; return;
} }
#ifndef NDEBUG #ifndef NDEBUG
// Show the invalid registers to ease debugging. // Show the invalid registers to ease debugging.
dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber() dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
<< ": " << PrintReg(DestReg, &HRI) << ": " << printReg(DestReg, &HRI)
<< " = " << PrintReg(SrcReg, &HRI) << '\n'; << " = " << printReg(SrcReg, &HRI) << '\n';
#endif #endif
llvm_unreachable("Unimplemented"); llvm_unreachable("Unimplemented");
} }
void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
DebugLoc DL = MBB.findDebugLoc(I); DebugLoc DL = MBB.findDebugLoc(I);
▲ Show 20 Lines • Show All 3,278 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double", INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
"Hexagon Split Double Registers", false, false) "Hexagon Split Double Registers", false, false)
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os, LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
const USet &Part, const TargetRegisterInfo &TRI) { const USet &Part, const TargetRegisterInfo &TRI) {
dbgs() << '{'; dbgs() << '{';
for (auto I : Part) for (auto I : Part)
dbgs() << ' ' << PrintReg(I, &TRI); dbgs() << ' ' << printReg(I, &TRI);
dbgs() << " }"; dbgs() << " }";
} }
#endif #endif
bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const { bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
for (auto I : IRM) { for (auto I : IRM) {
const USet &Rs = I.second; const USet &Rs = I.second;
if (Rs.find(Reg) != Rs.end()) if (Rs.find(Reg) != Rs.end())
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines if (!DefI || isFixedInstr(DefI))
FixedRegs.set(x); FixedRegs.set(x);
} }
UUSetMap AssocMap; UUSetMap AssocMap;
for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
if (FixedRegs[x]) if (FixedRegs[x])
continue; continue;
unsigned R = TargetRegisterInfo::index2VirtReg(x); unsigned R = TargetRegisterInfo::index2VirtReg(x);
DEBUG(dbgs() << PrintReg(R, TRI) << " ~~"); DEBUG(dbgs() << printReg(R, TRI) << " ~~");
USet &Asc = AssocMap[R]; USet &Asc = AssocMap[R];
for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end(); for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
U != Z; ++U) { U != Z; ++U) {
MachineOperand &Op = *U; MachineOperand &Op = *U;
MachineInstr *UseI = Op.getParent(); MachineInstr *UseI = Op.getParent();
if (isFixedInstr(UseI)) if (isFixedInstr(UseI))
continue; continue;
for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) { for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
MachineOperand &MO = UseI->getOperand(i); MachineOperand &MO = UseI->getOperand(i);
// Skip non-registers or registers with subregisters. // Skip non-registers or registers with subregisters.
if (&MO == &Op || !MO.isReg() || MO.getSubReg()) if (&MO == &Op || !MO.isReg() || MO.getSubReg())
continue; continue;
unsigned T = MO.getReg(); unsigned T = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(T)) { if (!TargetRegisterInfo::isVirtualRegister(T)) {
FixedRegs.set(x); FixedRegs.set(x);
continue; continue;
} }
if (MRI->getRegClass(T) != DoubleRC) if (MRI->getRegClass(T) != DoubleRC)
continue; continue;
unsigned u = TargetRegisterInfo::virtReg2Index(T); unsigned u = TargetRegisterInfo::virtReg2Index(T);
if (FixedRegs[u]) if (FixedRegs[u])
continue; continue;
DEBUG(dbgs() << ' ' << PrintReg(T, TRI)); DEBUG(dbgs() << ' ' << printReg(T, TRI));
Asc.insert(T); Asc.insert(T);
// Make it symmetric. // Make it symmetric.
AssocMap[T].insert(R); AssocMap[T].insert(R);
} }
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
▲ Show 20 Lines • Show All 838 Lines • ▼ Show 20 Lines for (unsigned DR : Part) {
// Collect all instructions, including fixed ones. We won't split them, // Collect all instructions, including fixed ones. We won't split them,
// but we need to visit them again to insert the REG_SEQUENCE instructions. // but we need to visit them again to insert the REG_SEQUENCE instructions.
for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end(); for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
U != W; ++U) U != W; ++U)
SplitIns.insert(U->getParent()); SplitIns.insert(U->getParent());
unsigned LoR = MRI->createVirtualRegister(IntRC); unsigned LoR = MRI->createVirtualRegister(IntRC);
unsigned HiR = MRI->createVirtualRegister(IntRC); unsigned HiR = MRI->createVirtualRegister(IntRC);
DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> " DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
<< PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n'); << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n');
PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR))); PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
} }
MISet Erase; MISet Erase;
for (auto MI : SplitIns) { for (auto MI : SplitIns) {
if (isFixedInstr(MI)) { if (isFixedInstr(MI)) {
collapseRegPairs(MI, PairMap); collapseRegPairs(MI, PairMap);
} else { } else {
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llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp

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namespace llvm { namespace llvm {
namespace rdf { namespace rdf {
template<> template<>
raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) { raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
OS << '{'; OS << '{';
for (auto &I : P.Obj) { for (auto &I : P.Obj) {
OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{'; OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
for (auto J = I.second.begin(), E = I.second.end(); J != E; ) { for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second); OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second);
if (++J != E) if (++J != E)
OS << ','; OS << ',';
} }
OS << '}'; OS << '}';
} }
OS << " }"; OS << " }";
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llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp

Show First 20 Lines • Show All 359 Lines • ▼ Show 20 Lines if (Units.test(P.first))
M |= P.second.none() ? LaneBitmask::getAll() : P.second; M |= P.second.none() ? LaneBitmask::getAll() : P.second;
} }
return RegisterRef(F, M); return RegisterRef(F, M);
} }
void RegisterAggr::print(raw_ostream &OS) const { void RegisterAggr::print(raw_ostream &OS) const {
OS << '{'; OS << '{';
for (int U = Units.find_first(); U >= 0; U = Units.find_next(U)) for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
OS << ' ' << PrintRegUnit(U, &PRI.getTRI()); OS << ' ' << printRegUnit(U, &PRI.getTRI());
OS << " }"; OS << " }";
} }
RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG, RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG,
bool End) bool End)
: Owner(&RG) { : Owner(&RG) {
for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) { for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
RegisterRef R = RG.PRI.getRefForUnit(U); RegisterRef R = RG.PRI.getRefForUnit(U);
Masks[R.Reg] |= R.Mask; Masks[R.Reg] |= R.Mask;
} }
Pos = End ? Masks.end() : Masks.begin(); Pos = End ? Masks.end() : Masks.begin();
Index = End ? Masks.size() : 0; Index = End ? Masks.size() : 0;
} }