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[X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class

Authored by RKSimon on Nov 22 2017, 5:26 AM.



As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with the FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general).

Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes.

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RKSimon created this revision.Nov 22 2017, 5:26 AM
gadi.haber added inline comments.Nov 26 2017, 6:31 AM
5793 ↗(On Diff #123918)

I cannot find which port WriteFMA is set to here.

It should be set to Port01 on HSW, BDW and SkylakeClient
but it should be set to Port015 on SKX

This needs to be defined in the right .td files

RKSimon updated this revision to Diff 124306.Nov 26 2017, 8:04 AM

Updated SkylakeServer to Port015 as suggested by @gadi.haber

gadi.haber accepted this revision.Nov 26 2017, 11:19 PM
This revision is now accepted and ready to land.Nov 26 2017, 11:19 PM
This revision was automatically updated to reflect the committed changes.