[X86] Add BTVER2 sched support for SHLD/SHRD

[avt77]

Summary

This patch is the first step to implement proper usage of SHLD/SHRD on Machine Combiner level. At first the patch introduces proper sched model for these 2 instructions. And at second the patch adds new schedule test specially for SHLD/SHRD.

In the next patch I'm going to introduce the selection of the best code sequence (SHLD/SHRD or alternative) based on [latency:throughput] numbers.

[RKSimon]

Please split off the SHLD/SHRD and MOV changes into two separate patches - the RET chang is far too noisy to see anything else.

[avt77]

Only SHLD/SHRD related changes were left inside the patch.

[RKSimon]

schedule-x86-64-shld.ll is superfluous - please remove it

[avt77]

In D40124#928414, @RKSimon wrote:

schedule-x86-64-shld.ll is superfluous - please remove it

In fact I use it to show and check code patterns:

shldrri <-> shl+shr+lea

or

shldrrCL <-> mov+shr+mov+sub+....

I was planning to extend it with other possible variants.
Of course if you insist I could keep it localy but from my point of view the test could be useful for others. I could remove several RUN lines and leave one or two of them only if you'd like.
Should I remove/update the test?

[avt77]

I removed schedule-x86-64-shld.ll.

[RKSimon]

lib/Target/X86/X86ScheduleBtVer2.td

154 ↗

(On Diff #123886)

Better call this WriteSHLDm - as its a RW - also add the JLAGU dependency

[RKSimon]

Also, the subject should be something like: "[X86] Add BTVER2 sched support for SHLD/SHRD"

[avt77]

Last Simon's comments were fixed.

[RKSimon]

LGTM

llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

 def : WriteRes<WriteLEA, [JALU01]>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Integer shifts and rotates.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResIntPair<WriteShift, JALU01, 1>;
 
+def WriteSHLDrri : SchedWriteRes<[JALU01]> {
+  let Latency = 3;
+  let ResourceCycles = [6];
+  let NumMicroOps = 6;
+}
+def: InstRW<[WriteSHLDrri], (instregex "SHLD(16|32|64)rri8")>;
+def: InstRW<[WriteSHLDrri], (instregex "SHRD(16|32|64)rri8")>;
+
+def WriteSHLDrrCL : SchedWriteRes<[JALU01]> {
+  let Latency = 4;
+  let ResourceCycles = [8];
+  let NumMicroOps = 7;
+}
+def: InstRW<[WriteSHLDrrCL], (instregex "SHLD(16|32|64)rrCL")>;
+def: InstRW<[WriteSHLDrrCL], (instregex "SHRD(16|32|64)rrCL")>;
+
+def WriteSHLDm : SchedWriteRes<[JLAGU, JALU01]> {
+  let Latency = 9;
+  let ResourceCycles = [1, 22];
+  let NumMicroOps = 8;
+}
+def: InstRW<[WriteSHLDm], (instregex "SHLD(16|32|64)mr(i8|CL)")>;
+def: InstRW<[WriteSHLDm], (instregex "SHRD(16|32|64)mr(i8|CL)")>;
+
 ////////////////////////////////////////////////////////////////////////////////
 // Loads, stores, and moves, not folded with other operations.
 // FIXME: Split x86 and SSE load/store/moves
 ////////////////////////////////////////////////////////////////////////////////
 
 def : WriteRes<WriteLoad,  [JLAGU]> { let Latency = 5; }
 def : WriteRes<WriteStore, [JSAGU]>;
 def : WriteRes<WriteMove,  [JAny]>;

llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll

 ; SKX-NEXT:    shldw $7, %si, (%rdx) # sched: [9:1.00]
 ; SKX-NEXT:    shrdw $7, %si, (%rdx) # sched: [9:1.00]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_shld_shrd_16:
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    shldw %cl, %si, %di # sched: [1:0.50]
-; BTVER2-NEXT:    shrdw %cl, %si, %di # sched: [1:0.50]
-; BTVER2-NEXT:    shldw %cl, %si, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shrdw %cl, %si, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shldw $7, %si, %di # sched: [1:0.50]
-; BTVER2-NEXT:    shrdw $7, %si, %di # sched: [1:0.50]
-; BTVER2-NEXT:    shldw $7, %si, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shrdw $7, %si, (%rdx) # sched: [4:1.00]
+; BTVER2-NEXT:    shldw %cl, %si, %di # sched: [4:4.00]
+; BTVER2-NEXT:    shrdw %cl, %si, %di # sched: [4:4.00]
+; BTVER2-NEXT:    shldw %cl, %si, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shrdw %cl, %si, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shldw $7, %si, %di # sched: [3:3.00]
+; BTVER2-NEXT:    shrdw $7, %si, %di # sched: [3:3.00]
+; BTVER2-NEXT:    shldw $7, %si, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shrdw $7, %si, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_shld_shrd_16:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    shldw %cl, %si, %di # sched: [100:?]
 ; ZNVER1-NEXT:    shrdw %cl, %si, %di # sched: [100:?]

 ; SKX-NEXT:    shldl $7, %esi, (%rdx) # sched: [9:1.00]
 ; SKX-NEXT:    shrdl $7, %esi, (%rdx) # sched: [9:1.00]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_shld_shrd_32:
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    shldl %cl, %esi, %edi # sched: [1:0.50]
-; BTVER2-NEXT:    shrdl %cl, %esi, %edi # sched: [1:0.50]
-; BTVER2-NEXT:    shldl %cl, %esi, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shrdl %cl, %esi, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shldl $7, %esi, %edi # sched: [1:0.50]
-; BTVER2-NEXT:    shrdl $7, %esi, %edi # sched: [1:0.50]
-; BTVER2-NEXT:    shldl $7, %esi, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shrdl $7, %esi, (%rdx) # sched: [4:1.00]
+; BTVER2-NEXT:    shldl %cl, %esi, %edi # sched: [4:4.00]
+; BTVER2-NEXT:    shrdl %cl, %esi, %edi # sched: [4:4.00]
+; BTVER2-NEXT:    shldl %cl, %esi, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shrdl %cl, %esi, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shldl $7, %esi, %edi # sched: [3:3.00]
+; BTVER2-NEXT:    shrdl $7, %esi, %edi # sched: [3:3.00]
+; BTVER2-NEXT:    shldl $7, %esi, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shrdl $7, %esi, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_shld_shrd_32:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    shldl %cl, %esi, %edi # sched: [100:?]
 ; ZNVER1-NEXT:    shrdl %cl, %esi, %edi # sched: [100:?]

 ; SKX-NEXT:    shldq $7, %rsi, (%rdx) # sched: [9:1.00]
 ; SKX-NEXT:    shrdq $7, %rsi, (%rdx) # sched: [9:1.00]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_shld_shrd_64:
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    shldq %cl, %rsi, %rdi # sched: [1:0.50]
-; BTVER2-NEXT:    shrdq %cl, %rsi, %rdi # sched: [1:0.50]
-; BTVER2-NEXT:    shldq %cl, %rsi, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shrdq %cl, %rsi, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shldq $7, %rsi, %rdi # sched: [1:0.50]
-; BTVER2-NEXT:    shrdq $7, %rsi, %rdi # sched: [1:0.50]
-; BTVER2-NEXT:    shldq $7, %rsi, (%rdx) # sched: [4:1.00]
-; BTVER2-NEXT:    shrdq $7, %rsi, (%rdx) # sched: [4:1.00]
+; BTVER2-NEXT:    shldq %cl, %rsi, %rdi # sched: [4:4.00]
+; BTVER2-NEXT:    shrdq %cl, %rsi, %rdi # sched: [4:4.00]
+; BTVER2-NEXT:    shldq %cl, %rsi, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shrdq %cl, %rsi, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shldq $7, %rsi, %rdi # sched: [3:3.00]
+; BTVER2-NEXT:    shrdq $7, %rsi, %rdi # sched: [3:3.00]
+; BTVER2-NEXT:    shldq $7, %rsi, (%rdx) # sched: [9:11.00]
+; BTVER2-NEXT:    shrdq $7, %rsi, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_shld_shrd_64:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    shldq %cl, %rsi, %rdi # sched: [100:?]
 ; ZNVER1-NEXT:    shrdq %cl, %rsi, %rdi # sched: [100:?]