[GISel][NFC]: Refactor a simple helper function to infer OpcodeDefs through copies

[aditya_nandakumar]

Summary

moved this from legalizationArtifactCombiner to GlobalISel/Utils for use elsewhere.

include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

public:
   LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
                     const LegalizerInfo &LI)
       : Builder(B), MRI(MRI), LI(LI) {}
 
   bool tryCombineAnyExt(MachineInstr &MI,
                         SmallVectorImpl<MachineInstr *> &DeadInsts) {
     if (MI.getOpcode() != TargetOpcode::G_ANYEXT)
       return false;
-    if (MachineInstr *DefMI =
-            getOpcodeDef(TargetOpcode::G_TRUNC, MI.getOperand(1).getReg())) {
+    if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
+                                           MI.getOperand(1).getReg(), MRI)) {
       DEBUG(dbgs() << ".. Combine MI: " << MI;);
       unsigned DstReg = MI.getOperand(0).getReg();
       unsigned SrcReg = DefMI->getOperand(1).getReg();
       Builder.setInstr(MI);
       // We get a copy/trunc/extend depending on the sizes
       Builder.buildAnyExtOrTrunc(DstReg, SrcReg);
       markInstAndDefDead(MI, *DefMI, DeadInsts);
       return true;
     }
     return tryFoldImplicitDef(MI, DeadInsts);
   }
 
   bool tryCombineZExt(MachineInstr &MI,
                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
 
     if (MI.getOpcode() != TargetOpcode::G_ZEXT)
       return false;
-    if (MachineInstr *DefMI =
-            getOpcodeDef(TargetOpcode::G_TRUNC, MI.getOperand(1).getReg())) {
+    if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
+                                           MI.getOperand(1).getReg(), MRI)) {
       unsigned DstReg = MI.getOperand(0).getReg();
       LLT DstTy = MRI.getType(DstReg);
       if (isInstUnsupported(TargetOpcode::G_AND, DstTy) ||
           isInstUnsupported(TargetOpcode::G_CONSTANT, DstTy))
         return false;
       DEBUG(dbgs() << ".. Combine MI: " << MI;);
       Builder.setInstr(MI);
       unsigned ZExtSrc = MI.getOperand(1).getReg();
bool tryCombineZExt(MachineInstr &MI,
     return tryFoldImplicitDef(MI, DeadInsts);
   }
 
   bool tryCombineSExt(MachineInstr &MI,
                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
 
     if (MI.getOpcode() != TargetOpcode::G_SEXT)
       return false;
-    if (MachineInstr *DefMI =
-            getOpcodeDef(TargetOpcode::G_TRUNC, MI.getOperand(1).getReg())) {
+    if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
+                                           MI.getOperand(1).getReg(), MRI)) {
       unsigned DstReg = MI.getOperand(0).getReg();
       LLT DstTy = MRI.getType(DstReg);
       if (isInstUnsupported(TargetOpcode::G_SHL, DstTy) ||
           isInstUnsupported(TargetOpcode::G_ASHR, DstTy) ||
           isInstUnsupported(TargetOpcode::G_CONSTANT, DstTy))
         return false;
       DEBUG(dbgs() << ".. Combine MI: " << MI;);
       Builder.setInstr(MI);
public:
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts) {
     unsigned Opcode = MI.getOpcode();
     if (Opcode != TargetOpcode::G_ANYEXT && Opcode != TargetOpcode::G_ZEXT &&
         Opcode != TargetOpcode::G_SEXT)
       return false;
 
     if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
-                                           MI.getOperand(1).getReg())) {
+                                           MI.getOperand(1).getReg(), MRI)) {
       unsigned DstReg = MI.getOperand(0).getReg();
       LLT DstTy = MRI.getType(DstReg);
       if (isInstUnsupported(TargetOpcode::G_IMPLICIT_DEF, DstTy))
         return false;
       DEBUG(dbgs() << ".. Combine EXT(IMPLICIT_DEF) " << MI;);
       Builder.setInstr(MI);
       Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, DstReg);
       markInstAndDefDead(MI, *DefMI, DeadInsts);
private:
   }
   /// Checks if the target legalizer info has specified anything about the
   /// instruction, or if unsupported.
   bool isInstUnsupported(unsigned Opcode, const LLT &DstTy) const {
     auto Action = LI.getAction({Opcode, 0, DstTy});
     return Action.first == LegalizerInfo::LegalizeAction::Unsupported ||
            Action.first == LegalizerInfo::LegalizeAction::NotFound;
   }
-  /// See if Reg is defined by an single def instruction that is
-  /// Opcode. Also try to do trivial folding if it's a COPY with
-  /// same types. Returns null otherwise.
-  MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg) {
-    auto *DefMI = MRI.getVRegDef(Reg);
-    auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
-    if (!DstTy.isValid())
-      return nullptr;
-    while (DefMI->getOpcode() == TargetOpcode::COPY) {
-      unsigned SrcReg = DefMI->getOperand(1).getReg();
-      auto SrcTy = MRI.getType(SrcReg);
-      if (!SrcTy.isValid() || SrcTy != DstTy)
-        break;
-      DefMI = MRI.getVRegDef(SrcReg);
-    }
-    return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
-  }
 };
 
 } // namespace llvm

include/llvm/CodeGen/GlobalISel/Utils.h

void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
                         const char *PassName, StringRef Msg,
                         const MachineInstr &MI);
 
 Optional<int64_t> getConstantVRegVal(unsigned VReg,
                                      const MachineRegisterInfo &MRI);
 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
                                        const MachineRegisterInfo &MRI);
 
+/// See if Reg is defined by an single def instruction that is
+/// Opcode. Also try to do trivial folding if it's a COPY with
+/// same types. Returns null otherwise.
+MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg,
+                           const MachineRegisterInfo &MRI);
+
 } // End namespace llvm.
 #endif

lib/CodeGen/GlobalISel/Utils.cpp

 
 const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
                                        const MachineRegisterInfo &MRI) {
   MachineInstr *MI = MRI.getVRegDef(VReg);
   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
     return nullptr;
   return MI->getOperand(1).getFPImm();
 }
+
+llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
+                                       const MachineRegisterInfo &MRI) {
+  auto *DefMI = MRI.getVRegDef(Reg);
+  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
+  if (!DstTy.isValid())
+    return nullptr;
+  while (DefMI->getOpcode() == TargetOpcode::COPY) {
+    unsigned SrcReg = DefMI->getOperand(1).getReg();
+    auto SrcTy = MRI.getType(SrcReg);
+    if (!SrcTy.isValid() || SrcTy != DstTy)
+      break;
+    DefMI = MRI.getVRegDef(SrcReg);
+  }
+  return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
+}