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[DAGCombine] Enable more srl + load combines
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Authored by samparker on Nov 14 2017, 9:18 AM.

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Summary

Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as:

(srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1])

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Event Timeline

samparker created this revision.Nov 14 2017, 9:18 AM

Hi Sam, that's a very nice optimisation, but I think we need more tests. The "variables" that we have here are the values types (load byte, load half, load word), and the different possible offsets. Guessing a bit here, but that must be something like 3 * 3(?) = 9 tests.
And another question is how this interacts with -munaligned-access and -mno-unaligned-access?

Hi Sjoerd,

Yes I agree, more tests would be good. I've added V6-M to test whether no unaligned accesses are permitted, but admittedly that is for only one of the test cases. So I will add some more tests for different byte positions and some more for no unaligned accesses.

Many thanks!
sam

samparker updated this revision to Diff 123002.Nov 15 2017, 4:53 AM

Increased the number of tests by adding different shift values, plus I've added a +strict-align target.

SjoerdMeijer accepted this revision.Nov 16 2017, 12:58 AM

Looks good to me.

This revision is now accepted and ready to land.Nov 16 2017, 12:58 AM
This revision was automatically updated to reflect the committed changes.