[ARM GlobalISel] Fix call opcode for Thumb

[javed.absar]

Summary

Fixing call opcodes for Thumb.
Review https://reviews.llvm.org/D39592 (Adding legalizer for Thumb) is gated on this patch.

Currently this patch is not complete, and running the test causes assertion failure
"Assertion `RC && RC->isAllocatable() && "Invalid RC for virtual register", so it seems to missing something.
But putting it up to get early feedback if the direction is ok.

[javed.absar]

Gentle reminder.

[rovka]

lib/Target/ARM/ARMCallLowering.cpp

424

This isn't correct, you're returning true as if you had lowered the arguments, but you actually haven't done anything with them. You should remove this check altogether.

test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll

1

Typo: DIRECT

Anyway, the "direct" is a property of the code snippet, not of the command line used to run it, so I'm not sure you should include it in the name of the checks. I think what you want here is actually ARM-NOV4T. Similarly below, you can have ARM-V5T and THUMB-V5T.

5

You should also test for thumb + v4t.

30

The CALL-THUMB check seems wrong.

lib/Target/ARM/ARMCallLowering.cpp

 
 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
                                            const Function &F,
                                            ArrayRef<unsigned> VRegs) const {
   auto &TLI = *getTLI<ARMTargetLowering>();
   auto Subtarget = TLI.getSubtarget();
 
   if (Subtarget->isThumb())
-    return false;
+    return true;
 
   // Quick exit if there aren't any args
   if (F.arg_empty())
     return true;
 
   if (F.isVarArg())
     return false;
 
if (STI.genLongCalls())
     return false;
 
   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
 
   // Create the call instruction so we can add the implicit uses of arg
   // registers, but don't insert it yet.
   bool isDirect = !Callee.isReg();
   auto CallOpcode =
-      isDirect ? ARM::BL
+      STI.isThumb() ? (isDirect ? ARM::tBL : ARM::tBLXr)
+                    : (isDirect ? ARM::BL
                                 : STI.hasV5TOps()
                                       ? ARM::BLX
-                     : STI.hasV4TOps() ? ARM::BX_CALL : ARM::BMOVPCRX_CALL;
+                                      : STI.hasV4TOps() ? ARM::BX_CALL
+                                                        : ARM::BMOVPCRX_CALL);
+
   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode)
                  .add(Callee)
                  .addRegMask(TRI->getCallPreservedMask(MF, CallConv));
   if (Callee.isReg()) {
     auto CalleeReg = Callee.getReg();
     if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg))
       MIB->getOperand(0).setReg(constrainOperandRegClass(
           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),

test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll

-; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T
-; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T
-; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T
+; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,DIREC-CALL-ARM,NOV4T
+; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,DIREC-CALL-ARM,V4T
+; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T,DIREC-CALL-ARM,V5T-CALL-ARM
+
+; RUN: llc -mtriple thumb-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T,DIRECT-CALL-THUMB,V5T-CALL-THUMB
 
 define arm_aapcscc void @test_indirect_call(void() *%fptr) {
 ; CHECK-LABEL: name: test_indirect_call
 ; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
 ; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
 ; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
-; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
+; V5T-CALL-ARM:    BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
+; V5T-CALL-THUMB: tBLXr %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
 ; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
 ; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
 entry:
   notail call arm_aapcscc void %fptr()
   ret void
 }
 
 declare arm_aapcscc void @call_target()
 
 define arm_aapcscc void @test_direct_call() {
 ; CHECK-LABEL: name: test_direct_call
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
+; DIRECT-CALL-ARM:    BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
+; DIRECT-CALL-THUMB: tBL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
+; CALL-THUMB: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
 entry:
   notail call arm_aapcscc void @call_target()
   ret void
 }