[AVX512] Adding support for load truncate store of I1

[m_zuckerman]

Summary

store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion.
This patch fixes this issue.

[igorb]

lib/Target/X86/X86ISelLowering.cpp

1228

could you please explain why you set custom in case DQI & AVX512 & VL & BWI and not for AVX512

test/CodeGen/X86/avx512-load-trunc-store-i1.ll

5

Is it possible to create tests that test SELECT only

[igorb]

LGTM

lib/Target/X86/X86ISelLowering.cpp

if (Subtarget.hasVLX()){
       setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
     } else {
       for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
            MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
         setOperationAction(ISD::MLOAD,  VT, Custom);
         setOperationAction(ISD::MSTORE, VT, Custom);
       }
     }
+    if (Subtarget.hasDQI() && Subtarget.hasVLX() && Subtarget.hasAVX512() &&
+        Subtarget.hasBWI())
+        setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
 
     if (Subtarget.hasDQI()) {
       for (auto VT : { MVT::v2i64, MVT::v4i64, MVT::v8i64 }) {
         setOperationAction(ISD::SINT_TO_FP,     VT, Legal);
         setOperationAction(ISD::UINT_TO_FP,     VT, Legal);
         setOperationAction(ISD::FP_TO_SINT,     VT, Legal);
         setOperationAction(ISD::FP_TO_UINT,     VT, Legal);
       }
if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
       Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
     else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
       Op2Scalar = Op2.getOperand(0);
     if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
       SDValue newSelect = DAG.getSelect(DL, Op1Scalar.getValueType(), Cond,
                                         Op1Scalar, Op2Scalar);
       if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
         return DAG.getBitcast(VT, newSelect);
+
+      if(Subtarget.hasAVX512() && Subtarget.hasVLX() && Subtarget.hasBWI() &&
+         Subtarget.hasDQI())
+        return newSelect;
+
       SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
       return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
                          DAG.getIntPtrConstant(0, DL));
     }
   }
 
   if (VT == MVT::v4i1 || VT == MVT::v2i1) {
     SDValue zeroConst = DAG.getIntPtrConstant(0, DL);

test/CodeGen/X86/avx512-load-trunc-store-i1.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -O2 | FileCheck %s --check-prefix=AVX512
+
+
+define void @load_v1i2_trunc_v1i1_store(<1 x i2>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i2_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    movb (%rdi), %al
+; AVX512-NEXT:    testb %al, %al
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i2>, <1 x i2>* %a0
+    %d1 = trunc <1 x i2> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+define void @load_v1i3_trunc_v1i1_store(<1 x i3>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i3_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    movb (%rdi), %al
+; AVX512-NEXT:    testb %al, %al
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i3>, <1 x i3>* %a0
+    %d1 = trunc <1 x i3> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+define void @load_v1i4_trunc_v1i1_store(<1 x i4>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i4_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    movb (%rdi), %al
+; AVX512-NEXT:    testb %al, %al
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i4>, <1 x i4>* %a0
+    %d1 = trunc <1 x i4> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+define void @load_v1i8_trunc_v1i1_store(<1 x i8>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i8_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    cmpb $0, (%rdi)
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i8>, <1 x i8>* %a0
+    %d1 = trunc <1 x i8> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+define void @load_v1i16_trunc_v1i1_store(<1 x i16>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i16_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    cmpb $0, (%rdi)
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i16>, <1 x i16>* %a0
+    %d1 = trunc <1 x i16> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+define void @load_v1i32_trunc_v1i1_store(<1 x i32>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i32_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    cmpb $0, (%rdi)
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i32>, <1 x i32>* %a0
+    %d1 = trunc <1 x i32> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+define void @load_v1i64_trunc_v1i1_store(<1 x i64>* %a0,<1 x i1>* %a1) {
+; AVX512-LABEL: load_v1i64_trunc_v1i1_store:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    cmpb $0, (%rdi)
+; AVX512-NEXT:    setne (%rsi)
+; AVX512-NEXT:    retq
+    %d0 = load <1 x i64>, <1 x i64>* %a0
+    %d1 = trunc <1 x i64> %d0 to <1 x i1>
+    store <1 x i1> %d1, <1 x i1>* %a1
+    ret void
+}
+