[mips] Provide alternate predicates for constant synthesis

[smaksimovic]

Summary

Ordering of patterns should not be of importance anymore since the predicates used are mutually exclusive now.

[smaksimovic]

We could, in addition to the new predicates, reorder the patterns which use them resulting in exposure of the underlying dependence of the order the patterns are laid out.
I stuck with Val & 0xfff instead of suggested isUInt<16>(Val) since it seems that it behaves differently.

[sdardis]

Some quick inlined comments.

Can you provide a test case where you check the various edge values and use a combination of CHECK and CHECK-NOT to assert that the ISel is picking the expected instructions?

E.g.

define i32 @ret_zero() {
  CHECK-MIPS:     addiu $2, $zero, 0
  CHECK-MIPS-NOT: lui
  CHECK-MIPS-NOT: ori
  CHECK-MIPS-NOT: li16
 
  ret i32 0
}

The goal of the test case is to document what's "canonical" for us in terms of constant materialisation or at least the current behaviour.

lib/Target/Mips/MicroMipsInstrInfo.td

1009–1015

Use AdditionalPredicates with a scope to cover both the def and multidef.

1018–1023

Delete these patterns, they are covered by the MaterializeImms multiclass and the explict pattern for LI16_MM above.

lib/Target/Mips/MipsInstrInfo.td

2736–2744

Your suggestion for reordering the predicates is a good one, can you invert the order and add a comment saying why they are in an unusual order?

[smaksimovic]

Addressed review comments.

[sdardis]

LGTM with inline nits addressed.

lib/Target/Mips/MipsInstrInfo.td

1836–1851

These should go in the block of other leaf patterns starting at 1155.

1839–1840

You can return the result of isUInt<16>(ZVal) && !isInt<16> directly, as isUInt<16> already tests

return static_cast<int16_t>(x) == x;

See include/llvm/Support/MathExtras.h

test/CodeGen/Mips/constMaterialization.ll

3 ↗

(On Diff #118789)

Add a comment here explaining that this test documents/tests the patterns used for constant materialization.

7 ↗

(On Diff #118789)

This check line needs to be indented to the same level as the check lines below. This applies to the rest of the functions in this test.

35 ↗

(On Diff #118789)

This should be ALL.

75 ↗

(On Diff #118789)

Stray whitespace here and in the rest of the functions at the same location.

90 ↗

(On Diff #118789)

Check that a negative number that doesn't have the lower 16 bits is synthesized with a single lui.

[smaksimovic]

Nits addressed.

lib/Target/Mips/MicroMipsInstrInfo.td

def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
                              mem_simm12>, LL_FM_MM<0xe>,
                ISA_MICROMIPS32_NOT_MIPS32R6;
 }
 
 //===----------------------------------------------------------------------===//
 // MicroMips arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [InMicroMips] in {
   def : MipsPat<(i32 immLi16:$imm),
                 (LI16_MM immLi16:$imm)>;
+}
 
 let AdditionalPredicates = [InMicroMips] in
 defm :  MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>;
 
 let Predicates = [InMicroMips] in {
   def : MipsPat<(i32 immLi16:$imm),
                 (LI16_MM immLi16:$imm)>;
   def : MipsPat<(i32 immSExt16:$imm),
                 (ADDiu_MM ZERO, immSExt16:$imm)>;
   def : MipsPat<(i32 immZExt16:$imm),
                 (ORi_MM ZERO, immZExt16:$imm)>;
 
   def : MipsPat<(not GPRMM16:$in),
                 (NOT16_MM GPRMM16:$in)>;
   def : MipsPat<(not GPR32:$in),
                 (NOR_MM GPR32Opnd:$in, ZERO)>;
 
   def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
                 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;

lib/Target/Mips/MipsInstrInfo.td

 // Expands to: lui $dst, %hi($tgt - $baltgt)
 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
   (ins brtarget:$tgt, brtarget:$baltgt), []>;
 
 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
   (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
 
+def ORiPred  : PatLeaf<(imm), [{
+  uint64_t ZVal = N->getZExtValue();
+  int64_t SVal = N->getSExtValue();
+  bool cond =  isUInt<16>(ZVal) && !isInt<16>(SVal);
+  return (uint32_t)ZVal == (unsigned short)ZVal && cond;
+}], LO16>;
+
+def LUiPred : PatLeaf<(imm), [{
+  int64_t Val = N->getSExtValue();
+  return !isInt<16>(Val) && isInt<32>(Val) && !(Val & 0xffff);
+}]>;
+
+def LUiORiPred  : PatLeaf<(imm), [{
+  int64_t SVal = N->getSExtValue();
+  return isInt<32>(SVal) && (SVal & 0xffff);
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction definition
 //===----------------------------------------------------------------------===//
 //===----------------------------------------------------------------------===//
 // MipsI Instructions
 //===----------------------------------------------------------------------===//
 
 /// Arithmetic Instructions (ALU Immediate)

 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
   MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
 
 // Materialize constants.
 multiclass MaterializeImms<ValueType VT, Register ZEROReg,
                            Instruction ADDiuOp, Instruction LUiOp,
                            Instruction ORiOp> {
 
 // Small immediates
 def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>;
-def : MipsPat<(VT immZExt16:$imm), (ORiOp ZEROReg, imm:$imm)>;
+def : MipsPat<(VT ORiPred:$imm), (ORiOp ZEROReg, imm:$imm)>;
 
 // Bits 32-16 set, sign/zero extended.
-def : MipsPat<(VT immSExt32Low16Zero:$imm), (LUiOp (HI16 imm:$imm))>;
+def : MipsPat<(VT LUiPred:$imm), (LUiOp (HI16 imm:$imm))>;
 
 // Arbitrary immediates
-def : MipsPat<(VT immSExt32:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
+def : MipsPat<(VT LUiORiPred:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
 }
 
 let AdditionalPredicates = [NotInMicroMips] in
   defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>;
 
 // Carry MipsPatterns
 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),