AMDGPU: Expand setcc for v2i32 and v4i32

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

186–188 ↗

(On Diff #117543)

Not sure how this could have been missing. Is f32 also broken?

This should go in the vector loops in AMDGPUISelLowering with the other v2i32/v4i32 operations

[kzhuravl]

Address review feedback.

lib/Target/AMDGPU/SIISelLowering.cpp

186–188 ↗

(On Diff #117543)

I do not think f32 is broken.

[arsenm]

LGTM. It shouldn't be any different for the f32 vectors.

assert(isOperationExpand(ISD::SETCC, MVT::v2f32));

fails, so it should probably be added to the FP vector loop also even if you can't find a testcase for it.

[kzhuravl]

rL314852, rL314853.

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

for (MVT VT : VectorIntTypes) {
     setOperationAction(ISD::VSELECT, VT, Expand);
     setOperationAction(ISD::SELECT_CC, VT, Expand);
     setOperationAction(ISD::XOR,  VT, Expand);
     setOperationAction(ISD::BSWAP, VT, Expand);
     setOperationAction(ISD::CTPOP, VT, Expand);
     setOperationAction(ISD::CTTZ, VT, Expand);
     setOperationAction(ISD::CTLZ, VT, Expand);
     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
+    setOperationAction(ISD::SETCC, VT, Expand);
   }
 
   static const MVT::SimpleValueType FloatVectorTypes[] = {
     MVT::v2f32, MVT::v4f32
   };
 
   for (MVT VT : FloatVectorTypes) {
     setOperationAction(ISD::FABS, VT, Expand);

test/CodeGen/AMDGPU/setcc.ll

 bb1:
   store i32 0, i32 addrspace(1)* %out
   br label %bb2
 
 bb2:
   ret void
 }
 
+; FUNC-LABEL: setcc_v2i32_expand
+; GCN: v_cmp_gt_i32
+; GCN: v_cmp_gt_i32
+define amdgpu_kernel void @setcc_v2i32_expand(
+  <2 x i32> addrspace(1)* %a,
+  <2 x i32> addrspace(1)* %b,
+  <2 x i32> addrspace(1)* %c,
+  <2 x float> addrspace(1)* %r) {
+entry:
+  %a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a
+  %b.val = load <2 x i32>, <2 x i32> addrspace(1)* %b
+  %c.val = load <2 x i32>, <2 x i32> addrspace(1)* %c
+
+  %icmp.val.1 = icmp sgt <2 x i32> %a.val, <i32 1, i32 1>
+  %zext.val.1 = zext <2 x i1> %icmp.val.1 to <2 x i32>
+  %shl.val.1 = shl nuw <2 x i32> %zext.val.1, <i32 31, i32 31>
+  %xor.val.1 = xor <2 x i32> %shl.val.1, %b.val
+  %bitcast.val.1 = bitcast <2 x i32> %xor.val.1 to <2 x float>
+  %icmp.val.2 = icmp sgt <2 x i32> %c.val, <i32 1199570944, i32 1199570944>
+  %select.val.1 = select <2 x i1> %icmp.val.2, <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> %bitcast.val.1
+
+  store <2 x float> %select.val.1, <2 x float> addrspace(1)* %r
+  ret void
+}
+
+; FUNC-LABEL: setcc_v4i32_expand
+; GCN: v_cmp_gt_i32
+; GCN: v_cmp_gt_i32
+; GCN: v_cmp_gt_i32
+; GCN: v_cmp_gt_i32
+define amdgpu_kernel void @setcc_v4i32_expand(
+  <4 x i32> addrspace(1)* %a,
+  <4 x i32> addrspace(1)* %b,
+  <4 x i32> addrspace(1)* %c,
+  <4 x float> addrspace(1)* %r) {
+entry:
+  %a.val = load <4 x i32>, <4 x i32> addrspace(1)* %a
+  %b.val = load <4 x i32>, <4 x i32> addrspace(1)* %b
+  %c.val = load <4 x i32>, <4 x i32> addrspace(1)* %c
+
+  %icmp.val.1 = icmp sgt <4 x i32> %a.val, <i32 1, i32 1, i32 1, i32 1>
+  %zext.val.1 = zext <4 x i1> %icmp.val.1 to <4 x i32>
+  %shl.val.1 = shl nuw <4 x i32> %zext.val.1, <i32 31, i32 31, i32 31, i32 31>
+  %xor.val.1 = xor <4 x i32> %shl.val.1, %b.val
+  %bitcast.val.1 = bitcast <4 x i32> %xor.val.1 to <4 x float>
+  %icmp.val.2 = icmp sgt <4 x i32> %c.val, <i32 1199570944, i32 1199570944, i32 1199570944, i32 1199570944>
+  %select.val.1 = select <4 x i1> %icmp.val.2, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %bitcast.val.1
+
+  store <4 x float> %select.val.1, <4 x float> addrspace(1)* %r
+  ret void
+}
+
 attributes #0 = { nounwind }