[mips] Place certain 64 bit FPU instructions in their own decoder namespace

[sdardis]

Summary

Previously, instructions that were defined to use the FGR64 register class
were associated with the Mips64 table which was incorrect.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

if (IsMicroMips) {
     // Calling the auto-generated decoder function.
     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
                                this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
 
-    if (hasMips32r6() && isFP64()) {
-      DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
-      Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn,
+    if (isFP64()) {
+      DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
+      Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
                                  Address, this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 4;
         return Result;
       }
     }
 
     // This is an invalid instruction. Claim that the Size is 2 bytes. Since
DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   if (isGP64()) {
     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
                                Address, this, STI);
     if (Result != MCDisassembler::Fail)
       return Result;
   }
 
+  if (isFP64()) {
+    DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
+    Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
+                               Address, this, STI);
+    if (Result != MCDisassembler::Fail)
+      return Result;
+  }
+
   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
   // Calling the auto-generated decoder function.
   Result =
       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
   if (Result != MCDisassembler::Fail)
     return Result;
 
   return MCDisassembler::Fail;

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6;
 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
 def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
 def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
 def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
+let DecoderNamespace = "MicroMipsFP64" in {
   def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
                        ISA_MICROMIPS32R6;
 }
 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
 def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC,
                      ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
+let DecoderNamespace = "MicroMipsFP64" in {
   def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC,
                        ISA_MICROMIPS32R6;
 }
 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;

 def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
                    ISA_MICROMIPS32R6;
 def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
                    ISA_MICROMIPS32R6;
 def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
                    ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
+let DecoderNamespace = "MicroMipsFP64" in {
   def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
                       ISA_MICROMIPS32R6 {
     let BaseOpcode = "LDC164";
   }
   def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
                       ISA_MICROMIPS32R6;
 }
 def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;

llvm/trunk/lib/Target/Mips/MipsCondMov.td

 
 def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
                                     II_MOVZ_D>, CMov_I_F_FM<18, 17>,
                  INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
                                     II_MOVN_D>, CMov_I_F_FM<19, 17>,
                  INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
 
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
   def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
                    CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
                    CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   let isCodeGenOnly = 1 in {
     def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
                        CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
     def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,

 
 def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
                                   MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
                INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
 def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
                                   MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
                INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
 
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
   def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
                  CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
                  CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
 }
 
 // Instantiation of conditional move patterns.
 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
   HARDFLOAT {
   let isCommutable = IsComm;
 }
 
 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
                   SDPatternOperator OpNode = null_frag> {
   def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
   def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
-    string DecoderNamespace = "Mips64";
+    string DecoderNamespace = "MipsFP64";
   }
 }
 
 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
               InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
   InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
          [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
   HARDFLOAT,
   NeverHasSideEffects;
 
 multiclass ABSS_M<string opstr, InstrItinClass Itin,
                   SDPatternOperator OpNode= null_frag> {
   def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
              FGR_32;
   def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
-    string DecoderNamespace = "Mips64";
+    string DecoderNamespace = "MipsFP64";
   }
 }
 
 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
   def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
   def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
-    let DecoderNamespace = "Mips64";
+    let DecoderNamespace = "MipsFP64";
   }
 }
 
 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
               InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
   InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
          [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
 
def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
     let BaseOpcode = "c.ngt."#NAME;
   }
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
            FGR_32;
-let DecoderNamespace = "Mips64" in
+let DecoderNamespace = "MipsFP64" in
 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
            FGR_64;
 }
 //===----------------------------------------------------------------------===//
 // Floating Point Instructions
 //===----------------------------------------------------------------------===//
 def ROUND_W_S  : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
                  ABSS_FM<0xc, 16>, ISA_MIPS2;
def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
                 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
   def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
                 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
   def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
                 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
   def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
                 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
 }
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
   let AdditionalPredicates = [NotInMicroMips] in {
   def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
                   ABSS_FM<0x8, 16>, FGR_64;
   def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
                     ABSS_FM<0x8, 17>, FGR_64;
   def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
                   ABSS_FM<0x9, 16>, FGR_64;
   def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,

 
 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
                 ABSS_FM<0x20, 17>, FGR_32;
 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
                 ABSS_FM<0x21, 20>, FGR_32;
 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
                 ABSS_FM<0x21, 16>, FGR_32;
 
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
   def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
                   ABSS_FM<0x20, 17>, FGR_64;
   let AdditionalPredicates = [NotInMicroMips] in{
     def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
                     ABSS_FM<0x20, 21>, FGR_64;
   }
   def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
                   ABSS_FM<0x21, 20>, FGR_64;

 let AdditionalPredicates = [NotInMicroMips] in {
   def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
   def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
 }
 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
                           bitconvert>, MFC1_FM<0>;
 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
                FGR_64 {
-  let DecoderNamespace = "Mips64";
+  let DecoderNamespace = "MipsFP64";
 }
 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
                           bitconvert>, MFC1_FM<4>;
 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
                FGR_64 {
-  let DecoderNamespace = "Mips64";
+  let DecoderNamespace = "MipsFP64";
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
                   MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
   def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
                   MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
-    let DecoderNamespace = "Mips64";
+    let DecoderNamespace = "MipsFP64";
   }
 }
 let AdditionalPredicates = [NotInMicroMips] in {
   def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
                   MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
   def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
                   MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
-    let DecoderNamespace = "Mips64";
+    let DecoderNamespace = "MipsFP64";
   }
 }
 let AdditionalPredicates = [NotInMicroMips] in {
   def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
               bitconvert>, MFC1_FM<5>, ISA_MIPS3;
   def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
                       bitconvert>, MFC1_FM<1>, ISA_MIPS3;
 }
 
 def FMOV_S   : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
                ABSS_FM<0x6, 16>;
 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
                ABSS_FM<0x6, 17>, FGR_32;
 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
                ABSS_FM<0x6, 17>, FGR_64 {
-                 let DecoderNamespace = "Mips64";
+                 let DecoderNamespace = "MipsFP64";
 }
 
 /// Floating Point Memory Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
   def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
              LW_FM<0x31>;
   def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
              LW_FM<0x39>;
 }
 
-let DecoderNamespace = "Mips64", AdditionalPredicates = [NotInMicroMips] in {
+let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
   def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
                LW_FM<0x35>, ISA_MIPS2, FGR_64 {
     let BaseOpcode = "LDC164";
   }
   def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
                LW_FM<0x3d>, ISA_MIPS2, FGR_64;
 }
 

 
 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
   def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
               INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
   def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
               INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
 }
 
-let DecoderNamespace="Mips64" in {
+let DecoderNamespace="MipsFP64" in {
   def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
                 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
   def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
                 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
 }
 
 // Load/store doubleword indexed unaligned.
+// FIXME: This instruction should not be defined for FGR_32.
 let AdditionalPredicates = [IsNotNaCl] in {
   def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
               INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
   def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
               INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
 }
 
-let DecoderNamespace="Mips64" in {
+let DecoderNamespace="MipsFP64" in {
   def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
                 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
   def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
                 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
 }
 
 /// Floating-point Aritmetic
 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,

 
 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
   def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
                   MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
   def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
                   MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
 }
 
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
   def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
                  MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
   def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
                  MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
 }
 
 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
-    DecoderNamespace = "Mips64" in {
+    DecoderNamespace = "MipsFP64" in {
   def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
                   MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
   def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
                   MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
 }
 
 //===----------------------------------------------------------------------===//
 // Floating Point Branch Codes
let AdditionalPredicates = [NotInMicroMips] in {
   def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
                  ISA_MIPS1_NOT_32R6_64R6, FGR_32 {
   // FIXME: This is a required to work around the fact that these instructions
   //        only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
   //        fcc register set is used directly.
   bits<3> fcc = 0;
   }
 }
-let DecoderNamespace = "Mips64" in
+let DecoderNamespace = "MipsFP64" in
 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
                ISA_MIPS1_NOT_32R6_64R6, FGR_64 {
   // FIXME: This is a required to work around the fact that thiese instructions
   //        only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
   //        fcc register set is used directly.
   bits<3> fcc = 0;
 }
 

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s
 # Try a mips64* triple to confirm that mips* vs mips64* triples no longer have
 # an effect on the disassembler behaviour.
 # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips32r2 | FileCheck %s
 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
 0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s
 # Try a mips64* triple to confirm that mips* vs mips64* triples no longer have
 # an effect on the disassembler behaviour.
 # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r2 | FileCheck %s
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x00 0x00 0x00 0x09 # CHECK: jr $zero
 0x00 0x00 0x00 0x0c # CHECK: syscall                         
 0x00 0x00 0x00 0x0d # CHECK: break
 0x00 0x00 0x00 0x0f # CHECK: sync                            

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r3 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r3 -mattr=+fp64 | FileCheck %s
 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
 0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
 0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
 0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
 0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 -mattr=+fp64 | FileCheck %s
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x00 0x00 0x00 0x09 # CHECK: jr $zero
 0x00 0x00 0x00 0x0c # CHECK: syscall                         
 0x00 0x00 0x00 0x0d # CHECK: break
 0x00 0x00 0x00 0x0f # CHECK: sync                            
 0x00 0x00 0x00 0x20 # CHECK: add $zero, $zero, $zero
 0x00 0x00 0x00 0x40 # CHECK: ssnop
 0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r5 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r5 -mattr=+fp64 | FileCheck %s
 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
 0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
 0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
 0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
 0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 -mattr=+fp64 | FileCheck %s
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x00 0x00 0x00 0x09 # CHECK: jr $zero
 0x00 0x00 0x00 0x0c # CHECK: syscall                         
 0x00 0x00 0x00 0x0d # CHECK: break
 0x00 0x00 0x00 0x0f # CHECK: sync                            
 0x00 0x00 0x00 0x20 # CHECK: add $zero, $zero, $zero
 0x00 0x00 0x00 0x40 # CHECK: ssnop
 0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2