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[X86][SKX] Adding the scheduling information for the SKX target.

Authored by gadi.haber on Oct 1 2017, 3:15 AM.



Adding the scheduling information for the SkylakeServer (SKX) target.

This patch adds the instruction scheduling information for the SkylakeServer (SKX) architecture target by adding the file located under the X86 Target.
We used the scheduling information retrieved from the Skylake architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction.

The patch continues the scheduling replacement and insertion effort started with the SNB target in r310792, the HSW target in r311879 and the SkylakeClient (SKL) target in rL313613.

Please expect some performance fluctuations due to code alignment effects.

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gadi.haber created this revision.Oct 1 2017, 3:15 AM
gadi.haber edited the summary of this revision. (Show Details)
RKSimon edited edge metadata.Oct 1 2017, 5:38 AM

How come the skylake SERVER model has gone back to including load latency while for the CLIENT model Intel said it was irrelevant?

By the looks of it we need to add KNL/SKX testing on many of the existing *-schedule.ll tests to get better coverage

Good point. We had multiple rounds of checks and it seems that indeed some (not all) of the memory instructions do need to include additional latency based on whether they are load of an address or data, load of 128 or 256 or 512 bits vector, load and store and store alone.
I intend to go back and fix it for the Skylake Client and for Haswell.

I've added more SKX cpu scheduler tests at rL315061 - please can you rebase?

gadi.haber updated this revision to Diff 118152.Oct 8 2017, 1:09 AM

Updated diff file after rebase,

RKSimon accepted this revision.Oct 8 2017, 3:39 AM


This revision is now accepted and ready to land.Oct 8 2017, 3:39 AM
This revision was automatically updated to reflect the committed changes.