[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem

[craig.topper]

Summary

Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.

For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.

I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995.

[craig.topper]

Looks like objdump also prints the memory on the right in at&t syntax. So this makes our disassembler printing consistent

465e9c:»85 6c 24 58          »test   %ebp,0x58(%rsp)

[aymanmus]

LGTM

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

unsigned FixupKind = [=]() {
       switch (Opcode) {
       default:
         return X86::reloc_riprel_4byte;
       case X86::MOV64rm:
         assert(Rex);
         return X86::reloc_riprel_4byte_movq_load;
       case X86::CALL64m:
       case X86::JMP64m:
-      case X86::TEST64rm:
+      case X86::TEST64mr:
       case X86::ADC64rm:
       case X86::ADD64rm:
       case X86::AND64rm:
       case X86::CMP64rm:
       case X86::OR64rm:
       case X86::SBB64rm:
       case X86::SUB64rm:
       case X86::XOR64rm:

lib/Target/X86/X86InstrArithmetic.td

class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
 
   // Infer instruction prefixes from type info.
   let OpSize = typeinfo.OpSize;
   let hasREX_WPrefix  = typeinfo.HasREX_WPrefix;
 }
 
 // BinOpRR - Instructions like "add reg, reg, reg".
 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-              dag outlist, list<dag> pattern, InstrItinClass itin,
-              Format f = MRMDestReg>
-  : ITy<opcode, f, typeinfo, outlist,
+              dag outlist, list<dag> pattern, InstrItinClass itin>
+  : ITy<opcode, MRMDestReg, typeinfo, outlist,
         (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
         mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
     Sched<[WriteALU]>;
 
 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
 // just a EFLAGS as a result.
 class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-                SDPatternOperator opnode, Format f = MRMDestReg>
+                SDPatternOperator opnode>
   : BinOpRR<opcode, mnemonic, typeinfo, (outs),
             [(set EFLAGS,
                   (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
-            IIC_BIN_NONMEM, f>;
+            IIC_BIN_NONMEM>;
 
 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
 // both a regclass and EFLAGS as a result.
 class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
                  SDNode opnode>
   : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
             [(set typeinfo.RegClass:$dst, EFLAGS,
                   (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
               InstrItinClass itin = IIC_BIN_MEM>
   : ITy<opcode, MRMSrcMem, typeinfo, outlist,
         (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
         mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
     Sched<[WriteALULd, ReadAfterLd]>;
 
 // BinOpRM_F - Instructions like "cmp reg, [mem]".
 class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-              SDPatternOperator opnode>
+                SDNode opnode>
   : BinOpRM<opcode, mnemonic, typeinfo, (outs),
             [(set EFLAGS,
             (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
 
 // BinOpRM_RF - Instructions like "add reg, reg, [mem]".
 class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
                  SDNode opnode>
   : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
                     SDNode opnode>
   : BinOpMR<opcode, mnemonic, typeinfo,
           [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
                   addr:$dst),
            (implicit EFLAGS)], IIC_BIN_CARRY_MEM>;
 
 // BinOpMR_F - Instructions like "cmp [mem], reg".
 class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-                  SDNode opnode>
+                SDPatternOperator opnode>
   : BinOpMR<opcode, mnemonic, typeinfo,
             [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
 
 // BinOpMI - Instructions like "add [mem], imm".
 class BinOpMI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
               Format f, list<dag> pattern,
               InstrItinClass itin = IIC_BIN_MEM>
   : ITy<opcode, f, typeinfo,
let isCompare = 1 in {
   let Defs = [EFLAGS] in {
     let isCommutable = 1 in {
       def TEST8rr  : BinOpRR_F<0x84, "test", Xi8 , X86testpat>;
       def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat>;
       def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat>;
       def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>;
     } // isCommutable
 
-    def TEST8rm    : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
-    def TEST16rm   : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
-    def TEST32rm   : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
-    def TEST64rm   : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
+    def TEST8mr    : BinOpMR_F<0x84, "test", Xi8 , X86testpat>;
+    def TEST16mr   : BinOpMR_F<0x84, "test", Xi16, X86testpat>;
+    def TEST32mr   : BinOpMR_F<0x84, "test", Xi32, X86testpat>;
+    def TEST64mr   : BinOpMR_F<0x84, "test", Xi64, X86testpat>;
 
     def TEST8ri    : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
     def TEST16ri   : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
     def TEST32ri   : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
     def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
 
     def TEST8mi    : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>;
     def TEST16mi   : BinOpMI_F<0xF6, "test", Xi16, X86testpat, MRM0m>;

lib/Target/X86/X86InstrInfo.cpp

static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
+    { X86::TEST16rr,    X86::TEST16mr,      TB_FOLDED_LOAD },
     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
+    { X86::TEST32rr,    X86::TEST32mr,      TB_FOLDED_LOAD },
     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
+    { X86::TEST64rr,    X86::TEST64mr,      TB_FOLDED_LOAD },
     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
+    { X86::TEST8rr,     X86::TEST8mr,       TB_FOLDED_LOAD },
 
     // AVX 128-bit versions of foldable instructions
     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVDQUrr,   X86::VMOVDQUmr,     TB_FOLDED_STORE },
static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        TB_NO_REVERSE },
     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         TB_NO_REVERSE },
     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         TB_NO_REVERSE },
-    { X86::TEST16rr,        X86::TEST16rm,            0 },
-    { X86::TEST32rr,        X86::TEST32rm,            0 },
-    { X86::TEST64rr,        X86::TEST64rm,            0 },
-    { X86::TEST8rr,         X86::TEST8rm,             0 },
     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
 
     // MMX version of foldable instructions
     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },

lib/Target/X86/X86InstrInfo.td

 
 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
 defm : ShiftRotateByOneAlias<"rol", "ROL">;
 defm : ShiftRotateByOneAlias<"ror", "ROR">;
 FIXME */
 
 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
-def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
-                (TEST8rm  GR8 :$val, i8mem :$mem), 0>;
-def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
-                (TEST16rm GR16:$val, i16mem:$mem), 0>;
-def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
-                (TEST32rm GR32:$val, i32mem:$mem), 0>;
-def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
-                (TEST64rm GR64:$val, i64mem:$mem), 0>;
+def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}",
+                (TEST8mr  i8mem :$mem, GR8 :$val), 0>;
+def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}",
+                (TEST16mr i16mem:$mem, GR16:$val), 0>;
+def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}",
+                (TEST32mr i32mem:$mem, GR32:$val), 0>;
+def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}",
+                (TEST64mr i64mem:$mem, GR64:$val), 0>;
 
 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
                 (XCHG8rm  GR8 :$val, i8mem :$mem), 0>;
 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
                 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
                 (XCHG32rm GR32:$val, i32mem:$mem), 0>;

lib/Target/X86/X86MacroFusion.cpp

static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   case X86::TEST32rr:
   case X86::TEST64rr:
   case X86::TEST8ri:
   case X86::TEST16ri:
   case X86::TEST32ri:
   case X86::TEST32i32:
   case X86::TEST64i32:
   case X86::TEST64ri32:
-  case X86::TEST8rm:
-  case X86::TEST16rm:
-  case X86::TEST32rm:
-  case X86::TEST64rm:
+  case X86::TEST8mr:
+  case X86::TEST16mr:
+  case X86::TEST32mr:
+  case X86::TEST64mr:
   case X86::TEST8ri_NOREX:
   case X86::AND16i16:
   case X86::AND16ri:
   case X86::AND16ri8:
   case X86::AND16rm:
   case X86::AND16rr:
   case X86::AND32i32:
   case X86::AND32ri:

lib/Target/X86/X86SchedHaswell.td

 def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP8mr")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP8rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "OR(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "OR8rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>;
 def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>;
-def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>;
-def: InstRW<[HWWriteResGroup18], (instregex "TEST8rm")>;
+def: InstRW<[HWWriteResGroup18], (instregex "TEST8mr")>;
 def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>;
 
 def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
   let Latency = 1;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }

lib/Target/X86/X86SchedSandyBridge.td

 def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi8")>;
 def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi8")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
-def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>;
+def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
 
 def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;

lib/Target/X86/X86SchedSkylakeClient.td

 def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mi")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mr")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "CMP8rm")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "OR(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "OR8rm")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)mr")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mr")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>;
 def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>;
 
 def SKLWriteResGroup22 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
   let Latency = 1;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }

test/CodeGen/X86/absolute-bit-mask.ll

 
 f:
   ret void
 }
 
 define void @foo64(i64* %ptr) {
   %load = load i64, i64* %ptr
   ; CHECK: movabsq $bit_mask64, %rax
-  ; CHECK: testq (%rdi), %rax
+  ; CHECK: testq %rax, (%rdi)
   %and = and i64 %load, ptrtoint (i8* @bit_mask64 to i64)
   %icmp = icmp eq i64 %and, 0
   br i1 %icmp, label %t, label %f
 
 t:
   call void @f()
   ret void
 
 f:
   ret void
 }
 
 !0 = !{i64 0, i64 256}
 !1 = !{i64 0, i64 4294967296}
 !2 = !{i64 -1, i64 -1}

test/CodeGen/X86/post-ra-sched-with-debug.mir

bb.0:
     %rsi = OR64rr killed %rsi, killed %rcx, implicit-def %eflags
     %rcx = LEA64r %rbp, 1, _, -20, _
     DBG_VALUE debug-use %rcx, debug-use _, !46, !17, debug-location !48
     DBG_VALUE debug-use %rcx, debug-use _, !39, !17, debug-location !44
     DBG_VALUE %rbp, -20, !29, !17, debug-location !36
     %rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags
     %rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags
     %rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8)
-    TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4)
+    TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4)
     JNE_1 %bb.2, implicit %eflags
     JMP_1 %bb.3
 
   bb.1:
     successors: %bb.2
     liveins: %rbx, %rbp
 
     %rdi = MOV64rm %rbx, 1, _, 24, _ :: (load 8)

test/CodeGen/X86/testl-commute.ll

 ; RUN: llc < %s | FileCheck %s
 ; rdar://5671654
 ; The loads should fold into the testl instructions, no matter how
 ; the inputs are commuted.
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin7"
 
 define i32 @test(i32* %P, i32* %G) nounwind {
 ; CHECK-LABEL: test:
 ; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
 ; CHECK: ret
 
 entry:
   %0 = load i32, i32* %P, align 4    ; <i32> [#uses=3]
   %1 = load i32, i32* %G, align 4    ; <i32> [#uses=1]
   %2 = and i32 %1, %0    ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0    ; <i1> [#uses=1]
   br i1 %3, label %bb1, label %bb
 
 bb:   ; preds = %entry
   %4 = tail call i32 @bar() nounwind    ; <i32> [#uses=0]
   ret i32 %0
 
 bb1:    ; preds = %entry
   ret i32 %0
 }
 
 define i32 @test2(i32* %P, i32* %G) nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
 ; CHECK: ret
 
 entry:
   %0 = load i32, i32* %P, align 4    ; <i32> [#uses=3]
   %1 = load i32, i32* %G, align 4    ; <i32> [#uses=1]
   %2 = and i32 %0, %1    ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0    ; <i1> [#uses=1]
   br i1 %3, label %bb1, label %bb
 
 bb:   ; preds = %entry
   %4 = tail call i32 @bar() nounwind    ; <i32> [#uses=0]
   ret i32 %0
 
 bb1:    ; preds = %entry
   ret i32 %0
 }
 
 define i32 @test3(i32* %P, i32* %G) nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
 ; CHECK: ret
 
 entry:
   %0 = load i32, i32* %P, align 4    ; <i32> [#uses=3]
   %1 = load i32, i32* %G, align 4    ; <i32> [#uses=1]
   %2 = and i32 %0, %1    ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0    ; <i1> [#uses=1]
   br i1 %3, label %bb1, label %bb

test/MC/Disassembler/X86/x86-16.txt

 0x66 0xcf
 
 # CHECK: sysretl
 0x0f 0x07
 
 # CHECK: sysretl
 0x0f 0x07
 
-# CHECK: testl -24(%ebp), %ecx
+# CHECK: testl %ecx, -24(%ebp)
 0x67 0x66 0x85 0x4d 0xe8
 
-# CHECK: testl -24(%ebp), %ecx
+# CHECK: testl %ecx, -24(%ebp)
 0x67 0x66 0x85 0x4d 0xe8
 
 # CHECK: pushw %cs
 0x0e
 
 # CHECK: pushw %ds
 0x1e
 

test/MC/X86/intel-syntax.s

 // CHECK: xchgw %ax, (%ecx)
 xchg RAX, [ECX]
 xchg [ECX], RAX
 xchg EAX, [ECX]
 xchg [ECX], EAX
 xchg AX, [ECX]
 xchg [ECX], AX
 
-// CHECK: testq (%ecx), %rax
-// CHECK: testq (%ecx), %rax
-// CHECK: testl (%ecx), %eax
-// CHECK: testl (%ecx), %eax
-// CHECK: testw (%ecx), %ax
-// CHECK: testw (%ecx), %ax
-// CHECK: testb (%ecx), %al
-// CHECK: testb (%ecx), %al
+// CHECK: testq %rax, (%ecx)
+// CHECK: testq %rax, (%ecx)
+// CHECK: testl %eax, (%ecx)
+// CHECK: testl %eax, (%ecx)
+// CHECK: testw %ax, (%ecx)
+// CHECK: testw %ax, (%ecx)
+// CHECK: testb %al, (%ecx)
+// CHECK: testb %al, (%ecx)
 test RAX, [ECX]
 test [ECX], RAX
 test EAX, [ECX]
 test [ECX], EAX
 test AX, [ECX]
 test [ECX], AX
 test AL, [ECX]
 test [ECX], AL

test/MC/X86/x86-16.s

 sysret
 // CHECK: sysretl
 // CHECK: encoding: [0x0f,0x07]
 sysretl
 // CHECK: sysretl
 // CHECK: encoding: [0x0f,0x07]
 
 testl %ecx, -24(%ebp)
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
 testl -24(%ebp), %ecx
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
 
 
 push %cs
 // CHECK: pushw %cs
 // CHECK: encoding: [0x0e]
 push %ds
 // CHECK: pushw %ds
 // CHECK: encoding: [0x1e]

test/MC/X86/x86-32.s

 // CHECK: sysretl
 // CHECK: encoding: [0x0f,0x07]
 sysretl
 // CHECK: sysretl
 // CHECK: encoding: [0x0f,0x07]
 
 // rdar://8018260
 testl %ecx, -24(%ebp)
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
 testl -24(%ebp), %ecx
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
 
 
 // rdar://8407242
 push %cs
 // CHECK: pushl %cs
 // CHECK: encoding: [0x0e]
 push %ds
 // CHECK: pushl %ds