Add instruction subset for the ARC backend

[tatyana-krasnukha]

Summary

Add instruction subset required for disassembling:

• All compact (16-bit) instruction formats;
• A couple of 32-bit instructions;
• Ability to print symbolic information for branch and call instructions.

clang-format is applied.

[petecoup]

Hi Tatyana,

Thanks for working on this!
Can you add disassembly tests for the new 16-bit short instructions that you added here?
There are a few places in the ARCDisassembler code where you use 'auto' instead of standard scalar types (unsigned/uint64_t/etc.). Can you use these types instead of auto?
You create a new namespace (arc::inst_decoder) in the Disassembler. This looks different than the rest of the Disassemblers, can you use static routines instead?
Thanks again!

ARC/ARCInstrInfo.td

217

These aren't right, please remove these MultiPat<sub, SUB[123]...> lines. You can keep the defm SUB[123]: ... lines.

ARC/Disassembler/ARCDisassembler.cpp

128

Would DecodeGBR32ShortRegister be a better name?

172

I think static_cast is better than reinterpret_cast here?

[tatyana-krasnukha]

Hi Pete, thank you for review!

I'll do suggested corrections as soon as I'll have tests written.
Speaking of static and namespaces, I don't like this C-style code, but if you insist...)

ARC/ARCInstrInfo.td

217

Ok.

ARC/Disassembler/ARCDisassembler.cpp

128

Yes, probably it is...

172

static_cast could lead to the mistaken belief that this type cast is safe, whereas reinterpret_cast is more conspicuous and reminding that the code requires changes)

[petecoup]

Hello Tatyana,

I am mostly going with the style/conventions observed in the other backends/disassemblers. Can we use these current conventions for this patch? I feel like ARCDisassembler doesn't need many changes to enable the new instructions.
That will let us focus on the main new material here (new .td definitions/16-bit disassembly support). Perhaps suggestions on when do use C++ namespaces and MCDisassembler* instead of void* that would apply for all disassemblers could be proposed in a separate patch?

So, I view the goal of this patch is to provide enough 16-bit instruction format information so we can disassemble all 16-bit instructions with these formats.
Thanks again!

ARC/ARCInstrFormats.td

882

For consistency, can we change asmstr#"stuff" -> !strconcat(asmstr, "stuff")?

ARC/ARCInstrInfo.td

421

If we map bits 10-8,4-3 to the g register, do we need the custom decoder method anymore?

423

This doesn't need to be strconcat.

ARC/Disassembler/ARCDisassembler.cpp

286

See my earlier comment about mapping the correct bits for the g register. I don't think this custom decoder routine is needed.

368

Please remove the braces from this conditional.

ARC/InstPrinter/ARCInstPrinter.cpp

105

This reads a bit easier as 2 lines, and is how other printers do this:
OS << "0x";
OS.write_hex(CE->getValue());

[tatyana-krasnukha]

Added tests, fixed ARCDisassembler.cpp according suggestions.

[tatyana-krasnukha]

ARC/ARCInstrInfo.td

421

Yes, it is required to handle such cases as limm data operand or no destination (MOV_S 0,h and MOV_S 0,limm). I haven't found the way to implement it in .td

[tatyana-krasnukha]

Applied fixes from 2nd comment.

[tatyana-krasnukha]

Forgot to change decoder method name.

[petecoup]

Hello Tatyana,

Thanks again for the work here.
I applied this patch, and am getting build errors (DecodeFromCyclicRange, ReadField used before declared, others).
Assuming these declarations get moved to the right places, my only remaining question is how others feel about the ReadField/ReadFields variadic templates.

lib/Target/ARC/Disassembler/ARCDisassembler.cpp

265 ↗

(On Diff #118015)

This makes the users more compact, but it seems less readable.

[tatyana-krasnukha]

Thanks for comment, Pete!

Fixed the order of declarations and using of functions.
Removed variadic template for better readability.

[petecoup]

I'm getting a few errors when running these tests now?

misc.txt:25:10: error: expected string not found in input
# CHECK: bl -2028
         ^
<stdin>:9:2: note: scanning from here
 bl -1996

br.txt:6:10: error: expected string not found in input
# CHECK: brlo %r10, %r4, -112
         ^
<stdin>:3:2: note: scanning from here
 brlo %r10, %r4, -108
 ^

compact.txt:81:10: error: expected string not found in input
# CHECK: b_s 256
         ^
<stdin>:28:2: note: scanning from here
 b_s 316
 ^

[tatyana-krasnukha]

Corrupted it by merging...

[petecoup]

Hi Tatyana,

Thanks for the delay, I only have a couple other minor things.

lib/Target/ARC/Disassembler/ARCDisassembler.cpp

275 ↗

(On Diff #118804)

Can we use the appropriate unsigned type, rather than auto?

280 ↗

(On Diff #118804)

Can we pull this out into another static routine?

[tatyana-krasnukha]

Hi Pete,

lib/Target/ARC/Disassembler/ARCDisassembler.cpp

275 ↗

(On Diff #118804)

Ok. I would like to use decltype(Insn) instead of uint64_t to draw the attention that size of return value is always the same as Insn size. Do you mind?

280 ↗

(On Diff #118804)

This routine has no sense outside the scope of this function.

May be if the routine will take a parameter determine whether this is 32 or 16 bit instruction and check register number (30/62), depending on it, there will be good reason to make it a separate static function and use in many other places... But I guess to do it in another patch, do you think?

[petecoup]

I don't personally feel strongly about either of these.
I'm generally trying to match the style in other backends, which on observation I thinke would either just implement the logic inline, or create a new static routine...and omit auto.
I was wrong on other details myself originally.
But, I'm also a newbie at this reviewing bit (like I somehow mistakenly marked this as accepted?), so I'm happy to be told otherwise.

[tatyana-krasnukha]

I agree that matching the style in other backends is very important, but it is hard to be consistent with last, because it was written long before even c++11 was released...

[tatyana-krasnukha]

Use type of instruction for its fields instead of 'auto'.

[tatyana-krasnukha]

Removed accidentally added file.

[petecoup]

Hi Tatyana,

OK, what you have here is fine with me. Thanks for all of the work here!

[tatyana-krasnukha]

Hi Pete,

Could you commit it for me, please? I have not commit access.

[petecoup]

@kparzysz, procedural question...am I OK to commit this for Tatyana, or do we need someone else to also sign off on this as well?

[tatyana-krasnukha]

When I added instructions, I didn't care about properties like isBranch, isBarrier, etc., because didn't know its purpose. But it was found that debugger cannot step over a range of instructions correctly without this knowing, thus, I've added appropriate fields to instructions.

Also, replaced empty { } with ;

[petecoup]

OK, I was aware of these...but didn't know that you'd need them for the debugger. There are a couple of others (mayLoad, mayStore, Defs STATUS32), but I was going to add them when the code generation uses them. Thanks!

[tatyana-krasnukha]

Hi Pete,
Now I have commit after approval access and would land this revision. May I do it now?

[petecoup]

Hello Tatyana,

This looks fine to me. If you can commit, please do!

ARC/ARCInstrFormats.td

 }
 
 // Address operands
-def immU6 : Operand<i32>, PatLeaf<(imm), [{
-    return isUInt<6>(N->getSExtValue()); }]> {
+
+class immU<int BSz> : Operand<i32>, PatLeaf<(imm),
+    "\n    return isUInt<"#BSz#">(N->getSExtValue());"> {
 }
 
-def immS12 : Operand<i32>, PatLeaf<(imm), [{
-    return isInt<12>(N->getSExtValue()); }]> {
-  let DecoderMethod = "DecodeS12Operand";
+def immU6 : immU<6> {}
+
+class immS<int BSz> : Operand<i32>, PatLeaf<(imm),
+    "\n    return isInt<"#BSz#">(N->getSExtValue());"> {
+  let DecoderMethod = "DecodeSignedOperand<"#BSz#">";
 }
 
-def immS9 : Operand<i32>, PatLeaf<(imm), [{
-    return isInt<9>(N->getSExtValue()); }]> {
-  let DecoderMethod = "DecodeS9Operand";
+// e.g. s3 field may encode the signed integers values -1 .. 6
+// using binary codes 111, 000, 001, 010, 011, 100, 101, and 110, respectively
+class immC<int BSz, int OvrFlw> : Operand<i32>, PatLeaf<(imm),
+    "\n    return isInt<"#BSz#">(N->getSExtValue());"> {
+  let DecoderMethod = "DecodeFromCyclicRange<"#BSz#", "#OvrFlw#">";
 }
 
 def MEMii : Operand<i32> {

 }
 
 def MEMrs9 : Operand<iAny> {
-  let MIOperandInfo = (ops GPR32:$B, immS9:$S9);
+  let MIOperandInfo = (ops GPR32:$B, immS<9>:$S9);
   let PrintMethod = "printMemOperandRI";
   let DecoderMethod = "DecodeMEMrs9";
 }

   let DecoderMethod = "DecodeMEMrlimm";
 }
 
+def GPR32Reduced : Operand<iAny> {
+  let DecoderMethod = "DecodeGPR32ReducedRegister";
+}
+
 class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
     : Instruction, Encoding64 {
 

   let Inst{17} = 0;
 }
 
-
 // BRcc targets have limited 9-bit range.  These are for compare and branch
 // in single instruction.  Their targets are 2-byte aligned.  They also use
 // a different (3-bit) set of condition codes.

   let DecoderMethod = "DecodeStLImmInstruction";
 }
 
+// Compact Move/Load.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |      |h    |   |i|H  |
+class F16_COMPACT<bits<1> i, dag outs, dag ins,
+                 string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  bits<5> h;
+
+  let Inst{15-11} = 0b01000;
+  let Inst{7-5} = h{2-0};
+  let Inst{2} = i;
+  let Inst{1-0} = h{4-3};  
+}
+
+// Compact Load/Add/Sub.
+class F16_LD_ADD_SUB<dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  bits<3> b;  
+  let Inst{15-11} = 0b01001;
+  let Inst{10-8} = b;
+}
+
+class F16_LD_SUB<bit i, string asmstr> :
+  F16_LD_ADD_SUB<(outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
+  asmstr> {
+
+  bits<3> a;
+  bits<3> c;
+
+  let Inst{7-5} = c;
+  let Inst{4} = i;
+  let Inst{3} = 0;
+  let Inst{2-0} = a;
+}
+
+class F16_ADD :
+  F16_LD_ADD_SUB<(outs GPR32:$r), (ins GPR32:$b, immU<6>:$u6),
+  "add_s\t$r, $b, $u6"> {
+  
+  bit r;
+  bits<6> u6;
+  
+  let Inst{7} = r;
+  let Inst{6-4} = u6{5-3};
+  let Inst{3} = 1;
+  let Inst{2-0} = u6{2-0};
+}
+
+// Compact Load/Store.
+class F16_LD_ST_1<dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  let Inst{15-11} = 0b01010;
+}
+
+class F16_LD_ST_s11<bit i, string asmstr> :
+  F16_LD_ST_1<(outs), (ins immS<11>:$s11), asmstr> {
+
+  bits<11> s11;
+
+  let Inst{10-5} = s11{10-5};
+  let Inst{4} = i;
+  let Inst{3} = 0;
+  let Inst{2-0} = s11{4-2};
+  let s11{1-0} = 0b00;
+}
+
+class F16_LDI_u7 :
+  F16_LD_ST_1<(outs GPR32:$b), (ins immU<7>:$u7),
+  "ldi_s\t$b, [$u7]"> {
+
+  bits<3> b;
+  bits<7> u7;
+  
+  let Inst{10-8} = b;
+  let Inst{7-4} = u7{6-3};
+  let Inst{3} = 1;
+  let Inst{2-0} = u7{2-0};
+}
+
+// Indexed Jump or Execute.
+class F16_JLI_EI<bit i, string asmstr> :
+  InstARC<2, (outs), (ins immU<10>:$u10),
+  !strconcat(asmstr, "\t$u10"), []> {
+
+  bits<10> u10;
+  
+  let Inst{15-11} = 0b01011;
+  let Inst{10} = i;
+  let Inst{9-0} = u10;
+}
+
+// Load/Add Register-Register.
+class F16_LD_ADD_RR<bits<2> i, string asmstr> :
+  InstARC<2, (outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
+  asmstr, []> {
+
+  bits<3> a;
+  bits<3> b; 
+  bits<3> c;
+ 
+  let Inst{15-11} = 0b01100;
+  let Inst{10-8} = b;
+  let Inst{7-5} = c;
+  let Inst{4-3} = i;
+  let Inst{2-0} = a;
+}
+
+// Load/Add GP-Relative.
+class F16_GP_LD_ADD<bits<2> i, dag ins, string asmstr> :
+  InstARC<2, (outs), ins, asmstr, []> {
+ 
+  let Inst{15-11} = 0b11001;
+  let Inst{10-9} = i;
+}
+
+// Add/Sub/Shift Register-Immediate.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b     |c    |i  |u    |
+class F16_ADD_IMM<bits<2> i, string asmstr> :
+  InstARC<2, (outs GPR32:$c), (ins GPR32:$b, immU<3>:$u3),
+  !strconcat(asmstr, "\t$c, $b, $u3"), []> {
+
+  bits<3> b;
+  bits<3> c;
+  bits<3> u3;
+  
+  let Inst{15-11} = 0b01101;
+  let Inst{10-8} = b;
+  let Inst{7-5} = c;
+  let Inst{4-3} = i;
+  let Inst{2-0} = u3;
+}
+
+// Dual Register Operations.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b/s   |h    |i    |H  |
+class F16_OP_HREG<bits<3> i, dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  bits<3> b_s3;
+  bits<5> h;
+
+  let Inst{15-11} = 0b01110;
+  let Inst{10-8} = b_s3;
+  let Inst{7-5} = h{2-0};
+  let Inst{4-2} = i;
+  let Inst{1-0} = h{4-3};
+}
+
+class F16_OP_HREG30<bits<3> i, dag outs, dag ins, string asmstr> :
+  F16_OP_HREG<i, outs, ins, asmstr> {
+    
+  bits<5> LImmReg = 0b11110;  
+  let Inst{7-5} = LImmReg{2-0};
+  let Inst{1-0} = LImmReg{4-3};
+}
+
+class F16_OP_HREG_LIMM<bits<3> i, dag outs, dag ins, string asmstr> :
+  F16_OP_HREG30<i, outs, ins, asmstr> {
+
+  bits<32> LImm;
+  let Inst{47-16} = LImm;
+  let Size = 6;
+}
+
+// General compact DOP format.
+class F16_GEN_DOP_BASE<bits<5> i, dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  bits<3> b;
+  bits<3> c;
+  let Inst{15-11} = 0b01111;
+  let Inst{10-8} = b;
+  let Inst{7-5} = c;
+  let Inst{4-0} = i;
+}
+
+class F16_GEN_DOP<bits<5> i, string asmstr> :
+  F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
+  !strconcat(asmstr, "\t$b, $b, $c")> {}
+
+class F16_GEN_DOP_NODST<bits<5> i, string asmstr> :
+  F16_GEN_DOP_BASE<i, (outs), (ins GPR32:$b, GPR32:$c),
+  !strconcat(asmstr, "\t$b, $c")> {}
+
+class F16_GEN_DOP_SINGLESRC<bits<5> i, string asmstr> :
+  F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
+  !strconcat(asmstr, "\t$b, $c")> {}
+
+class F16_GEN_SOP_BASE<bits<3> i, dag outs, dag ins, string asmstr> :
+  F16_GEN_DOP_BASE<0b00000, outs, ins, asmstr> {
+
+  let c = i;
+}
+
+class F16_GEN_SOP<bits<3> i, string asmstr> :
+  F16_GEN_SOP_BASE<i, (outs), (ins GPR32:$b), asmstr> {}
+
+class F16_GEN_ZOP<bits<3> i, string asmstr> :
+  F16_GEN_SOP_BASE<0b111, (outs), (ins), asmstr> {
+
+  let b = i;
+}
+
+// Compact Load/Store with Offset Format.
+class F16_LD_ST_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, !strconcat(asmstr, "\t$c, [$b, $off]"), []> {
+
+  bits<3> b;
+  bits<3> c;
+  let Inst{15-11} = opc;
+  let Inst{10-8} = b;
+  let Inst{7-5} = c;
+}
+
+class F16_LD_ST_WORD_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+  F16_LD_ST_OFF<opc, outs, ins, asmstr> {
+
+  bits<7> off;
+  let Inst{4-0} = off{6-2};
+  let off{1-0} = 0b00;
+}
+
+class F16_LD_ST_HALF_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+  F16_LD_ST_OFF<opc, outs, ins, asmstr> {
+
+  bits<6> off;
+  let Inst{4-0} = off{5-1};
+  let off{0} = 0b0;
+}
+
+class F16_LD_ST_BYTE_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+  F16_LD_ST_OFF<opc, outs, ins, asmstr> {
+
+  bits<5> off;
+  let Inst{4-0} = off;
+}
+
+// Shift/Subtract/Bit Immediate.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b     |i    |u        |
+class F16_SH_SUB_BIT<bits<3> i, string asmstr> :
+  InstARC<2, (outs), (ins GPR32:$b, immU<5>:$u5), asmstr, []> {
+
+  bits<3> b;
+  bits<5> u5;
+  
+  let Inst{15-11} = 0b10111;
+  let Inst{10-8} = b;
+  let Inst{7-5} = i;
+  let Inst{4-0} = u5;
+}
+
+class F16_SH_SUB_BIT_DST<bits<3> i, string asmstr> :
+  F16_SH_SUB_BIT<i, !strconcat(asmstr, "\t$b, $b, $u5")> {}
+
+// 16-bit stack-based operations.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b     |i    |u        |
+class F16_SP_OPS<bits<3> i,
+  dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  bits<3> fieldB;
+  bits<5> fieldU;
+
+  let Inst{15-11} = 0b11000;
+  let Inst{10-8} = fieldB;
+  let Inst{7-5} = i;
+  let Inst{4-0} = fieldU;
+}
+
+class F16_SP_OPS_u7_aligned<bits<3> i,
+  dag outs, dag ins, string asmstr> :
+  F16_SP_OPS<i, outs, ins, asmstr> {
+
+  bits<3> b3;
+  bits<7> u7;
+  
+  let fieldB = b3;
+  let fieldU = u7{6-2};
+  let u7{1-0} = 0b00;
+}
+
+class F16_SP_OPS_bconst<bits<3> b, string asmop> :
+  F16_SP_OPS_u7_aligned<0b101,
+  (outs), (ins immU<7>:$u7),
+  !strconcat(asmop, "\t%sp, %sp, $u7")> {
+  
+  let fieldB = b;
+}
+
+class F16_SP_OPS_uconst<bits<3> i,
+  dag outs, dag ins, string asmop> :
+  F16_SP_OPS_u7_aligned<i, outs, ins,
+  !strconcat(asmop, "\t$b3")> {
+  
+  let fieldU = 0b00001;
+}
+
+class F16_SP_OPS_buconst<bits<3> i, string asmop> :
+  F16_SP_OPS_u7_aligned<i, (outs), (ins),
+    !strconcat(asmop, "\t%blink")> {
+  
+  let fieldB = 0x000;
+  let fieldU = 0b10001;
+}
+
+class F16_SP_LD<bits<3> i, string asmop> : F16_SP_OPS_u7_aligned<i,
+                         (outs GPR32Reduced:$b3), (ins immU<7>:$u7),
+                         !strconcat(asmop, "\t$b3, [%sp, $u7]")> {}
+
+class F16_SP_ST<bits<3> i, string asmop> : F16_SP_OPS_u7_aligned<i,
+                         (outs), (ins GPR32Reduced:$b3, immU<7>:$u7),
+                         !strconcat(asmop, "\t$b3, [%sp, $u7]")> {}
+
+// Compact MOV/ADD/CMP Immediate Format.
+class F16_OP_IMM<bits<5> opc, dag outs, dag ins, string asmstr> :
+  InstARC<2, outs, ins, asmstr, []> {
+
+  bits<3> b;
+  let Inst{15-11} = opc;
+  let Inst{10-8} = b;
+}
+
+class F16_OP_U7<bit i, string asmstr> :
+  F16_OP_IMM<0b11100, (outs GPR32:$b), (ins immU<7>:$u7), asmstr> {
+
+  bits<7> u7;
+  let Inst{7} = i;
+  let Inst{6-0} = u7;
+}
+
 // Special types for different instruction operands.
 def cmovpred : Operand<i32>, PredicateOp,
                ComplexPattern<i32, 2, "SelectCMOVPred"> {

   let PrintMethod = "printBRCCPredicateOperand";
 }
 
-// Branch targets of different offset sizes.
-def btarget : Operand<OtherVT> {
+// Branch/call targets of different offset sizes.
+class BCTarget<ValueType vt> : Operand<vt> {
   let OperandType = "OPERAND_PCREL";
 }
 
-def btargetS9 : Operand<OtherVT> {
-  let OperandType = "OPERAND_PCREL";
-  let DecoderMethod = "DecodeBranchTargetS9";
+def btarget : BCTarget<OtherVT> {}
+
+class BCTargetSigned<ValueType vt, int BSz> : BCTarget<vt> {
+  let DecoderMethod = "DecodeBranchTargetS<"#BSz#">";
 }
 
-def btargetS21 : Operand<OtherVT> {
-  let OperandType = "OPERAND_PCREL";
-  let DecoderMethod = "DecodeBranchTargetS21";
+class BranchTargetS<int BSz> : BCTargetSigned<OtherVT, BSz> {}
+def btargetS7 : BranchTargetS<7> {}
+def btargetS8 : BranchTargetS<8> {}
+def btargetS9 : BranchTargetS<9> {}
+def btargetS10 : BranchTargetS<10> {}
+def btargetS21 : BranchTargetS<21> {}
+def btargetS25 : BranchTargetS<25> {}
+
+class CallTargetS<int BSz> : BCTargetSigned<i32, BSz> {}
+def calltargetS25: CallTargetS<25> {}
+
+// Compact Branch on Compare Register with Zero.
+class F16_BCC_REG<bit i, string asmstr> :
+  InstARC<2, (outs), (ins GPR32:$b, btargetS8:$s8),
+  asmstr#"\t$b, 0, $s8", []> {
+
+  bits<3> b;
+  bits<8> s8;
+
+  let Inst{15-11} = 0b11101;
+  let Inst{10-8} = b;
+  let Inst{7} = i;
+  let Inst{6-0} = s8{7-1};
+  let s8{0} = 0b0;
 }
 
-def btargetS25 : Operand<OtherVT> {
-  let OperandType = "OPERAND_PCREL";
-  let DecoderMethod = "DecodeBranchTargetS25";
+// Compact Branch Conditionally Format.
+class F16_BCC<bits<2> i, dag ins, string asmstr> :
+  InstARC<2, (outs), ins, asmstr, []> {
+
+  let Inst{15-11} = 0b11110;
+  let Inst{10-9} = i;
 }
 
-def calltargetS25: Operand<i32> {
-  let OperandType = "OPERAND_PCREL";
-  let DecoderMethod = "DecodeBranchTargetS25";
+class F16_BCC_s10<bits<2> i, string asmstr> :
+  F16_BCC<i, (ins btargetS10:$s), asmstr#"\t$s"> {
+
+  bits<10> s;
+  let Inst{8-0} = s{9-1};
+  let s{0} = 0b0;
 }
 
+class F16_BCC_s7<bits<3> i, string asmstr> :
+  F16_BCC<0b11, (ins btargetS7:$s), asmstr#"\t$s"> {
+
+  bits<7> s;
+  let Inst{8-6} = i;
+  let Inst{5-0} = s{6-1};
+  let s{0} = 0b0;
+}

ARC/ARCInstrInfo.td

 // multiclass.  These classes do not contain Selection DAG patterns.
 //===----------------------------------------------------------------------===//
 
-// Generic 3 operand binary instructions (i.e., add, r0, r1, r2).
+// Generic 3 operand binary instructions (i.e., add r0, r1, r2).
 multiclass ArcBinaryInst<bits<5> major, bits<6> mincode,
                        string opasm> {
   // 3 register variant.

   // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1).
   def _rrs12 : F32_DOP_RS12<major, mincode, 0,
                             (outs GPR32:$B),
-                            (ins GPR32:$in, immS12:$S12),
+                            (ins GPR32:$in, immS<12>:$S12),
                             !strconcat(opasm, "\t$B, $in, $S12"),
                             []>
   { let Constraints = "$B = $in"; }

 // Definitions for 3 operand binary instructions.
 defm ADD : ArcBinaryGEN4Inst<0b000000, "add">;
 defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">;
+defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;
+defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">;
+defm SUB3 : ArcBinaryGEN4Inst<0b011001, "sub3">;
 defm OR  : ArcBinaryGEN4Inst<0b000101, "or">;
 defm AND : ArcBinaryGEN4Inst<0b000100, "and">;
 defm XOR : ArcBinaryGEN4Inst<0b000111, "xor">;

 defm MPY  : ArcBinaryGEN4Inst<0b011010, "mpy">;
 defm MPYM : ArcBinaryGEN4Inst<0b011011, "mpym">;
 defm MPYMU : ArcBinaryGEN4Inst<0b011100, "mpymu">;
+defm SETEQ : ArcBinaryGEN4Inst<0b111000, "seteq">;
 
 // Patterns for 3 operand binary instructions.
 defm : MultiPat<add, ADD_rrr, ADD_rru6, ADD_rrlimm>;
 defm : MultiPat<sub, SUB_rrr, SUB_rru6, SUB_rrlimm>;
+defm : MultiPat<sub, SUB1_rrr, SUB1_rru6, SUB1_rrlimm>;
+defm : MultiPat<sub, SUB2_rrr, SUB2_rru6, SUB2_rrlimm>;
+defm : MultiPat<sub, SUB3_rrr, SUB3_rru6, SUB3_rrlimm>;
 defm : MultiPat<or, OR_rrr, OR_rru6, OR_rrlimm>;
 defm : MultiPat<and, AND_rrr, AND_rru6, AND_rrlimm>;
 defm : MultiPat<xor, XOR_rrr, XOR_rru6, XOR_rrlimm>;

 defm : MultiPat<mulhs, MPYM_rrr, MPYM_rru6, MPYM_rrlimm>;
 defm : MultiPat<mulhu, MPYMU_rrr, MPYMU_rru6, MPYMU_rrlimm>;
 
-
 // ---------------------------------------------------------------------------
 // Unary Instruction definitions.
 // ---------------------------------------------------------------------------

 // ---------------------------------------------------------------------------
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
 def MOV_rs12 : F32_DOP_RS12<0b00100, 0b001010, 0,
-                 (outs GPR32:$B), (ins immS12:$S12),
+                 (outs GPR32:$B), (ins immS<12>:$S12),
                  "mov\t$B, $S12",
-                 [(set GPR32:$B, immS12:$S12)]>;
+                 [(set GPR32:$B, immS<12>:$S12)]>;
 }
 
 def MOV_rr : F32_DOP_RR<0b00100, 0b001010, 0,

 }
 
 //----------------------------------------------------------------------------
-// Load/Store instructions.
+// Compact stack-based operations.
 //----------------------------------------------------------------------------
 
 // 2-byte push/pop blink instructions commonly used for prolog/epilog

 // format instructions that aren't generalized to a larger 2-byte
 // class, so we might as well have them here.
 let Uses = [BLINK], Defs = [SP] in {
-def PUSH_S_BLINK : InstARC<2, (outs), (ins),
-                             "push_s\t%blink", []> {
-  let Inst{15-0} = 0b1100000011110001;
+ def PUSH_S_BLINK : F16_SP_OPS_buconst<0b111, "push_s"> {}
 }
-}
 
 let Defs = [BLINK, SP] in {
-def POP_S_BLINK : InstARC<2, (outs), (ins),
-                             "pop_s\t%blink", []> {
-  let Inst{15-0} = 0b1100000011010001;
+ def POP_S_BLINK : F16_SP_OPS_buconst<0b110, "pop_s"> {}
 }
+
+def PUSH_S_r : F16_SP_OPS_uconst<0b110,
+  (outs), (ins GPR32Reduced:$b3), "push_s"> {}
+def POP_S_r : F16_SP_OPS_uconst<0b111,
+  (outs GPR32Reduced:$b3), (ins), "pop_s"> {}
+
+def SP_SUB_SP_S : F16_SP_OPS_bconst<0b001, "sub_s"> {}
+def SP_ADD_SP_S : F16_SP_OPS_bconst<0b000, "add_s"> {}
+def SP_ADD_S : F16_SP_OPS_u7_aligned<0b100,
+                (outs GPR32Reduced:$b3), (ins immU<7>:$u7),
+                "add_s\t$b3, %sp, $u7"> {}
+
+def SP_LD_S : F16_SP_LD<0b000, "ld_s"> {}
+def SP_LDB_S : F16_SP_LD<0b001, "ldb_s"> {}
+def SP_ST_S : F16_SP_ST<0b010, "st_s"> {}
+def SP_STB_S : F16_SP_ST<0b011, "stb_s"> {}
+
+def LEAVE_S : F16_SP_OPS<0b110,
+  (outs), (ins immU<7>:$u7), "leave_s\t$u7"> {
+
+  bits<7> u7;
+  
+  let fieldB = u7{6-4};
+  let fieldU{4-1} = u7{3-0};
+  let fieldU{0} = 0b0;
 }
 
+def ENTER_S : F16_SP_OPS<0b111,
+  (outs), (ins immU<6>:$u6), "enter_s\t$u6"> {
+
+  bits<6> u6;
+  
+  let fieldB{2} = 0;
+  let fieldB{1-0} = u6{5-4};
+  let fieldU{4-1} = u6{3-0};
+  let fieldU{0} = 0b0;
+}
+
+//----------------------------------------------------------------------------
+// Compact Move/Load instructions.
+//----------------------------------------------------------------------------
+class COMPACT_MOV_S :
+  F16_COMPACT<0b0, (outs GPR32:$g), (ins GPR32:$h),
+          !strconcat("mov_s", "\t$g, $h")> {  
+  let DecoderMethod = "DecodeMoveHRegInstruction";
+}
+
+def COMPACT_MOV_S_limm : COMPACT_MOV_S {
+  bits<32> LImm;  
+  let Inst{47-16} = LImm;
+
+  bits<5> LImmReg = 0b11110;  
+  let Inst{7-5} = LImmReg{2-0};
+  let Inst{1-0} = LImmReg{4-3};
+
+  let Size = 6;  
+}
+
+def COMPACT_MOV_S_hreg : COMPACT_MOV_S {}
+
+def COMPACT_LD_S :
+  F16_COMPACT<0b1, (outs GPR32:$r), (ins GPR32:$h, immU<5>:$u5),
+          "ld_s\t$r, [$h,$u5]"> {
+  bits<5> u5;
+  bits<2> r;
+
+  let Inst{10} = u5{4};
+  let Inst{9-8} = r;
+  let Inst{4-3} = u5{3-2};
+  let u5{1-0} = 0b00;
+}
+
+//----------------------------------------------------------------------------
+// Compact Load/Add/Sub.
+//----------------------------------------------------------------------------
+def LD_S_AS_rrr : F16_LD_SUB<0b0, "ld_s.as\t$a, [$b, $c]"> {}
+def SUB_S_rrr : F16_LD_SUB<0b1, "sub_s\t$a, $b, $c"> {}
+def ADD_S_rru6 : F16_ADD {}
+
+//----------------------------------------------------------------------------
+// Compact Load/Store.
+//----------------------------------------------------------------------------
+def LD_S_s11 : F16_LD_ST_s11<0b0, "ld_s\t%r1, [%gp, $s11]"> {}
+def ST_S_s11 : F16_LD_ST_s11<0b1, "st_s\t%r0, [%gp, $s11]"> {}
+def LDI_S_u7 : F16_LDI_u7 {}
+
+//----------------------------------------------------------------------------
+// Indexed Jump or Execute.
+//----------------------------------------------------------------------------
+def JLI_S : F16_JLI_EI<0, "jli_s"> {}
+def EI_S : F16_JLI_EI<1, "ei_s"> {}
+
+//----------------------------------------------------------------------------
+// Load/Add Register-Register.
+//----------------------------------------------------------------------------
+def LD_S_rrr : F16_LD_ADD_RR<0b00, "ld_s\t$a, [$b, $c]"> {}
+def LDB_S_rrr : F16_LD_ADD_RR<0b01, "ldb_s\t$a, [$b, $c]"> {}
+def LDH_S_rrr : F16_LD_ADD_RR<0b10, "ldh_s\t$a, [$b, $c]"> {}
+def ADD_S_rrr : F16_LD_ADD_RR<0b11, "add_s\t$a, $b, $c"> {}
+
+//----------------------------------------------------------------------------
+// Load/Add GP-Relative.
+//----------------------------------------------------------------------------
+def GP_LD_S : F16_GP_LD_ADD<0b00, (ins immS<11>:$s),
+  "ld_s\t%r0, [%gp, $s]"> {
+
+  bits<11> s;
+  let Inst{8-0} = s{10-2};
+  let s{1-0} = 0b00;
+}
+
+def GP_LDB_S : F16_GP_LD_ADD<0b01, (ins immS<9>:$s),
+  "ldb_s\t%r0, [%gp, $s]"> {
+
+  bits<9> s;
+  let Inst{8-0} = s{8-0};
+}
+
+def GP_LDH_S : F16_GP_LD_ADD<0b10, (ins immS<10>:$s),
+  "ldh_s\t%r0, [%gp, $s]"> {
+
+  bits<10> s;
+  let Inst{8-0} = s{9-1};
+  let s{0} = 0b0;
+}
+
+def GP_ADD_S : F16_GP_LD_ADD<0b11, (ins immS<11>:$s),
+  "add_s\t%r0, %gp, $s"> {
+
+  bits<11> s;
+  let Inst{8-0} = s{10-2};
+  let s{1-0} = 0b00;
+}
+
+//----------------------------------------------------------------------------
+// Load PCL-Relative.
+//----------------------------------------------------------------------------
+def PCL_LD : InstARC<2, (outs GPR32:$b), (ins immU<10>:$u10),
+ "ld_s\t$b, [%pcl, $u10]", []> {
+ 
+  bits<3> b; 
+  bits<10> u10; 
+
+  let Inst{15-11} = 0b11010;
+  let Inst{10-8} = b;
+  let Inst{7-0} = u10{9-2};
+  let u10{1-0} = 0b00;
+}
+
+//----------------------------------------------------------------------------
+// Branch on Compare Register with Zero.
+//----------------------------------------------------------------------------
+def BREQ_S : F16_BCC_REG<0b0, "breq_s"> {}
+def BRNE_S : F16_BCC_REG<0b1, "brne_s"> {}
+
+//----------------------------------------------------------------------------
+// Branch Conditionally.
+//----------------------------------------------------------------------------
+def B_S : F16_BCC_s10<0b00, "b_s"> {}
+def BEQ_S : F16_BCC_s10<0b01, "beq_s"> {}
+def BNE_S : F16_BCC_s10<0b10, "bne_s"> {}
+def BGT_S : F16_BCC_s7<0b000, "bgt_s"> {}
+def BGE_S : F16_BCC_s7<0b001, "bge_s"> {}
+def BLT_S : F16_BCC_s7<0b010, "blt_s"> {}
+def BLE_S : F16_BCC_s7<0b011, "ble_s"> {}
+def BHI_S : F16_BCC_s7<0b100, "bhi_s"> {}
+def BHS_S : F16_BCC_s7<0b101, "bhs_s"> {}
+def BLO_S : F16_BCC_s7<0b110, "blo_s"> {}
+def BLS_S : F16_BCC_s7<0b111, "bls_s"> {}
+
+def BL_S :
+  InstARC<2, (outs), (ins immS<13>:$s13), "bl_s\t$s13", []> {
+
+  let Inst{15-11} = 0b11111;
+  
+  bits<13> s;
+  let Inst{10-0} = s{12-2};
+  let s{1-0} = 0b00;
+}
+
+//----------------------------------------------------------------------------
+// Add/Sub/Shift Register-Immediate.
+//----------------------------------------------------------------------------
+def ADD_S_ru3 : F16_ADD_IMM<0b00,"add_s"> {}
+def SUB_S_ru3 : F16_ADD_IMM<0b01,"sub_s"> {}
+def ASL_S_ru3 : F16_ADD_IMM<0b10,"asl_s"> {}
+def ASR_S_ru3 : F16_ADD_IMM<0b11,"asr_s"> {}
+
+//----------------------------------------------------------------------------
+// Shift/Subtract/Bit Immediate.
+//----------------------------------------------------------------------------
+def ASL_S_ru5 : F16_SH_SUB_BIT_DST<0b000,"asl_s"> {}
+def LSR_S_ru5 : F16_SH_SUB_BIT_DST<0b001,"lsr_s"> {}
+def ASR_S_ru5 : F16_SH_SUB_BIT_DST<0b010,"asr_s"> {}
+def SUB_S_ru5 : F16_SH_SUB_BIT_DST<0b011,"sub_s"> {}
+def BSET_S_ru5 : F16_SH_SUB_BIT_DST<0b100,"bset_s"> {}
+def BCLR_S_ru5 : F16_SH_SUB_BIT_DST<0b101,"bclr_s"> {}
+def BMSK_S_ru5 : F16_SH_SUB_BIT_DST<0b110,"bmsk_s"> {}
+def BTST_S_ru5 : F16_SH_SUB_BIT<0b111, "btst_s\t$b, $u5"> {}
+
+//----------------------------------------------------------------------------
+// Dual Register Operations.
+//----------------------------------------------------------------------------
+def ADD_S_rlimm :
+  F16_OP_HREG_LIMM<0b000, (outs GPR32:$b_s3), (ins i32imm:$LImm),
+          !strconcat("add_s", "\t$b_s3, $b_s3, $LImm")> {}
+
+def ADD_S_rr :
+  F16_OP_HREG<0b000, (outs GPR32:$b_s3), (ins GPR32:$h),
+          !strconcat("add_s", "\t$b_s3, $b_s3, $h")> {}
+
+def ADD_S_rs3 :
+  F16_OP_HREG<0b001, (outs GPR32:$h), (ins immC<3, -1>:$b_s3),
+          !strconcat("add_s", "\t$h, $h, $b_s3")> {}
+
+def ADD_S_limms3 :
+  F16_OP_HREG_LIMM<0b001, (outs), (ins immC<3, -1>:$b_s3, i32imm:$LImm),
+          !strconcat("add_s", "\t0, $LImm, $b_s3")> {}
+
+def MOV_S_NE_rlimm :
+  F16_OP_HREG_LIMM<0b111, (outs GPR32:$b_s3), (ins i32imm:$LImm),
+          !strconcat("mov_s.ne", "\t$b_s3, $LImm")> {}
+
+def MOV_S_NE_rr :
+  F16_OP_HREG<0b111,(outs GPR32:$b_s3), (ins GPR32:$h),
+          !strconcat("mov_s.ne", "\t$b_s3, $h")> {}
+
+def MOV_S_rs3 :
+  F16_OP_HREG<0b011, (outs GPR32:$h), (ins immC<3, -1>:$b_s3),
+          !strconcat("mov_s", "\t$h, $b_s3")> {}
+
+def MOV_S_s3 :
+  F16_OP_HREG30<0b011, (outs), (ins immS<3>:$b_s3),
+          !strconcat("mov_s", "\t0, $b_s3")> {}
+
+def CMP_S_rlimm :
+  F16_OP_HREG_LIMM<0b100, (outs GPR32:$b_s3), (ins i32imm:$LImm),
+          !strconcat("cmp_s", "\t$b_s3, $LImm")> {}
+
+def CMP_S_rr :
+  F16_OP_HREG<0b100, (outs GPR32:$b_s3), (ins GPR32:$h),
+          !strconcat("cmp_s", "\t$b_s3, $h")> {}
+
+def CMP_S_rs3 :
+  F16_OP_HREG<0b101, (outs GPR32:$h), (ins immC<3, -1>:$b_s3),
+          !strconcat("cmp_s", "\t$h, $b_s3")> {}
+
+def CMP_S_limms3 :
+  F16_OP_HREG_LIMM<0b101, (outs), (ins immC<3, -1>:$b_s3, i32imm:$LImm),
+          !strconcat("cmp_s", "\t$LImm, $b_s3")> {}
+
+//----------------------------------------------------------------------------
+// Compact MOV/ADD/CMP Immediate instructions.
+//----------------------------------------------------------------------------
+def MOV_S_u8 :
+  F16_OP_IMM<0b11011, (outs GPR32:$b), (ins immU<8>:$u8),
+          !strconcat("mov_s", "\t$b, $u8")> {
+  bits<8> u8;
+  let Inst{7-0} = u8;
+}
+
+def ADD_S_u7 :
+  F16_OP_U7<0b0, !strconcat("add_s", "\t$b, $b, $u7")> {}
+
+def CMP_S_u7 :
+  F16_OP_U7<0b1, !strconcat("cmp_s", "\t$b, $u7")> {}
+
+//----------------------------------------------------------------------------
+// Compact Load/Store instructions with offset.
+//----------------------------------------------------------------------------
+def LD_S_OFF :
+  F16_LD_ST_WORD_OFF<0x10, (outs GPR32:$c), (ins GPR32:$b, immU<7>:$off),
+  "ld_s"> {}
+
+def LDB_S_OFF :
+  F16_LD_ST_BYTE_OFF<0x11, (outs GPR32:$c), (ins GPR32:$b, immU<5>:$off),
+  "ldb_s"> {}
+
+class F16_LDH_OFF<bits<5> opc, string asmstr> :
+  F16_LD_ST_HALF_OFF<opc, (outs GPR32:$c), (ins GPR32:$b, immU<6>:$off),
+  asmstr> {}
+
+def LDH_S_OFF : F16_LDH_OFF<0x12, "ldh_s"> {}
+def LDH_S_X_OFF : F16_LDH_OFF<0x13, "ldh_s.x"> {}
+
+def ST_S_OFF :
+  F16_LD_ST_WORD_OFF<0x14, (outs), (ins GPR32:$c, GPR32:$b, immU<7>:$off),
+  "st_s"> {}
+
+def STB_S_OFF :
+  F16_LD_ST_BYTE_OFF<0x15, (outs), (ins GPR32:$c, GPR32:$b, immU<5>:$off),
+  "stb_s"> {}
+
+def STH_S_OFF :
+  F16_LD_ST_HALF_OFF<0x16, (outs), (ins GPR32:$c, GPR32:$b, immU<6>:$off),
+  "sth_s"> {}
+
+//----------------------------------------------------------------------------
+// General compact instructions.
+//----------------------------------------------------------------------------
+def GEN_SUB_S : F16_GEN_DOP<0x02, "sub_s"> {}
+def GEN_AND_S : F16_GEN_DOP<0x04, "and_s"> {}
+def GEN_OR_S : F16_GEN_DOP<0x05, "or_s"> {}
+def GEN_BIC_S : F16_GEN_DOP<0x06, "bic_s"> {}
+def GEN_XOR_S : F16_GEN_DOP<0x07, "xor_s"> {}
+def GEN_MPYW_S : F16_GEN_DOP<0x09, "mpyw_s"> {}
+def GEN_MPYUW_S : F16_GEN_DOP<0x0a, "mpyuw_s"> {}
+def GEN_TST_S : F16_GEN_DOP_NODST<0x0b, "tst_s"> {}
+def GEN_MPY_S : F16_GEN_DOP<0x0c, "mpy_s"> {}
+def GEN_SEXB_S : F16_GEN_DOP_SINGLESRC<0x0d, "sexb_s"> {}
+def GEN_SEXH_S : F16_GEN_DOP_SINGLESRC<0x0e, "sexh_s"> {}
+def GEN_EXTB_S : F16_GEN_DOP_SINGLESRC<0x0f, "extb_s"> {}
+def GEN_EXTH_S : F16_GEN_DOP_SINGLESRC<0x10, "exth_s"> {}
+def GEN_ABS_S : F16_GEN_DOP_SINGLESRC<0x11, "abs_s"> {}
+def GEN_NOT_S : F16_GEN_DOP_SINGLESRC<0x12, "not_s"> {}
+def GEN_NEG_S : F16_GEN_DOP_SINGLESRC<0x13, "neg_s"> {}
+def GEN_ADD1_S : F16_GEN_DOP<0x14, "add1_s"> {}
+def GEN_ADD2_S : F16_GEN_DOP<0x15, "add2_s"> {}
+def GEN_ADD3_S : F16_GEN_DOP<0x16, "add3_s"> {}
+def GEN_ASL_S : F16_GEN_DOP<0x18, "asl_s"> {}
+def GEN_LSR_S : F16_GEN_DOP<0x19, "lsr_s"> {}
+def GEN_ASR_S : F16_GEN_DOP<0x1a, "asr_s"> {}
+def GEN_AS1L_S : F16_GEN_DOP_SINGLESRC<0x1b, "asl_s"> {}
+def GEN_AS1R_S : F16_GEN_DOP_SINGLESRC<0x1c, "asr_s"> {}
+def GEN_LS1R_S : F16_GEN_DOP_SINGLESRC<0x1d, "lsr_s"> {}
+def GEN_TRAP_S : F16_GEN_DOP_BASE<0x1e, (outs), (ins immU6:$u6),
+  "trap_s\t$u6"> {
+
+  bits<6> u6;
+  let b = u6{5-3};
+  let c = u6{2-0};
+}
+
+def GEN_BRK_S : F16_GEN_DOP_BASE<0x1f, (outs), (ins),
+  "brk_s"> {
+
+  let b = 0b111;
+  let c = 0b111;
+}
+
+def GEN_J_S : F16_GEN_SOP<0x0, "j_s\t$b"> {}
+def GEN_J_S_D : F16_GEN_SOP<0x1, "j_s.d\t[$b]"> {}
+def GEN_JL_S : F16_GEN_SOP<0x2, "jl_s\t$b"> {}
+def GEN_JL_S_D : F16_GEN_SOP<0x3, "jl_s.d\t[$b]"> {}
+def GEN_SUB_S_NE : F16_GEN_SOP<0x6, "sub_s.ne\t$b, $b, $b"> {}
+
+def GEN_NOP_S : F16_GEN_ZOP<0x0, "nop_s"> {}
+def GEN_UNIMP_S : F16_GEN_ZOP<0x1, "unimp_s"> {}
+def GEN_SWI_S : F16_GEN_ZOP<0x2, "swi_s"> {}
+def GEN_JEQ_S : F16_GEN_ZOP<0x4, "jeq_s [blink]"> {}
+def GEN_JNE_S : F16_GEN_ZOP<0x5, "jne_s [blink]"> {}
+//def GEN_J_S_BLINK : F16_GEN_ZOP<0x6, "j_s [blink]"> {}
+def GEN_J_S_D_BLINK : F16_GEN_ZOP<0x7, "j_s.d [blink]"> {}
+
+//----------------------------------------------------------------------------
+// Load/Store instructions.
+//----------------------------------------------------------------------------
+
 // Load instruction variants:
 // Control bits: x, aa, di, zz
 // x - sign extend.

 
   def _AB_rs9 : F32_LD_RS9<0, 0b10, 0, zz,
                       (outs GPR32:$addrout, GPR32:$A),
-                      (ins GPR32:$B, immS9:$S9),
+                      (ins GPR32:$B, immS<9>:$S9),
                       !strconcat(asmop, ".ab\t$A, [$B,$S9]"), []>
     { let Constraints = "$addrout = $B"; }
   }

                          !strconcat(asmop, "\t$C, [$addr]"), []>;
 
   def _AW_rs9 : F32_ST_RS9<0b01, 0, zz, (outs GPR32:$addrout),
-                      (ins GPR32:$C, GPR32:$B, immS9:$S9),
+                      (ins GPR32:$C, GPR32:$B, immS<9>:$S9),
                       !strconcat(asmop, ".aw\t$C, [$B,$S9]"), []>
     { let Constraints = "$addrout = $B"; }
   }

ARC/Disassembler/ARCDisassembler.cpp

 
 } // end anonymous namespace
 
-static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
-                              uint64_t &Size, uint32_t &Insn) {
+namespace arc {
+namespace inst_decoder {
+
+bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
+                       uint64_t &Size, uint32_t &Insn) {
   Size = 4;
   // Read 2 16-bit values, but swap hi/lo parts.
   Insn =

   return true;
 }
 
-static bool readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
-                              uint64_t &Size, uint64_t &Insn) {
+bool readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
   Size = 8;
   Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
          ((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |

   return true;
 }
 
-static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
-                              uint64_t &Size, uint32_t &Insn) {
+bool readInstruction48(ArrayRef<uint8_t> Bytes, uint64_t Address,
+                       uint64_t &Size, uint64_t &Insn) {
+  Size = 6;
+  Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
+         ((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
+         ((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
+  return true;
+}
+
+bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
+                       uint64_t &Size, uint32_t &Insn) {
   Size = 2;
   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
   return true;
 }
 
-static MCDisassembler::DecodeStatus DecodeS12Operand(MCInst &, unsigned,
-                                                     uint64_t, const void *);
+template <unsigned B>
+DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
+                                 uint64_t Address = 0,
+                                 const void *Decoder = nullptr);
 
-static MCDisassembler::DecodeStatus DecodeS9Operand(MCInst &, unsigned,
-                                                    uint64_t, const void *);
+template <unsigned B>
+DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, uint64_t Address,
+                                 const void *Decoder);
 
-static MCDisassembler::DecodeStatus
-DecodeBranchTargetS9(MCInst &, unsigned, uint64_t, const void *);
+DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const void *);
 
-static MCDisassembler::DecodeStatus
-DecodeBranchTargetS21(MCInst &, unsigned, uint64_t, const void *);
+DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
+                                     const void *);
 
-static MCDisassembler::DecodeStatus
-DecodeBranchTargetS25(MCInst &, unsigned, uint64_t, const void *);
+DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
+                                     const void *);
 
-static MCDisassembler::DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t,
-                                                 const void *);
+DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
 
-static MCDisassembler::DecodeStatus
-DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t, const void *);
-
-static MCDisassembler::DecodeStatus
-DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, const void *);
-
-static MCDisassembler::DecodeStatus
-DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, const void *);
-
 static const uint16_t GPR32DecoderTable[] = {
     ARC::R0,  ARC::R1,    ARC::R2,  ARC::R3,   ARC::R4,  ARC::R5,  ARC::R6,
     ARC::R7,  ARC::R8,    ARC::R9,  ARC::R10,  ARC::R11, ARC::R12, ARC::R13,

     ARC::R21, ARC::R22,   ARC::R23, ARC::R24,  ARC::R25, ARC::GP,  ARC::FP,
     ARC::SP,  ARC::ILINK, ARC::R30, ARC::BLINK};
 
-static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
-                                             uint64_t Address,
-                                             const void *Decoder) {
+DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                      uint64_t Address, const void *Decoder) {
   if (RegNo >= 32) {
     DEBUG(dbgs() << "Not a GPR32 register.");
     return MCDisassembler::Fail;
   }
+
   unsigned Reg = GPR32DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+DecodeStatus DecodeGPR32ReducedRegister(MCInst &Inst, unsigned RegNo,
+                                        uint64_t Address, const void *Decoder) {
+  // Enumerates registers from ranges [r0-r3],[r12-r15].
+  if (RegNo > 3)
+    RegNo += 8; // 4 for r12, etc...
+
+  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
+}
+} // end namespace inst_decoder
+} // end namespace arc
+
+using namespace arc::inst_decoder;
 #include "ARCGenDisassemblerTables.inc"
 
-static unsigned decodeCField(unsigned Insn) {
+namespace arc {
+namespace inst_decoder {
+
+unsigned decodeCField(unsigned Insn) {
   return fieldFromInstruction(Insn, 6, 6);
 }
 
-static unsigned decodeBField(unsigned Insn) {
+unsigned decodeBField(unsigned Insn) {
   return (fieldFromInstruction(Insn, 12, 3) << 3) |
          fieldFromInstruction(Insn, 24, 3);
 }
 
-static unsigned decodeAField(unsigned Insn) {
+unsigned decodeAField(unsigned Insn) {
   return fieldFromInstruction(Insn, 0, 6);
 }
 
-static MCDisassembler::DecodeStatus
-DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Dec) {
+DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
+                          const void *Dec) {
   // We have the 9-bit immediate in the low bits, 6-bit register in high bits.
   unsigned S9 = Insn & 0x1ff;
   unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;

   return MCDisassembler::Success;
 }
 
-static MCDisassembler::DecodeStatus DecodeS9Operand(MCInst &Inst,
-                                                    unsigned InsnS9,
-                                                    uint64_t Address,
-                                                    const void *Decoder) {
-  Inst.addOperand(MCOperand::createImm(SignExtend32<9>(0x1ff & InsnS9)));
-  return MCDisassembler::Success;
+bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address, uint64_t Value,
+                           const void *Decoder) {
+  static const uint64_t atLeast = 2;
+  // TODO: Try to force emitter to use MCDisassembler* instead of void*.
+  auto Disassembler = reinterpret_cast<const MCDisassembler *>(Decoder);
+  return (nullptr != Disassembler &&
+          Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, 0,
+                                                 atLeast));
 }
 
-static MCDisassembler::DecodeStatus DecodeS12Operand(MCInst &Inst,
-                                                     unsigned InsnS12,
-                                                     uint64_t Address,
-                                                     const void *Decoder) {
-  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(0xfff & InsnS12)));
-  return MCDisassembler::Success;
+void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address, uint64_t Offset,
+                              const void *Decoder) {
+  auto nextAddress = Address + Offset;
+
+  if (!DecodeSymbolicOperand(Inst, Address, nextAddress, Decoder))
+    Inst.addOperand(MCOperand::createImm(nextAddress));
 }
 
-static MCDisassembler::DecodeStatus DecodeBranchTargetS9(MCInst &Inst,
-                                                         unsigned S,
-                                                         uint64_t Address,
-                                                         const void *Decoder) {
-  Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S)));
+template <unsigned B>
+DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, uint64_t Address,
+                                 const void *Decoder) {
+
+  DecodeSymbolicOperandOff(Inst, Address, SignExtend32<B>(InsnS), Decoder);
   return MCDisassembler::Success;
 }
 
-static MCDisassembler::DecodeStatus DecodeBranchTargetS21(MCInst &Inst,
-                                                          unsigned S,
-                                                          uint64_t Address,
-                                                          const void *Decoder) {
-  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(S)));
+template <unsigned B>
+DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
+                                 uint64_t /*Address*/,
+                                 const void * /*Decoder*/) {
+
+  Inst.addOperand(MCOperand::createImm(
+      SignExtend32<B>(maskTrailingOnes<decltype(InsnS)>(B) & InsnS)));
   return MCDisassembler::Success;
 }
 
-static MCDisassembler::DecodeStatus DecodeBranchTargetS25(MCInst &Inst,
-                                                          unsigned S,
-                                                          uint64_t Address,
-                                                          const void *Decoder) {
-  Inst.addOperand(MCOperand::createImm(SignExtend32<25>(S)));
+// TODO: make it lambda when c++17 will be supported.
+constexpr unsigned Factorial(unsigned N) {
+  return N > 0 ? N * Factorial(N - 1) : 1;
+}
+
+template <unsigned B, int Overflow = -1>
+DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
+                                   uint64_t /*Address*/,
+                                   const void * /*Decoder*/) {
+
+  static_assert(B > 0, "field is empty");
+
+  const auto max = Factorial(B);
+  Inst.addOperand(MCOperand::createImm(InsnS <= max ? static_cast<int>(InsnS)
+                                                    : Overflow + InsnS - max));
+
   return MCDisassembler::Success;
 }
 
-static MCDisassembler::DecodeStatus
-DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address,
-                        const void *Decoder) {
+DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
+                                     uint64_t Address, const void *Decoder) {
   unsigned SrcC, DstB, LImm;
   DstB = decodeBField(Insn);
   if (DstB != 62) {

   return MCDisassembler::Success;
 }
 
-static MCDisassembler::DecodeStatus
-DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address,
-                        const void *Decoder) {
+DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
+                                     uint64_t Address, const void *Decoder) {
   unsigned DstA, SrcB, LImm;
   DEBUG(dbgs() << "Decoding LdLImm:\n");
   SrcB = decodeBField(Insn);

   return MCDisassembler::Success;
 }
 
-static MCDisassembler::DecodeStatus
-DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address,
-                         const void *Decoder) {
+DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
+                                      uint64_t Address, const void *Decoder) {
   unsigned DstA, SrcB;
   DEBUG(dbgs() << "Decoding LdRLimm\n");
   DstA = decodeAField(Insn);

   return MCDisassembler::Success;
 }
 
-MCDisassembler::DecodeStatus ARCDisassembler::getInstruction(
-    MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
-    raw_ostream &vStream, raw_ostream &cStream) const {
+// Sequential ranges from lowest to highest.
+template <uint8_t _first, uint8_t _last, uint8_t... _ranges>
+uint64_t ReadFields(uint64_t Insn) {
+  return ReadField<_first, _last>(Insn) |
+         (ReadFields<_ranges...>(Insn) << (_last - _first + 1));
+}
+
+template <class STOP = void> uint64_t ReadFields(uint64_t Insn) { return 0; }
+
+template <uint8_t _first, uint8_t _last> uint64_t ReadField(uint64_t Insn) {
+  static_assert(_first <= _last, "invalid range!");
+  return fieldFromInstruction(Insn, _first, _last - _first + 1);
+}
+
+DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
+                                       uint64_t Address, const void *Decoder) {
+  DEBUG(dbgs() << "Decoding MOV_S h-register\n");
+  //auto h = fieldFromInstruction(Insn, 5, 3) |
+  //         (fieldFromInstruction(Insn, 0, 2) << 3);
+  //auto g = fieldFromInstruction(Insn, 8, 3) |
+  //        (fieldFromInstruction(Insn, 3, 2) << 3);
+  auto h = ReadFields<5, 7, 0, 1>(Insn);
+  auto g = ReadFields<8, 10, 3, 4>(Insn);
+
+  auto DecodeRegisterOrImm = [&Inst, Address, Decoder](decltype(h) field,
+                                                       decltype(Insn) value) {
+    if (30 == field) {
+      Inst.addOperand(MCOperand::createImm(value));
+      return MCDisassembler::Success;
+    }
+
+    return DecodeGPR32RegisterClass(Inst, field, Address, Decoder);
+  };
+
+  if (MCDisassembler::Success != DecodeRegisterOrImm(g, 0))
+    return MCDisassembler::Fail;
+
+  return DecodeRegisterOrImm(h, Insn >> 16u);
+}
+} // end namespace inst_decoder
+} // end namespace arc
+
+DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
+                                             ArrayRef<uint8_t> Bytes,
+                                             uint64_t Address,
+                                             raw_ostream &vStream,
+                                             raw_ostream &cStream) const {
   MCDisassembler::DecodeStatus Result;
   if (Bytes.size() < 2) {
     Size = 0;

         return Fail;
       Result =
           decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);
-      if (Result == MCDisassembler::Success) {
+      if (Success == Result) {
         DEBUG(dbgs() << "Successfully decoded 64-bit instruction.");
-        return MCDisassembler::Success;
+        return Result;
       }
       DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit.");
     }

     }
     // Calling the auto-generated decoder function.
     return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);
+  } else {
+    if (Bytes.size() >= 6) {
+      // Attempt to treat as instr. with limm data.
+      uint64_t Insn48;
+      if (!readInstruction48(Bytes, Address, Size, Insn48))
+        return Fail;
+      Result =
+          decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI);
+      if (Success == Result) {
+        DEBUG(dbgs() << "Successfully decoded 16-bit instruction with limm.");
+        return Result;
+      }
+      DEBUG(dbgs() << "Not a 16-bit instruction with limm, try without it.");
+    }
+    uint32_t Insn16;
+    if (!readInstruction16(Bytes, Address, Size, Insn16)) {
+      return Fail;
+    }
+    // Calling the auto-generated decoder function.
+    return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);
   }
-
-  // 16-bit instruction.
-  uint32_t Insn16;
-  if (!readInstruction16(Bytes, Address, Size, Insn16)) {
-    return Fail;
-  }
-  // Calling the auto-generated decoder function.
-  return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);
 }
 
 static MCDisassembler *createARCDisassembler(const Target &T,

ARC/InstPrinter/ARCInstPrinter.cpp

   int Offset = 0;
   const MCSymbolRefExpr *SRE;
 
+  if (const auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
+    (OS << "0x").write_hex(CE->getValue());
+    return;
+  }
+
   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr)) {
     SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
     const auto *CE = dyn_cast<MCConstantExpr>(BE->getRHS());