[MIPS] Fix PLT entries generation in case of linking regular and microMIPS code

[atanasyan]

Summary

Currently LLD calls the isMicroMips routine to determine type of PLT entries needs to be generated: regular or microMIPS. This routine checks ELF header flags in the FirstObj to retrieve type of linked object files. So if the first file does not contain microMIPS code, LLD will generate PLT entries with regular (non-microMIPS) code only.

Ideally, if a PLT entry is referenced by microMIPS code only this entry should contain microMIPS code, if a PLT entry is referenced by regular code this entry should contain regular code. In a "mixed" case the PLT entry can be either microMIPS or regular, but each "cross-mode-call" has additional cost.

It's rather difficult to implement this ideal solution. But we can assume that if there is an input object file with microMIPS code, the most part of the code is microMIPS too. So we need to deduce type of PLT entries based on finally calculated ELF header flags and do not check only the first input object file.

This change implements this.

• The getMipsEFlags function caches result of ELF flags calculation. Now it's cheap to call it multiple times.
• The isMicroMips and isMipsR6 routines call getMipsEFlags to get and check calculated ELF flags.
• A side effect - these functions become non-template.

[ruiu]

ELF/Arch/Mips.cpp

219–220 ↗

(On Diff #114846)

I'd remove the temporary variable.

return (getMipsEFlags() & EF_MIPS_ARCH_ASE) == EF_MIPS_MICROMIPS;

ELF/Arch/MipsArchTree.cpp

284 ↗

(On Diff #114846)

We do use global variables, but I'd like to reduce usage of it to make it more friendly with embedding, so I wouldn't add a new global variable just for caching. If you do need this, I'd probably add a new member to Config. I don't like to add yet another MIPS-specific member to Config, but that is perhaps still better than adding a new global variable.

[atanasyan]

Address review comments:

• Removed a temporary variable in the isMicroMips function.
• Moved MipsEFlags global variable to the Config. Calculation of its value requires iterating over all input object files so doing that each time when we call getMipsEFlags() is expensive.

[ruiu]

ELF/Arch/MipsArchTree.cpp

296 ↗

(On Diff #115531)

I'd avoid dispatching based on Config->EKind. Can you initialize Config->EKind after all object files are ready?

[atanasyan]

ELF/Arch/MipsArchTree.cpp

296 ↗

(On Diff #115531)

I'd avoid dispatching based on Config->EKind. Can you initialize Config->EKind after all object files are ready?

Do you mean that we need an explicit guarantee that the calcMipsEFlags is called after the Config->EKind initialization? When I code this function I based on an implicit guarantee like in some other existing LLD routines.

[atanasyan]

Ping?

[ruiu]

ELF/Arch/MipsArchTree.cpp

296 ↗

(On Diff #115531)

Do you mean that we need an explicit guarantee that the calcMipsEFlags is called after the Config->EKind initialization?

Yes, what I meant. Then you can remove this dispatch function, no?

[atanasyan]

• Removed getMipsEFlags.
• Call calcMipsEFlags from the LinkerDriver::link to initialize the Configuration::MipsEFlags field.
• Replaced call of the getMipsEFlags by access to the Configuration::MipsEFlags in all other places.

[ruiu]

LGTM

I think this looks much nicer than before. Thank you for making the change.

ELF/Config.h

215 ↗

(On Diff #116924)

cache

lld/trunk/ELF/Arch/Mips.cpp

 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
                                    uint8_t Shift) {
   uint16_t Instr = read16<E>(Loc);
   uint16_t Mask = 0xffff >> (16 - BitsSize);
   uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
   write16<E>(Loc, Data);
 }
 
-template <class ELFT> static bool isMicroMips() {
-  // FIXME (simon): This code does not support the case when both
-  // microMIPS and MIPS object files are linked together.
-  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
-  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
-  return Arch == EF_MIPS_MICROMIPS;
-}
+static bool isMicroMips() { return Config->MipsEFlags & EF_MIPS_MICROMIPS; }
 
-template <class ELFT> static bool isMipsR6() {
-  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
-  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
+static bool isMipsR6() {
+  uint32_t Arch = Config->MipsEFlags & EF_MIPS_ARCH;
   return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
 }
 
 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
   const endianness E = ELFT::TargetEndianness;
-  if (isMicroMips<ELFT>()) {
+  if (isMicroMips()) {
     uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
     uint64_t Plt = In<ELFT>::Plt->getVA();
     // Overwrite trap instructions written by Writer::writeTrapInstr.
     memset(Buf, 0, PltHeaderSize);
 
-    write16<E>(Buf, isMipsR6<ELFT>() ? 0x7860 : 0x7980);
-                                    // addiupc v1, (GOTPLT) - .
+    write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980);  // addiupc v1, (GOTPLT) - .
     write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
     write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
     write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
     write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
     write16<E>(Buf + 14, 0xfffe);
     write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
-    if (isMipsR6<ELFT>()) {
+    if (isMipsR6()) {
       write16<E>(Buf + 18, 0x0f83); // move    $28, $3
       write16<E>(Buf + 20, 0x472b); // jalrc   $25
       write16<E>(Buf + 22, 0x0c00); // nop
       relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
     } else {
       write16<E>(Buf + 18, 0x45f9); // jalrc   $25
       write16<E>(Buf + 20, 0x0f83); // move    $28, $3
       write16<E>(Buf + 22, 0x0c00); // nop
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
   writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
 }
 
 template <class ELFT>
 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
                           uint64_t PltEntryAddr, int32_t Index,
                           unsigned RelOff) const {
   const endianness E = ELFT::TargetEndianness;
-  if (isMicroMips<ELFT>()) {
+  if (isMicroMips()) {
     // Overwrite trap instructions written by Writer::writeTrapInstr.
     memset(Buf, 0, PltEntrySize);
 
-    if (isMipsR6<ELFT>()) {
+    if (isMipsR6()) {
       write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
       write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
       write16<E>(Buf + 8, 0x0f02);  // move $24, $2
       write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
       relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
     } else {
       write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
       write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
       write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
       write16<E>(Buf + 10, 0x0f02); // move $24, $2
       relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
     }
     return;
   }
 
   write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
   write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
-                                   // jr    $25
-  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008);
+  write32<E>(Buf + 8, isMipsR6() ? 0x03200009 : 0x03200008);  // jr  $25
   write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
   writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
   writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
   writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
 }
 
 template <class ELFT>
 bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File,

lld/trunk/ELF/Arch/MipsArchTree.cpp

if (!isArchMatched(Ret, New)) {
             getArchName(New) + "': " + F.Filename);
       return 0;
     }
     Ret = New;
   }
   return Ret;
 }
 
-template <class ELFT> uint32_t elf::getMipsEFlags() {
+template <class ELFT> uint32_t elf::calcMipsEFlags() {
   std::vector<FileFlags> V;
   for (InputFile *F : ObjectFiles)
     V.push_back(
         {F->getName(), cast<ObjFile<ELFT>>(F)->getObj().getHeader()->e_flags});
   if (V.empty())
     return 0;
   checkFlags(V);
   return getMiscFlags(V) | getPicFlags(V) | getArchFlags(V);
case ELF64LEKind:
     return isN32Abi<ELF64LE>(F);
   case ELF64BEKind:
     return isN32Abi<ELF64BE>(F);
   default:
     llvm_unreachable("unknown Config->EKind");
   }
 }
 
-template uint32_t elf::getMipsEFlags<ELF32LE>();
-template uint32_t elf::getMipsEFlags<ELF32BE>();
-template uint32_t elf::getMipsEFlags<ELF64LE>();
-template uint32_t elf::getMipsEFlags<ELF64BE>();
+template uint32_t elf::calcMipsEFlags<ELF32LE>();
+template uint32_t elf::calcMipsEFlags<ELF32BE>();
+template uint32_t elf::calcMipsEFlags<ELF64LE>();
+template uint32_t elf::calcMipsEFlags<ELF64BE>();

lld/trunk/ELF/Config.h

struct Configuration {
   // not in various places.
   //
   // (Note that MIPS64EL is not a typo for MIPS64LE. This is the official
   // name whatever that means. A fun hypothesis is that "EL" is short for
   // little-endian written in the little-endian order, but I don't know
   // if that's true.)
   bool IsMips64EL;
 
+  // Holds set of ELF header flags for MIPS targets. The set calculated
+  // by the `elf::calcMipsEFlags` function and cached in this field. For
+  // the calculation we iterate over all input object files and combine
+  // their ELF flags.
+  uint32_t MipsEFlags = 0;
+
   // The ELF spec defines two types of relocation table entries, RELA and
   // REL. RELA is a triplet of (offset, info, addend) while REL is a
   // tuple of (offset, info). Addends for REL are implicit and read from
   // the location where the relocations are applied. So, REL is more
   // compact than RELA but requires a bit of more work to process.
   //
   // (From the linker writer's view, this distinction is not necessary.
   // If the ELF had chosen whichever and sticked with it, it would have

lld/trunk/ELF/Driver.cpp

template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
   for (InputFile *F : ObjectFiles)
     for (InputSectionBase *S : F->getSections())
       if (S && S != &InputSection::Discarded)
         InputSections.push_back(S);
   for (BinaryFile *F : BinaryFiles)
     for (InputSectionBase *S : F->getSections())
       InputSections.push_back(cast<InputSection>(S));
 
+  if (Config->EMachine == EM_MIPS)
+    Config->MipsEFlags = calcMipsEFlags<ELFT>();
+
   // This adds a .comment section containing a version string. We have to add it
   // before decompressAndMergeSections because the .comment section is a
   // mergeable section.
   if (!Config->Relocatable)
     InputSections.push_back(createCommentSection<ELFT>());
 
   // Create a .bss section for each common symbol and then replace the common
   // symbol with a DefinedRegular symbol. As a result, all common symbols are

lld/trunk/ELF/SyntheticSections.cpp

for (InputSectionBase *Sec : InputSections) {
     }
     auto *S = reinterpret_cast<const Elf_Mips_ABIFlags *>(Sec->Data.data());
     if (S->version != 0) {
       error(Filename + ": unexpected .MIPS.abiflags version " +
             Twine(S->version));
       return nullptr;
     }
 
-    // LLD checks ISA compatibility in getMipsEFlags(). Here we just
+    // LLD checks ISA compatibility in calcMipsEFlags(). Here we just
     // select the highest number of ISA/Rev/Ext.
     Flags.isa_level = std::max(Flags.isa_level, S->isa_level);
     Flags.isa_rev = std::max(Flags.isa_rev, S->isa_rev);
     Flags.isa_ext = std::max(Flags.isa_ext, S->isa_ext);
     Flags.gpr_size = std::max(Flags.gpr_size, S->gpr_size);
     Flags.cpr1_size = std::max(Flags.cpr1_size, S->cpr1_size);
     Flags.cpr2_size = std::max(Flags.cpr2_size, S->cpr2_size);
     Flags.ases |= S->ases;

lld/trunk/ELF/Writer.h

struct PhdrEntry {
 
   OutputSection *FirstSec = nullptr;
   OutputSection *LastSec = nullptr;
   bool HasLMA = false;
 };
 
 llvm::StringRef getOutputSectionName(llvm::StringRef Name);
 
-template <class ELFT> uint32_t getMipsEFlags();
+template <class ELFT> uint32_t calcMipsEFlags();
 
 uint8_t getMipsFpAbiFlag(uint8_t OldFlag, uint8_t NewFlag,
                          llvm::StringRef FileName);
 
 bool isMipsN32Abi(const InputFile *F);
 } // namespace elf
 } // namespace lld
 
 #endif

lld/trunk/ELF/Writer.cpp

template <class ELFT> void Writer<ELFT>::writeHeader() {
   EHdr->e_shstrndx = InX::ShStrTab->getParent()->SectionIndex;
 
   if (Config->EMachine == EM_ARM)
     // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
     // but we don't have any firm guarantees of conformance. Linux AArch64
     // kernels (as of 2016) require an EABI version to be set.
     EHdr->e_flags = EF_ARM_EABI_VER5;
   else if (Config->EMachine == EM_MIPS)
-    EHdr->e_flags = getMipsEFlags<ELFT>();
+    EHdr->e_flags = Config->MipsEFlags;
 
   if (!Config->Relocatable) {
     EHdr->e_phoff = sizeof(Elf_Ehdr);
     EHdr->e_phentsize = sizeof(Elf_Phdr);
   }
 
   // Write the program header table.
   auto *HBuf = reinterpret_cast<Elf_Phdr *>(Buf + EHdr->e_phoff);

lld/trunk/test/ELF/mips-elf-flags.s

 # RUN:   | FileCheck -check-prefix=EXE-R6 %s
 
 # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
 # RUN:         -position-independent -mcpu=octeon %s -o %t.o
 # RUN: ld.lld %t.o -o %t.exe
 # RUN: llvm-readobj -h -mips-abi-flags %t.exe \
 # RUN:   | FileCheck -check-prefix=OCTEON %s
 
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         -mattr=micromips %S/Inputs/mips-fpic.s -o %t-mm.o
+# RUN: ld.lld %t.o %t-mm.o -o %t.exe
+# RUN: llvm-readobj -h -mips-abi-flags %t.exe | FileCheck -check-prefix=MICRO %s
+
 # REQUIRES: mips
 
   .text
   .globl  __start
 __start:
   nop
 
 # SO:      Flags [

 # OCTEON-NEXT:   GPR size: 64
 # OCTEON-NEXT:   CPR1 size: 64
 # OCTEON-NEXT:   CPR2 size: 0
 # OCTEON-NEXT:   Flags 1 [
 # OCTEON-NEXT:     ODDSPREG
 # OCTEON-NEXT:   ]
 # OCTEON-NEXT:   Flags 2: 0x0
 # OCTEON-NEXT: }
+
+# MICRO:      Flags [
+# MICRO-NEXT:   EF_MIPS_ABI_O32
+# MICRO-NEXT:   EF_MIPS_ARCH_32
+# MICRO-NEXT:   EF_MIPS_CPIC
+# MICRO-NEXT:   EF_MIPS_MICROMIPS
+# MICRO-NEXT: ]
+# MICRO:      MIPS ABI Flags {
+# MICRO-NEXT:   Version: 0
+# MICRO-NEXT:   ISA: MIPS32
+# MICRO-NEXT:   ISA Extension: None
+# MICRO-NEXT:   ASEs [
+# MICRO-NEXT:     microMIPS
+# MICRO-NEXT:   ]
+# MICRO-NEXT:   FP ABI: Hard float (double precision)
+# MICRO-NEXT:   GPR size: 32
+# MICRO-NEXT:   CPR1 size: 32
+# MICRO-NEXT:   CPR2 size: 0
+# MICRO-NEXT:   Flags 1 [
+# MICRO-NEXT:     ODDSPREG
+# MICRO-NEXT:   ]
+# MICRO-NEXT:   Flags 2: 0x0
+# MICRO-NEXT: }

lld/trunk/test/ELF/mips-micro-jal.s

 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips -mcpu=mips32r6 %S/Inputs/mips-micro.s -o %t1el.o
 # RUN: ld.lld -shared -o %tel.so %t1el.o
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips -mcpu=mips32r6 %s -o %t2el.o
 # RUN: ld.lld -o %tel.exe %t2el.o %tel.so
 # RUN: llvm-objdump -d -mattr=micromips %tel.exe | FileCheck --check-prefix=ELR6 %s
 
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         -mattr=micromips %S/Inputs/mips-micro.s -o %t1eb.o
+# RUN: ld.lld -shared -o %teb.so %t1eb.o
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         %S/Inputs/mips-fpic.s -o %t-reg.o
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         -mattr=micromips %s -o %t2eb.o
+# RUN: ld.lld --no-threads -o %teb.exe %t-reg.o %t2eb.o %teb.so
+# RUN: llvm-objdump -d -mattr=micromips %teb.exe \
+# RUN:   | FileCheck --check-prefix=MIXED %s
+
 # REQUIRES: mips
 
 # EB:      Disassembly of section .plt:
 # EB-NEXT: .plt:
 # EB-NEXT:    20010:       79 80 3f fd     addiupc $3, 65524
 # EB-NEXT:    20014:       ff 23 00 00     lw      $25, 0($3)
 # EB-NEXT:    20018:       05 35           subu16  $2, $2, $3
 # EB-NEXT:    2001a:       25 25           srl16   $2, $2, 2

 # ELR6-NEXT:    20022:       83 0f           move16  $gp, $3
 # ELR6-NEXT:    20024:       2b 47           jalr    $25
 
 # ELR6:         20030:       40 78 f7 3f     lapc    $2, 65500
 # ELR6-NEXT:    20034:       22 ff 00 00     lw      $25, 0($2)
 # ELR6-NEXT:    20038:       02 0f           move16  $24, $2
 # ELR6-NEXT:    2003a:       23 47           jrc16   $25
 
+# MIXED:      Disassembly of section .plt:
+# MIXED-NEXT: .plt:
+# MIXED-NEXT:    20020:       79 80 3f f9     addiupc $3, 65508
+# MIXED-NEXT:    20024:       ff 23 00 00     lw      $25, 0($3)
+# MIXED-NEXT:    20028:       05 35           subu16  $2, $2, $3
+# MIXED-NEXT:    2002a:       25 25           srl16   $2, $2, 2
+# MIXED-NEXT:    2002c:       33 02 ff fe     addiu   $24, $2, -2
+# MIXED-NEXT:    20030:       0d ff           move    $15, $ra
+# MIXED-NEXT:    20032:       45 f9           jalrs16 $25
+# MIXED-NEXT:    20034:       0f 83           move    $gp, $3
+# MIXED-NEXT:    20036:       0c 00           nop
+# MIXED-NEXT:    20038:       00 00 00 00     nop
+# MIXED-NEXT:    2003c:       00 00 00 00     nop
+
+# MIXED-NEXT:    20040:       79 00 3f f3     addiupc $2, 65484
+# MIXED-NEXT:    20044:       ff 22 00 00     lw      $25, 0($2)
+# MIXED-NEXT:    20048:       45 99           jr16    $25
+# MIXED-NEXT:    2004a:       0f 02           move    $24, $2
+
 # PLT:      Entries [
 # PLT-NEXT:   Entry {
 # PLT-NEXT:     Address: 0x3000C
 #                        ^ 0x20030 + 65500
 # PLT-NEXT:     Initial:
 # PLT-NEXT:     Value: 0x0
 # PLT-NEXT:     Type: Function
 # PLT-NEXT:     Section: Undefined