PPC: Don't select lxv/stxv for insufficiently aligned stack slots.
AcceptedPublic

Authored by iteratee on Sep 8 2017, 4:56 PM.

Details

Summary

The lxv/stxv instructions require an offset that is 0 % 16. Previously we were
selecting lxv/stxv for loads and stores to the stack where the offset from the
slot was a multiple of 16, but the stack slot was not 16 or more byte aligned.
When the frame gets lowered these transform to r(1|31) + slot + offset.
If slot is not aligned, slot + offset may not be 0 % 16.
Now we require 16 byte or more alignment for select lxv/stxv to stack slots.

Includes a testcase that shows both sufficiently and insufficiently aligned
stack slots.

Diff Detail

Repository
rL LLVM
iteratee created this revision.Sep 8 2017, 4:56 PM
echristo accepted this revision.Sep 8 2017, 5:00 PM

Couple inline comments, first should be handled, otherwise looks OK to me.

-eric

lib/Target/PowerPC/PPCISelDAGToDAG.cpp
3063

if (FrameIndexSDNode *FI = dyn_cast<....> ...) {
}

3064–3066

Can probably merge some of the single use variables here, but I also don't mind if you want to keep them :)

This revision is now accepted and ready to land.Sep 8 2017, 5:00 PM
hfinkel accepted this revision.Sep 8 2017, 5:03 PM
hfinkel added a subscriber: hfinkel.

LGTM.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp
3059

if -> If

I imagine this patch was prompted by a bug. Just out of curiosity, did the assert:

assert(MO.isImm() && !(MO.getImm() % 16) &&
       "Expecting an immediate that is a multiple of 16");

fire for the case where the frame op was lowered to an lxv/stxv with an offset that isn't a multiple of 16? If not, perhaps we need another assert somewhere else?