[AMDGPU] Fix legalization of VOP3P

[rampitec]

Summary

I am figuring out if I can create a relevant test now.

[rampitec]

Actually it seems I have misread the documentation. VOP3P still cannot have literals other than inline constants.
I will remove the part about the legalization, but need to keep isOperandLegal part.

[rampitec]

In fact this is all not needed. We just cannot produce such instructions and the testcase was artificial with the bogus td file change.

lib/Target/AMDGPU/SIInstrInfo.cpp

for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       if (i == OpIdx)
         continue;
       const MachineOperand &Op = MI.getOperand(i);
       if (Op.isReg()) {
         if ((Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg) &&
             usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
           return false;
         }
-      } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
+      } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 ||
+                 InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM16) {
+        return false;
+      } else if (Op.isImm() && !isInlineConstant(Op, OpInfo) &&
+                 InstDesc.OpInfo[i].OperandType >= AMDGPU::OPERAND_SRC_FIRST &&
+                 InstDesc.OpInfo[i].OperandType <= AMDGPU::OPERAND_SRC_LAST) {
         return false;
       }
     }
   }
 
   if (MO->isReg()) {
     assert(DefinedRC);
     return isLegalRegOperand(MRI, OpInfo, *MO);
else if (Src1.isReg()) {
     Src0.setSubReg(Src1.getSubReg());
   } else
     llvm_unreachable("Should only have register or immediate operands");
 
   Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
   Src1.setSubReg(Src0SubReg);
 }
 
-// Legalize VOP3 operands. Because all operand types are supported for any
-// operand, and since literal constants are not allowed and should never be
-// seen, we only need to worry about inserting copies if we use multiple SGPR
-// operands.
 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
                                        MachineInstr &MI) const {
   unsigned Opc = MI.getOpcode();
+  const SIRegisterInfo *TRI =
+      static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
+
 
   int VOP3Idx[3] = {
     AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
     AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
     AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
   };
 
   // Find the one SGPR operand we are allowed to use.
   unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
+  bool ConstantBusUsed = (SGPRReg != AMDGPU::NoRegister);
 
   for (unsigned i = 0; i < 3; ++i) {
     int Idx = VOP3Idx[i];
     if (Idx == -1)
       break;
     MachineOperand &MO = MI.getOperand(Idx);
 
-    // We should never see a VOP3 instruction with an illegal immediate operand.
+    if (MO.isImm()) {
+      auto OpType = get(Opc).OpInfo[Idx].OperandType;
+      if (TRI->opCanUseInlineConstant(OpType) && isInlineConstant(MO, OpType))
+        continue;
+      if (ConstantBusUsed)
+        legalizeOpWithMove(MI, Idx);
+      ConstantBusUsed = true;
+      continue;
+    }
+
     if (!MO.isReg())
       continue;
 
     if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
       continue; // VGPRs are legal
 
-    if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
-      SGPRReg = MO.getReg();
-      // We can use one SGPR in each VOP3 instruction.
+    // We can use one SGPR or one immediate in each VOP3P instruction.
+    if (SGPRReg == MO.getReg())
+      continue;
+
+    if (SGPRReg == AMDGPU::NoRegister && !ConstantBusUsed) {
+      SGPRReg = MO.getReg();
+      ConstantBusUsed = true;
       continue;
     }
 
     // If we make it this far, then the operand is not legal and we must
     // legalize it.
     legalizeOpWithMove(MI, Idx);
   }
 }