AMDGPU: Don't look for DS merge candidates with one use address

[arsenm]

Summary

The merge is only possible if the base address register is the
same for the two instructions. If there is only the one use,
there's no point in doing an expensive forward scan checking
for memory interference looking for a merge candidate.

This gives a signficant improvement in one extreme testcase.
The code to do the scan is still algorithmically terrible,
so this is still the slowest pass in that example.

[rampitec]

LGTM

[arsenm]

r312096

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI) {
   }
 
   return false;
 }
 
 bool SILoadStoreOptimizer::findMatchingDSInst(CombineInfo &CI) {
   MachineBasicBlock::iterator E = CI.I->getParent()->end();
   MachineBasicBlock::iterator MBBI = CI.I;
+
+  int AddrIdx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(),
+                                           AMDGPU::OpName::addr);
+  const MachineOperand &AddrReg0 = CI.I->getOperand(AddrIdx);
+
+  // We only ever merge operations with the same base address register, so don't
+  // bother scanning forward if there are no other uses.
+  if (MRI->hasOneNonDBGUse(AddrReg0.getReg()))
+    return false;
+
   ++MBBI;
 
   SmallVector<const MachineOperand *, 8> DefsToMove;
   addDefsToList(*CI.I, DefsToMove);
 
   for ( ; MBBI != E; ++MBBI) {
     if (MBBI->getOpcode() != CI.I->getOpcode()) {
       // This is not a matching DS instruction, but we can keep looking as
for ( ; MBBI != E; ++MBBI) {
     //   DS_WRITE_B32 addr, v, idx0
     //   w = DS_READ_B32 addr, idx0
     //   DS_WRITE_B32 addr, f(w), idx1
     // where the DS_READ_B32 ends up in InstsToMove and therefore prevents
     // merging of the two writes.
     if (addToListsIfDependent(*MBBI, DefsToMove, CI.InstsToMove))
       continue;
 
-    int AddrIdx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(),
-                                             AMDGPU::OpName::addr);
-    const MachineOperand &AddrReg0 = CI.I->getOperand(AddrIdx);
     const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
 
     // Check same base pointer. Be careful of subregisters, which can occur with
     // vectors of pointers.
     if (AddrReg0.getReg() == AddrReg1.getReg() &&
         AddrReg0.getSubReg() == AddrReg1.getSubReg()) {
       int OffsetIdx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(),
                                                  AMDGPU::OpName::offset);